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From: Anson Jacob <Anson.Jacob@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: <Harry.Wentland@amd.com>, <Sunpeng.Li@amd.com>,
	<Bhawanpreet.Lakha@amd.com>, <Rodrigo.Siqueira@amd.com>,
	<Aurabindo.Pillai@amd.com>, <qingqing.zhuo@amd.com>,
	<mikita.lipski@amd.com>,  <roman.li@amd.com>,
	<Anson.Jacob@amd.com>, <wayne.lin@amd.com>, <stylon.wang@amd.com>,
	<solomon.chiu@amd.com>, Wenjing Liu <wenjing.liu@amd.com>,
	Jun Lei <Jun.Lei@amd.com>
Subject: [PATCH 09/24] drm/amd/display: rename lane_settings to hw_lane_settings
Date: Fri, 24 Sep 2021 15:09:19 -0400	[thread overview]
Message-ID: <20210924190934.1193379-10-Anson.Jacob@amd.com> (raw)
In-Reply-To: <20210924190934.1193379-1-Anson.Jacob@amd.com>

From: Wenjing Liu <wenjing.liu@amd.com>

[why]
This is one of the major steps to decouple hw lane settings
from dpcd lane settings.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c |  8 ++--
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 38 +++++++++----------
 .../drm/amd/display/dc/core/dc_link_hwss.c    |  4 +-
 .../drm/amd/display/dc/dce/dce_link_encoder.c |  6 +--
 .../amd/display/dc/dcn10/dcn10_link_encoder.c |  6 +--
 .../amd/display/include/link_service_types.h  | 16 +++++++-
 6 files changed, 46 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 814f67d86a3c..7ceb4a14fa2a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -535,11 +535,11 @@ static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf,
 
 	/* apply phy settings from user */
 	for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) {
-		link_lane_settings.lane_settings[r].VOLTAGE_SWING =
+		link_lane_settings.hw_lane_settings[r].VOLTAGE_SWING =
 				(enum dc_voltage_swing) (param[0]);
-		link_lane_settings.lane_settings[r].PRE_EMPHASIS =
+		link_lane_settings.hw_lane_settings[r].PRE_EMPHASIS =
 				(enum dc_pre_emphasis) (param[1]);
-		link_lane_settings.lane_settings[r].POST_CURSOR2 =
+		link_lane_settings.hw_lane_settings[r].POST_CURSOR2 =
 				(enum dc_post_cursor2) (param[2]);
 	}
 
@@ -733,7 +733,7 @@ static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __us
 	}
 
 	for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++)
-		link_training_settings.lane_settings[i] = link->cur_lane_setting[i];
+		link_training_settings.hw_lane_settings[i] = link->cur_lane_setting[i];
 
 	dc_link_set_test_pattern(
 		link,
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 8e6af080cbe9..84eabdca8b24 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -554,7 +554,7 @@ static void dpcd_set_lt_pattern_and_lane_settings(
 			dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 	}
 
-	dp_hw_to_dpcd_lane_settings(lt_settings, lt_settings->lane_settings, dpcd_lane);
+	dp_hw_to_dpcd_lane_settings(lt_settings, lt_settings->hw_lane_settings, dpcd_lane);
 
 	/* concatenate everything into one buffer*/
 
@@ -926,7 +926,7 @@ enum dc_status dpcd_set_lane_settings(
 		((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 
 	dp_hw_to_dpcd_lane_settings(link_training_setting,
-			link_training_setting->lane_settings,
+			link_training_setting->hw_lane_settings,
 			dpcd_lane);
 
 	status = core_link_write_dpcd(link,
@@ -1006,7 +1006,7 @@ bool dp_is_max_vs_reached(
 	for (lane = 0; lane <
 		(uint32_t)(lt_settings->link_settings.lane_count);
 		lane++) {
-		if (lt_settings->lane_settings[lane].VOLTAGE_SWING
+		if (lt_settings->hw_lane_settings[lane].VOLTAGE_SWING
 			== VOLTAGE_SWING_MAX_LEVEL)
 			return true;
 	}
@@ -1065,9 +1065,9 @@ static bool perform_post_lt_adj_req_sequence(
 			for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
 
 				if (lt_settings->
-				lane_settings[lane].VOLTAGE_SWING !=
+				hw_lane_settings[lane].VOLTAGE_SWING !=
 				dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_LANE ||
-				lt_settings->lane_settings[lane].PRE_EMPHASIS !=
+				lt_settings->hw_lane_settings[lane].PRE_EMPHASIS !=
 				dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_LANE) {
 
 					req_drv_setting_changed = true;
@@ -1077,7 +1077,7 @@ static bool perform_post_lt_adj_req_sequence(
 
 			if (req_drv_setting_changed) {
 				dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
-						lt_settings->lane_settings, dpcd_lane_settings);
+						lt_settings->hw_lane_settings, dpcd_lane_settings);
 
 				dc_link_dp_set_drive_settings(link,
 						lt_settings);
@@ -1233,7 +1233,7 @@ static enum link_training_result perform_channel_equalization_sequence(
 
 		/* 7. update VS/PE/PC2 in lt_settings*/
 		dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
-				lt_settings->lane_settings, dpcd_lane_settings);
+				lt_settings->hw_lane_settings, dpcd_lane_settings);
 	}
 
 	return LINK_TRAINING_EQ_FAIL_EQ;
@@ -1344,12 +1344,12 @@ static enum link_training_result perform_clock_recovery_sequence(
 		/* Note: settings are the same for all lanes,
 		 * so comparing first lane is sufficient*/
 		if ((dp_get_link_encoding_format(&lt_settings->link_settings) == DP_8b_10b_ENCODING) &&
-				lt_settings->lane_settings[0].VOLTAGE_SWING ==
+				lt_settings->hw_lane_settings[0].VOLTAGE_SWING ==
 						dpcd_lane_adjust[0].bits.VOLTAGE_SWING_LANE)
 			retries_cr++;
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 		else if ((dp_get_link_encoding_format(&lt_settings->link_settings) == DP_128b_132b_ENCODING) &&
-				lt_settings->lane_settings[0].FFE_PRESET.settings.level ==
+				lt_settings->hw_lane_settings[0].FFE_PRESET.settings.level ==
 						dpcd_lane_adjust[0].tx_ffe.PRESET_VALUE)
 			retries_cr++;
 #endif
@@ -1358,7 +1358,7 @@ static enum link_training_result perform_clock_recovery_sequence(
 
 		/* 8. update VS/PE/PC2 in lt_settings*/
 		dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
-				lt_settings->lane_settings, dpcd_lane_settings);
+				lt_settings->hw_lane_settings, dpcd_lane_settings);
 
 		retry_count++;
 	}
@@ -1561,15 +1561,15 @@ static void override_training_settings(
 #endif
 
 	for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
-		lt_settings->lane_settings[lane].VOLTAGE_SWING =
+		lt_settings->hw_lane_settings[lane].VOLTAGE_SWING =
 			lt_settings->voltage_swing != NULL ?
 			*lt_settings->voltage_swing :
 			VOLTAGE_SWING_LEVEL0;
-		lt_settings->lane_settings[lane].PRE_EMPHASIS =
+		lt_settings->hw_lane_settings[lane].PRE_EMPHASIS =
 			lt_settings->pre_emphasis != NULL ?
 			*lt_settings->pre_emphasis
 			: PRE_EMPHASIS_DISABLED;
-		lt_settings->lane_settings[lane].POST_CURSOR2 =
+		lt_settings->hw_lane_settings[lane].POST_CURSOR2 =
 			lt_settings->post_cursor2 != NULL ?
 			*lt_settings->post_cursor2
 			: POST_CURSOR2_DISABLED;
@@ -1826,8 +1826,8 @@ static void print_status_message(
 				link_rate,
 				lt_settings->link_settings.lane_count,
 				lt_result,
-				lt_settings->lane_settings[0].VOLTAGE_SWING,
-				lt_settings->lane_settings[0].PRE_EMPHASIS,
+				lt_settings->hw_lane_settings[0].VOLTAGE_SWING,
+				lt_settings->hw_lane_settings[0].PRE_EMPHASIS,
 				lt_spread);
 }
 
@@ -1982,7 +1982,7 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence(
 	dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
 			&dpcd_lane_status_updated, dpcd_lane_adjust, DPRX);
 	dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
-			lt_settings->lane_settings, dpcd_lane_settings);
+			lt_settings->hw_lane_settings, dpcd_lane_settings);
 	dpcd_128b_132b_get_aux_rd_interval(link, &aux_rd_interval);
 	dp_set_hw_lane_settings(link, lt_settings, DPRX);
 	dpcd_set_lane_settings(link, lt_settings, DPRX);
@@ -1999,7 +1999,7 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence(
 		dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
 				&dpcd_lane_status_updated, dpcd_lane_adjust, DPRX);
 		dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
-				lt_settings->lane_settings, dpcd_lane_settings);
+				lt_settings->hw_lane_settings, dpcd_lane_settings);
 		dpcd_128b_132b_get_aux_rd_interval(link, &aux_rd_interval);
 		if (dp_is_ch_eq_done(lt_settings->link_settings.lane_count,
 				dpcd_lane_status)) {
@@ -2113,7 +2113,7 @@ static enum link_training_result dp_perform_8b_10b_link_training(
 		}
 
 		for (lane = 0; lane < (uint8_t)lt_settings->link_settings.lane_count; lane++)
-			lt_settings->lane_settings[lane].VOLTAGE_SWING = VOLTAGE_SWING_LEVEL0;
+			lt_settings->hw_lane_settings[lane].VOLTAGE_SWING = VOLTAGE_SWING_LEVEL0;
 	}
 
 	if (status == LINK_TRAINING_SUCCESS) {
@@ -3628,7 +3628,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
 	}
 
 	for (i = 0; i < 4; i++)
-		link_training_settings.lane_settings[i] =
+		link_training_settings.hw_lane_settings[i] =
 				link_settings.lane_settings[i];
 	link_training_settings.link_settings = link_settings.link;
 	link_training_settings.allow_invalid_msa_timing_param = false;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 368e834c6809..2666af299bc2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -364,7 +364,7 @@ void dp_set_hw_lane_settings(
 		link->hpo_dp_link_enc->funcs->set_ffe(
 				link->hpo_dp_link_enc,
 				&link_settings->link_settings,
-				link_settings->lane_settings[0].FFE_PRESET.raw);
+				link_settings->hw_lane_settings[0].FFE_PRESET.raw);
 	} else if (dp_get_link_encoding_format(&link_settings->link_settings)
 			== DP_8b_10b_ENCODING) {
 		encoder->funcs->dp_set_lane_settings(encoder, link_settings);
@@ -373,7 +373,7 @@ void dp_set_hw_lane_settings(
 	encoder->funcs->dp_set_lane_settings(encoder, link_settings);
 #endif
 	memmove(link->cur_lane_setting,
-			link_settings->lane_settings,
+			link_settings->hw_lane_settings,
 			sizeof(link->cur_lane_setting));
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index 1e77ffee71b3..af4dcd6714cf 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -1348,9 +1348,9 @@ void dce110_link_encoder_dp_set_lane_settings(
 		/* translate lane settings */
 
 		training_lane_set.bits.VOLTAGE_SWING_SET =
-			link_settings->lane_settings[lane].VOLTAGE_SWING;
+			link_settings->hw_lane_settings[lane].VOLTAGE_SWING;
 		training_lane_set.bits.PRE_EMPHASIS_SET =
-			link_settings->lane_settings[lane].PRE_EMPHASIS;
+			link_settings->hw_lane_settings[lane].PRE_EMPHASIS;
 
 		/* post cursor 2 setting only applies to HBR2 link rate */
 		if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) {
@@ -1358,7 +1358,7 @@ void dce110_link_encoder_dp_set_lane_settings(
 			 * to program post cursor 2 level */
 
 			training_lane_set.bits.POST_CURSOR2_SET =
-				link_settings->lane_settings[lane].POST_CURSOR2;
+				link_settings->hw_lane_settings[lane].POST_CURSOR2;
 		}
 
 		cntl.lane_select = lane;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
index 2dc4b4e4ba02..a8982ae7e876 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
@@ -1124,9 +1124,9 @@ void dcn10_link_encoder_dp_set_lane_settings(
 		/* translate lane settings */
 
 		training_lane_set.bits.VOLTAGE_SWING_SET =
-			link_settings->lane_settings[lane].VOLTAGE_SWING;
+			link_settings->hw_lane_settings[lane].VOLTAGE_SWING;
 		training_lane_set.bits.PRE_EMPHASIS_SET =
-			link_settings->lane_settings[lane].PRE_EMPHASIS;
+			link_settings->hw_lane_settings[lane].PRE_EMPHASIS;
 
 		/* post cursor 2 setting only applies to HBR2 link rate */
 		if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) {
@@ -1134,7 +1134,7 @@ void dcn10_link_encoder_dp_set_lane_settings(
 			 * to program post cursor 2 level
 			 */
 			training_lane_set.bits.POST_CURSOR2_SET =
-				link_settings->lane_settings[lane].POST_CURSOR2;
+				link_settings->hw_lane_settings[lane].POST_CURSOR2;
 		}
 
 		cntl.lane_select = lane;
diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h
index 9ffea7b40545..007274e73347 100644
--- a/drivers/gpu/drm/amd/display/include/link_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/link_service_types.h
@@ -90,7 +90,6 @@ enum lttpr_mode {
 
 struct link_training_settings {
 	struct dc_link_settings link_settings;
-	struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];
 
 	enum dc_voltage_swing *voltage_swing;
 	enum dc_pre_emphasis *pre_emphasis;
@@ -117,6 +116,21 @@ struct link_training_settings {
 	bool enhanced_framing;
 	bool allow_invalid_msa_timing_param;
 	enum lttpr_mode lttpr_mode;
+
+
+	/* TODO: Move hw_lane_settings along with lane adjust,
+	 * lane align, offset and all other training states
+	 * into a new structure called link training states,
+	 * so link_training_settings becomes a constant input
+	 * pre-decided prior to link training.
+	 *
+	 * The goal is to strictly decouple link training settings
+	 * decision making process from link training states to
+	 * prevent it from messy code practice of changing training
+	 * decision on the fly.
+	 */
+	struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX];
+
 };
 
 /*TODO: Move this enum test harness*/
-- 
2.25.1


  parent reply	other threads:[~2021-09-24 19:10 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-24 19:09 [PATCH 00/24] DC Patches Sep 24, 2021 Anson Jacob
2021-09-24 19:09 ` [PATCH 01/24] drm/amd/display: use correct vpg instance for 128b/132b encoding Anson Jacob
2021-09-24 19:09 ` [PATCH 02/24] drm/amd/display: [FW Promotion] Release 0.0.85 Anson Jacob
2021-09-24 19:09 ` [PATCH 03/24] drm/amd/display: Don't enable AFMT for DP audio stream Anson Jacob
2021-09-24 19:09 ` [PATCH 04/24] drm/amd/display: add vsync notify to dmub for abm pause Anson Jacob
2021-09-24 19:09 ` [PATCH 05/24] drm/amd/display: Add debug support to override the Minimum DRAM Clock Anson Jacob
2021-09-24 19:09 ` [PATCH 06/24] drm/amd/display: update cur_lane_setting to an array one for each lane Anson Jacob
2021-09-24 19:09 ` [PATCH 07/24] drm/amd/display: add function to convert hw to dpcd lane settings Anson Jacob
2021-09-24 19:09 ` [PATCH 08/24] drm/amd/display: implement decide " Anson Jacob
2021-09-24 19:09 ` Anson Jacob [this message]
2021-09-24 19:09 ` [PATCH 10/24] drm/amd/display: decouple hw_lane_settings from dpcd_lane_settings Anson Jacob
2021-09-24 19:09 ` [PATCH 11/24] drm/amd/display: add two lane settings training options Anson Jacob
2021-09-24 19:09 ` [PATCH 12/24] drm/amd/display: Fix for link encoder access for MST Anson Jacob
2021-09-24 19:09 ` [PATCH 13/24] drm/amd/display: Fix MST link encoder availability check Anson Jacob
2021-09-24 19:09 ` [PATCH 14/24] drm/amd/display: Add PPS immediate update flag for DCN2 Anson Jacob
2021-09-24 19:09 ` [PATCH 15/24] drm/amd/display: Add an extra check for dcn10 OPTC data format Anson Jacob
2021-09-24 19:09 ` [PATCH 16/24] drm/amd/display: [FW Promotion] Release 0.0.86 Anson Jacob
2021-09-24 19:09 ` [PATCH 17/24] drm/amd/display: 3.2.155 Anson Jacob
2021-09-24 19:09 ` [PATCH 18/24] drm/amd/display: Replace referral of dal with dc Anson Jacob
2021-09-24 19:09 ` [PATCH 19/24] drm/amd/display: Defer LUT memory powerdown until LUT bypass latches Anson Jacob
2021-09-24 19:09 ` [PATCH 20/24] drm/amd/display: initialize backlight_ramping_override to false Anson Jacob
2021-09-24 19:09 ` [PATCH 21/24] drm/amd/display: make verified link cap not exceeding max link cap Anson Jacob
2021-09-24 19:09 ` [PATCH 22/24] drm/amd/display: Handle Y carry-over in VCP X.Y calculation Anson Jacob
2021-09-24 19:09 ` [PATCH 23/24] drm/amd/display: Update VCP X.Y logging to improve usefulness Anson Jacob
2021-09-24 19:09 ` [PATCH 24/24] drm/amd/display: Pass PCI deviceid into DC Anson Jacob
2021-09-27 13:21 ` [PATCH 00/24] DC Patches Sep 24, 2021 Wheeler, Daniel

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