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[83.35.24.118]) by smtp.gmail.com with ESMTPSA id i2sm11055407wrq.78.2021.09.25.07.52.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Sep 2021 07:52:34 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v7 16/40] target/arm: Explicit v7M cores use arm_cpu_has_work as CPUClass:has_work Date: Sat, 25 Sep 2021 16:50:54 +0200 Message-Id: <20210925145118.1361230-17-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210925145118.1361230-1-f4bug@amsat.org> References: <20210925145118.1361230-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , "open list:ARM TCG CPUs" , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" ARM v7M cores inherit TYPE_ARM_CPU, so TYPE_ARM_CPU's class_init runs first and sets up most of the class fields, setting in particular the has_work handler to the generic arm_cpu_has_work(). Thus M-profile and A-profile share the same arm_cpu_has_work() function. Some of the checks the code there does are perhaps unnecessary for M-profile, but they're harmless. Since we want to move the has_work handler from CPUClass to TCGCPUOps, the next commit will be more explicit if we already register this handler in arm_v7m_class_init(). Since arm_cpu_has_work() is static to target/arm/cpu.c, we have to declare it in "internals.h" to be able to use it in target/arm/cpu_tcg.c. Suggested-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daudé --- target/arm/internals.h | 2 ++ target/arm/cpu.c | 2 +- target/arm/cpu_tcg.c | 1 + 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 9fbb3649682..f20aeb97fa0 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -177,6 +177,8 @@ void arm_translate_init(void); void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); #endif /* CONFIG_TCG */ +bool arm_cpu_has_work(CPUState *cs); + /** * aarch64_sve_zcr_get_valid_len: * @cpu: cpu context diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 641a8c2d3d3..4b08f717f64 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -76,7 +76,7 @@ void arm_cpu_synchronize_from_tb(CPUState *cs, } #endif /* CONFIG_TCG */ -static bool arm_cpu_has_work(CPUState *cs) +bool arm_cpu_has_work(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 0d5adccf1a7..9a0927ad5d0 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -920,6 +920,7 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data) acc->info = data; #ifdef CONFIG_TCG + cc->has_work = arm_cpu_has_work; cc->tcg_ops = &arm_v7m_tcg_ops; #endif /* CONFIG_TCG */ -- 2.31.1