[PATCH v6 0/6] Add Unisoc's drm kms module

[PATCH v6 0/6] Add Unisoc's drm kms module

[Kevin Tang]

ChangeList:
RFC v1:
1. only upstream modeset and atomic at first commit.
2. remove some unused code;
3. use alpha and blend_mode properties;
3. add yaml support;
4. remove auto-adaptive panel driver;
5. bugfix

RFC v2:
1. add sprd crtc and plane module for KMS, preparing for multi crtc&encoder
2. remove gem drivers, use generic CMA handlers
3. remove redundant "module_init", all the sub modules loading by KMS

RFC v3:
1. multi crtc&encoder design have problem, so rollback to v1

RFC v4:
1. update to gcc-linaro-7.5.0
2. update to Linux 5.6-rc3
3. remove pm_runtime support
4. add COMPILE_TEST, remove unused kconfig
5. "drm_dev_put" on drm_unbind
6. fix some naming convention issue
7. remove semaphore lock for crtc flip
8. remove static variables

RFC v5:
1. optimize encoder and connector code implementation
2. use "platform_get_irq" and "platform_get_resource"
3. drop useless function return type, drop unless debug log
4. custom properties should be separate, so drop it
5. use DRM_XXX replase pr_xxx
6. drop dsi&dphy hal callback ops
7. drop unless callback ops checking
8. add comments for sprd dpu structure

RFC v6:
1. Access registers via readl/writel
2. Checking for unsupported KMS properties (format, rotation, blend_mode, etc) on plane_check ops
3. Remove always true checks for dpu core ops

RFC v7:
1. Fix DTC unit name warnings
2. Fix the problem of maintainers
3. Call drmm_mode_config_init to mode config init
4. Embed drm_device in sprd_drm and use devm_drm_dev_alloc
5. Replace DRM_XXX with drm_xxx on KMS module, but not suitable for other subsystems
6. Remove plane_update stuff, dpu handles all the HW update in crtc->atomic_flush
7. Dsi&Dphy Code structure adjustment, all move to "sprd/"

v0:
1. Remove dpu_core_ops stuff layer for sprd drtc driver, but dpu_layer need to keeping.
   Because all the HW update in crtc->atomic_flush, we need temporary storage all layers for
   the dpu pageflip of atomic_flush.
2. Add ports subnode with port@X.

v1:
1. Remove dphy and dsi graph binding, merge the dphy driver into the dsi.
2. Add commit messages for Unisoc's virtual nodes.

v2:
1. Use drm_xxx to replace all DRM_XXX.
2. Use kzalloc to replace devm_kzalloc for sprd_dsi/sprd_dpu structure init.
3. Remove dpu_core_ops midlayer.

v3:
1. Remove dpu_layer midlayer and commit layers by aotmic_update

v4:
1. Move the devm_drm_dev_alloc to master_ops->bind function.
2. The managed drmm_mode_config_init() it is no longer necessary for drivers to explicitly call drm_mode_config_cleanup, so delete it.
3. Use drmm_helpers to allocate crtc ,planes and encoder.
4. Move allocate crtc ,planes, encoder to bind funtion.
5. Move rotation enum definitions to crtc layer reg bitfields.

v5:
1. Remove subdir-ccflgas-y for Makefile.
2. Keep the selects sorted by alphabet for Kconfig.
3. Fix the checkpatch warnings.
4. Use mode_set_nofb instead of mode_valid callback.
5. Follow the OF-Graph bindings, use of_graph_get_port_by_id instead of of_parse_phandle.
6. Use zpos to represent the layer position.
7. Rebase to last drm misc branch.
8. Remove panel_in port for dsi node.
9. Drop the dsi ip file prefix.
10. Add Signed-off-by for dsi&dphy patch.
11. Use the mode_flags of mipi_dsi_device to setup crtc DPI and EDPI mode.

v6:
1. Disable and clear interrupts before register dpu IRQ
2. Init dpi config used by crtc_state->adjusted_mode on mode_set_nofb
3. Remove enable_irq and disable_irq function call.
4. Remove drm_format_info function call.
5. Redesign the way to access the dsi register.
6. Reduce the dsi_context member variables.

Kevin Tang (6):
  dt-bindings: display: add Unisoc's drm master bindings
  drm/sprd: add Unisoc's drm kms master
  dt-bindings: display: add Unisoc's dpu bindings
  drm/sprd: add Unisoc's drm display controller driver
  dt-bindings: display: add Unisoc's mipi dsi controller bindings
  drm/sprd: add Unisoc's drm mipi dsi&dphy driver

 .../display/sprd/sprd,display-subsystem.yaml  |   64 +
 .../display/sprd/sprd,sharkl3-dpu.yaml        |   77 +
 .../display/sprd/sprd,sharkl3-dsi-host.yaml   |   88 ++
 drivers/gpu/drm/Kconfig                       |    2 +
 drivers/gpu/drm/Makefile                      |    1 +
 drivers/gpu/drm/sprd/Kconfig                  |   13 +
 drivers/gpu/drm/sprd/Makefile                 |    6 +
 drivers/gpu/drm/sprd/megacores_pll.c          |  317 +++++
 drivers/gpu/drm/sprd/megacores_pll.h          |  146 ++
 drivers/gpu/drm/sprd/sprd_dpu.c               |  954 +++++++++++++
 drivers/gpu/drm/sprd/sprd_dpu.h               |  109 ++
 drivers/gpu/drm/sprd/sprd_drm.c               |  207 +++
 drivers/gpu/drm/sprd/sprd_drm.h               |   19 +
 drivers/gpu/drm/sprd/sprd_dsi.c               | 1260 +++++++++++++++++
 drivers/gpu/drm/sprd/sprd_dsi.h               |   94 ++
 15 files changed, 3357 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/sprd/sprd,display-subsystem.yaml
 create mode 100644 Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dpu.yaml
 create mode 100644 Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dsi-host.yaml
 create mode 100644 drivers/gpu/drm/sprd/Kconfig
 create mode 100644 drivers/gpu/drm/sprd/Makefile
 create mode 100644 drivers/gpu/drm/sprd/megacores_pll.c
 create mode 100644 drivers/gpu/drm/sprd/megacores_pll.h
 create mode 100644 drivers/gpu/drm/sprd/sprd_dpu.c
 create mode 100644 drivers/gpu/drm/sprd/sprd_dpu.h
 create mode 100644 drivers/gpu/drm/sprd/sprd_drm.c
 create mode 100644 drivers/gpu/drm/sprd/sprd_drm.h
 create mode 100644 drivers/gpu/drm/sprd/sprd_dsi.c
 create mode 100644 drivers/gpu/drm/sprd/sprd_dsi.h

-- 
2.29.0

[PATCH v6 1/6] dt-bindings: display: add Unisoc's drm master bindings

[Kevin Tang]

From: Kevin Tang <kevin.tang@unisoc.com>

The Unisoc DRM master device is a virtual device needed to list all
DPU devices or other display interface nodes that comprise the
graphics subsystem

Unisoc's display pipeline have several components as below
description, multi display controllers and corresponding physical
interfaces.
For different display scenarios, dpu0 and dpu1 maybe binding to
different encoder.

E.g:
  dpu0 and dpu1 both binding to DSI for dual mipi-dsi display;
  dpu0 binding to DSI for primary display, and dpu1 binding to DP for
  external display;

Cc: Orson Zhai <orsonzhai@gmail.com>
Cc: Chunyan Zhang <zhang.lyra@gmail.com>
Signed-off-by: Kevin Tang <kevin.tang@unisoc.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../display/sprd/sprd,display-subsystem.yaml  | 64 +++++++++++++++++++
 1 file changed, 64 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/sprd/sprd,display-subsystem.yaml

diff --git a/Documentation/devicetree/bindings/display/sprd/sprd,display-subsystem.yaml b/Documentation/devicetree/bindings/display/sprd/sprd,display-subsystem.yaml
new file mode 100644
index 000000000..3d107e943
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/sprd/sprd,display-subsystem.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/sprd/sprd,display-subsystem.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Unisoc DRM master device
+
+maintainers:
+  - Kevin Tang <kevin.tang@unisoc.com>
+
+description: |
+  The Unisoc DRM master device is a virtual device needed to list all
+  DPU devices or other display interface nodes that comprise the
+  graphics subsystem.
+
+  Unisoc's display pipeline have several components as below description,
+  multi display controllers and corresponding physical interfaces.
+  For different display scenarios, dpu0 and dpu1 maybe binding to different
+  encoder.
+
+  E.g:
+  dpu0 and dpu1 both binding to DSI for dual mipi-dsi display;
+  dpu0 binding to DSI for primary display, and dpu1 binding to DP for external display;
+
+          +-----------------------------------------+
+          |                                         |
+          |                            +---------+  |
+  +----+  |   +----+    +---------+    |DPHY/CPHY|  |   +------+
+  |    +----->+dpu0+--->+MIPI|DSI +--->+Combo    +----->+Panel0|
+  |AXI |  |   +----+    +---------+    +---------+  |   +------+
+  |    |  |                  ^                      |
+  |    |  |                  |                      |
+  |    |  |      +-----------+                      |
+  |    |  |      |                                  |
+  |APB |  |   +--+-+    +-----------+    +---+      |   +------+
+  |    +----->+dpu1+--->+DisplayPort+--->+PHY+--------->+Panel1|
+  |    |  |   +----+    +-----------+    +---+      |   +------+
+  +----+  |                                         |
+          +-----------------------------------------+
+
+properties:
+  compatible:
+    const: sprd,display-subsystem
+
+  ports:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    description:
+      Should contain a list of phandles pointing to display interface port
+      of DPU devices.
+
+required:
+  - compatible
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    display-subsystem {
+        compatible = "sprd,display-subsystem";
+        ports = <&dpu_out>;
+    };
+
-- 
2.29.0

[PATCH v6 2/6] drm/sprd: add Unisoc's drm kms master

[Kevin Tang]

Adds drm support for the Unisoc's display subsystem.

This is drm kms driver, this driver provides support for the
application framework in Android, Yocto and more.

Application framework can access Unisoc's display internal
peripherals through libdrm or libkms, it's test ok by modetest
(DRM/KMS test tool) and Android HWComposer.

Cc: Orson Zhai <orsonzhai@gmail.com>
Cc: Chunyan Zhang <zhang.lyra@gmail.com>
Signed-off-by: Kevin Tang <kevin.tang@unisoc.com>

v4:
  - Move the devm_drm_dev_alloc to master_ops->bind function.
  - The managed drmm_mode_config_init() it is no longer necessary for drivers to explicitly call drm_mode_config_cleanup, so delete it.

v5:
  - Remove subdir-ccflgas-y for Makefile.
  - Keep the selects sorted by alphabet for Kconfig.
---
 drivers/gpu/drm/Kconfig         |   2 +
 drivers/gpu/drm/Makefile        |   1 +
 drivers/gpu/drm/sprd/Kconfig    |  11 ++
 drivers/gpu/drm/sprd/Makefile   |   3 +
 drivers/gpu/drm/sprd/sprd_drm.c | 205 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/sprd/sprd_drm.h |  16 +++
 6 files changed, 238 insertions(+)
 create mode 100644 drivers/gpu/drm/sprd/Kconfig
 create mode 100644 drivers/gpu/drm/sprd/Makefile
 create mode 100644 drivers/gpu/drm/sprd/sprd_drm.c
 create mode 100644 drivers/gpu/drm/sprd/sprd_drm.h

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 3c16bd1af..a92525445 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -386,6 +386,8 @@ source "drivers/gpu/drm/xlnx/Kconfig"
 
 source "drivers/gpu/drm/gud/Kconfig"
 
+source "drivers/gpu/drm/sprd/Kconfig"
+
 # Keep legacy drivers last
 
 menuconfig DRM_LEGACY
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 5279db439..03a52d1dc 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -126,3 +126,4 @@ obj-$(CONFIG_DRM_MCDE) += mcde/
 obj-$(CONFIG_DRM_TIDSS) += tidss/
 obj-y			+= xlnx/
 obj-y			+= gud/
+obj-$(CONFIG_DRM_SPRD) += sprd/
diff --git a/drivers/gpu/drm/sprd/Kconfig b/drivers/gpu/drm/sprd/Kconfig
new file mode 100644
index 000000000..726c3e76d
--- /dev/null
+++ b/drivers/gpu/drm/sprd/Kconfig
@@ -0,0 +1,11 @@
+config DRM_SPRD
+	tristate "DRM Support for Unisoc SoCs Platform"
+	depends on ARCH_SPRD || COMPILE_TEST
+	depends on DRM && OF
+	select DRM_GEM_CMA_HELPER
+	select DRM_KMS_CMA_HELPER
+	select DRM_KMS_HELPER
+	help
+	  Choose this option if you have a Unisoc chipset.
+	  If M is selected the module will be called sprd_drm.
+
diff --git a/drivers/gpu/drm/sprd/Makefile b/drivers/gpu/drm/sprd/Makefile
new file mode 100644
index 000000000..9850f00b8
--- /dev/null
+++ b/drivers/gpu/drm/sprd/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y := sprd_drm.o
diff --git a/drivers/gpu/drm/sprd/sprd_drm.c b/drivers/gpu/drm/sprd/sprd_drm.c
new file mode 100644
index 000000000..6b00a6f27
--- /dev/null
+++ b/drivers/gpu/drm/sprd/sprd_drm.c
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Unisoc Inc.
+ */
+
+#include <linux/component.h>
+#include <linux/dma-mapping.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of_graph.h>
+#include <linux/of_platform.h>
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_gem_framebuffer_helper.h>
+#include <drm/drm_of.h>
+#include <drm/drm_probe_helper.h>
+#include <drm/drm_vblank.h>
+
+#include "sprd_drm.h"
+
+#define DRIVER_NAME	"sprd"
+#define DRIVER_DESC	"Spreadtrum SoCs' DRM Driver"
+#define DRIVER_DATE	"20200201"
+#define DRIVER_MAJOR	1
+#define DRIVER_MINOR	0
+
+static const struct drm_mode_config_helper_funcs sprd_drm_mode_config_helper = {
+	.atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
+};
+
+static const struct drm_mode_config_funcs sprd_drm_mode_config_funcs = {
+	.fb_create = drm_gem_fb_create,
+	.atomic_check = drm_atomic_helper_check,
+	.atomic_commit = drm_atomic_helper_commit,
+};
+
+static void sprd_drm_mode_config_init(struct drm_device *drm)
+{
+	drm->mode_config.min_width = 0;
+	drm->mode_config.min_height = 0;
+	drm->mode_config.max_width = 8192;
+	drm->mode_config.max_height = 8192;
+	drm->mode_config.allow_fb_modifiers = true;
+
+	drm->mode_config.funcs = &sprd_drm_mode_config_funcs;
+	drm->mode_config.helper_private = &sprd_drm_mode_config_helper;
+}
+
+DEFINE_DRM_GEM_CMA_FOPS(sprd_drm_fops);
+
+static struct drm_driver sprd_drm_drv = {
+	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
+	.fops			= &sprd_drm_fops,
+
+	/* GEM Operations */
+	DRM_GEM_CMA_DRIVER_OPS,
+
+	.name			= DRIVER_NAME,
+	.desc			= DRIVER_DESC,
+	.date			= DRIVER_DATE,
+	.major			= DRIVER_MAJOR,
+	.minor			= DRIVER_MINOR,
+};
+
+static int sprd_drm_bind(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct drm_device *drm;
+	struct sprd_drm *sprd;
+	int ret;
+
+	sprd = devm_drm_dev_alloc(dev, &sprd_drm_drv, struct sprd_drm, drm);
+	if (IS_ERR(sprd))
+		return PTR_ERR(sprd);
+
+	drm = &sprd->drm;
+	platform_set_drvdata(pdev, drm);
+
+	ret = drmm_mode_config_init(drm);
+	if (ret)
+		return ret;
+
+	sprd_drm_mode_config_init(drm);
+
+	/* bind and init sub drivers */
+	ret = component_bind_all(drm->dev, drm);
+	if (ret) {
+		drm_err(drm, "failed to bind all component.\n");
+		return ret;
+	}
+
+	/* vblank init */
+	ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
+	if (ret) {
+		drm_err(drm, "failed to initialize vblank.\n");
+		goto err_unbind_all;
+	}
+	/* with irq_enabled = true, we can use the vblank feature. */
+	drm->irq_enabled = true;
+
+	/* reset all the states of crtc/plane/encoder/connector */
+	drm_mode_config_reset(drm);
+
+	/* init kms poll for handling hpd */
+	drm_kms_helper_poll_init(drm);
+
+	ret = drm_dev_register(drm, 0);
+	if (ret < 0)
+		goto err_kms_helper_poll_fini;
+
+	return 0;
+
+err_kms_helper_poll_fini:
+	drm_kms_helper_poll_fini(drm);
+err_unbind_all:
+	component_unbind_all(drm->dev, drm);
+	return ret;
+}
+
+static void sprd_drm_unbind(struct device *dev)
+{
+	struct drm_device *drm = dev_get_drvdata(dev);
+
+	drm_dev_unregister(drm);
+
+	drm_kms_helper_poll_fini(drm);
+
+	component_unbind_all(drm->dev, drm);
+}
+
+static const struct component_master_ops drm_component_ops = {
+	.bind = sprd_drm_bind,
+	.unbind = sprd_drm_unbind,
+};
+
+static int compare_of(struct device *dev, void *data)
+{
+	return dev->of_node == data;
+}
+
+static int sprd_drm_probe(struct platform_device *pdev)
+{
+	return drm_of_component_probe(&pdev->dev, compare_of, &drm_component_ops);
+}
+
+static int sprd_drm_remove(struct platform_device *pdev)
+{
+	component_master_del(&pdev->dev, &drm_component_ops);
+	return 0;
+}
+
+static void sprd_drm_shutdown(struct platform_device *pdev)
+{
+	struct drm_device *drm = platform_get_drvdata(pdev);
+
+	if (!drm) {
+		drm_warn(drm, "drm device is not available, no shutdown\n");
+		return;
+	}
+
+	drm_atomic_helper_shutdown(drm);
+}
+
+static const struct of_device_id drm_match_table[] = {
+	{ .compatible = "sprd,display-subsystem", },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, drm_match_table);
+
+static struct platform_driver sprd_drm_driver = {
+	.probe = sprd_drm_probe,
+	.remove = sprd_drm_remove,
+	.shutdown = sprd_drm_shutdown,
+	.driver = {
+		.name = "sprd-drm-drv",
+		.of_match_table = drm_match_table,
+	},
+};
+
+static struct platform_driver *sprd_drm_drivers[]  = {
+	&sprd_drm_driver,
+};
+
+static int __init sprd_drm_init(void)
+{
+	return platform_register_drivers(sprd_drm_drivers,
+					ARRAY_SIZE(sprd_drm_drivers));
+}
+
+static void __exit sprd_drm_exit(void)
+{
+	platform_unregister_drivers(sprd_drm_drivers,
+				    ARRAY_SIZE(sprd_drm_drivers));
+}
+
+module_init(sprd_drm_init);
+module_exit(sprd_drm_exit);
+
+MODULE_AUTHOR("Leon He <leon.he@unisoc.com>");
+MODULE_AUTHOR("Kevin Tang <kevin.tang@unisoc.com>");
+MODULE_DESCRIPTION("Unisoc DRM KMS Master Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/sprd/sprd_drm.h b/drivers/gpu/drm/sprd/sprd_drm.h
new file mode 100644
index 000000000..9781fd591
--- /dev/null
+++ b/drivers/gpu/drm/sprd/sprd_drm.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Unisoc Inc.
+ */
+
+#ifndef _SPRD_DRM_H_
+#define _SPRD_DRM_H_
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_print.h>
+
+struct sprd_drm {
+	struct drm_device drm;
+};
+
+#endif /* _SPRD_DRM_H_ */
-- 
2.29.0

[PATCH v6 3/6] dt-bindings: display: add Unisoc's dpu bindings

[Kevin Tang]

From: Kevin Tang <kevin.tang@unisoc.com>

DPU (Display Processor Unit) is the Display Controller for the Unisoc SoCs
which transfers the image data from a video memory buffer to an internal
LCD interface.

Cc: Orson Zhai <orsonzhai@gmail.com>
Cc: Chunyan Zhang <zhang.lyra@gmail.com>
Signed-off-by: Kevin Tang <kevin.tang@unisoc.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../display/sprd/sprd,sharkl3-dpu.yaml        | 77 +++++++++++++++++++
 1 file changed, 77 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dpu.yaml

diff --git a/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dpu.yaml b/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dpu.yaml
new file mode 100644
index 000000000..4ebea60b8
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dpu.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/sprd/sprd,sharkl3-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Unisoc Sharkl3 Display Processor Unit (DPU)
+
+maintainers:
+  - Kevin Tang <kevin.tang@unisoc.com>
+
+description: |
+  DPU (Display Processor Unit) is the Display Controller for the Unisoc SoCs
+  which transfers the image data from a video memory buffer to an internal
+  LCD interface.
+
+properties:
+  compatible:
+    const: sprd,sharkl3-dpu
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    minItems: 2
+
+  clock-names:
+    items:
+      - const: clk_src_128m
+      - const: clk_src_384m
+
+  power-domains:
+    maxItems: 1
+
+  iommus:
+    maxItems: 1
+
+  port:
+    type: object
+    description:
+      A port node with endpoint definitions as defined in
+      Documentation/devicetree/bindings/media/video-interfaces.txt.
+      That port should be the output endpoint, usually output to
+      the associated DSI.
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - port
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/sprd,sc9860-clk.h>
+    dpu: dpu@63000000 {
+        compatible = "sprd,sharkl3-dpu";
+        reg = <0x63000000 0x1000>;
+        interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+        clock-names = "clk_src_128m", "clk_src_384m";
+
+        clocks = <&pll CLK_TWPLL_128M>,
+          <&pll CLK_TWPLL_384M>;
+
+        dpu_port: port {
+            dpu_out: endpoint {
+                remote-endpoint = <&dsi_in>;
+            };
+        };
+    };
-- 
2.29.0

[PATCH v6 4/6] drm/sprd: add Unisoc's drm display controller driver

[Kevin Tang]

Adds DPU(Display Processor Unit) support for the Unisoc's display
subsystem.
It's support multi planes, scaler, rotation, PQ(Picture Quality) and more.

v2:
  - Use drm_xxx to replace all DRM_XXX.
  - Use kzalloc to replace devm_kzalloc for sprd_dpu structure init.

v3:
  - Remove dpu_layer stuff layer and commit layers by aotmic_update

v4:
  - Use drmm_helpers to allocate crtc and planes.
  - Move rotation enum definitions to crtc layer reg bitfields.
  - Move allocate crtc and planes to bind function.

v5:
  - Fix the checkpatch warnings.
  - Use mode_set_nofb instead of mode_valid callback.
  - Follow the OF-Graph bindings, use of_graph_get_port_by_id
    instead of of_parse_phandle.
  - Use zpos to represent the layer position.
  - Rebase to last drm misc branch.

v6:
  - Disable and clear interrupts before register dpu IRQ
  - Init dpi config used by crtc_state->adjusted_mode on mode_set_nofb
  - Remove enable_irq and disable_irq function call.
  - Remove drm_format_info function call.

Cc: Orson Zhai <orsonzhai@gmail.com>
Cc: Chunyan Zhang <zhang.lyra@gmail.com>
Signed-off-by: Kevin Tang <kevin.tang@unisoc.com>
---
 drivers/gpu/drm/sprd/Kconfig    |   1 +
 drivers/gpu/drm/sprd/Makefile   |   3 +-
 drivers/gpu/drm/sprd/sprd_dpu.c | 937 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/sprd/sprd_dpu.h | 109 ++++
 drivers/gpu/drm/sprd/sprd_drm.c |   1 +
 drivers/gpu/drm/sprd/sprd_drm.h |   2 +
 6 files changed, 1052 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/sprd/sprd_dpu.c
 create mode 100644 drivers/gpu/drm/sprd/sprd_dpu.h

diff --git a/drivers/gpu/drm/sprd/Kconfig b/drivers/gpu/drm/sprd/Kconfig
index 726c3e76d..37762c333 100644
--- a/drivers/gpu/drm/sprd/Kconfig
+++ b/drivers/gpu/drm/sprd/Kconfig
@@ -5,6 +5,7 @@ config DRM_SPRD
 	select DRM_GEM_CMA_HELPER
 	select DRM_KMS_CMA_HELPER
 	select DRM_KMS_HELPER
+	select VIDEOMODE_HELPERS
 	help
 	  Choose this option if you have a Unisoc chipset.
 	  If M is selected the module will be called sprd_drm.
diff --git a/drivers/gpu/drm/sprd/Makefile b/drivers/gpu/drm/sprd/Makefile
index 9850f00b8..ab12b95e6 100644
--- a/drivers/gpu/drm/sprd/Makefile
+++ b/drivers/gpu/drm/sprd/Makefile
@@ -1,3 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0
 
-obj-y := sprd_drm.o
+obj-y := sprd_drm.o \
+	sprd_dpu.o
diff --git a/drivers/gpu/drm/sprd/sprd_dpu.c b/drivers/gpu/drm/sprd/sprd_dpu.c
new file mode 100644
index 000000000..448dd4fb6
--- /dev/null
+++ b/drivers/gpu/drm/sprd/sprd_dpu.c
@@ -0,0 +1,937 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Unisoc Inc.
+ */
+
+#include <linux/component.h>
+#include <linux/delay.h>
+#include <linux/dma-buf.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_graph.h>
+#include <linux/of_irq.h>
+#include <linux/wait.h>
+#include <linux/workqueue.h>
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_fb_cma_helper.h>
+#include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_gem_framebuffer_helper.h>
+#include <drm/drm_plane_helper.h>
+
+#include "sprd_drm.h"
+#include "sprd_dpu.h"
+
+/* Global control registers */
+#define REG_DPU_CTRL	0x04
+#define REG_DPU_CFG0	0x08
+#define REG_PANEL_SIZE	0x20
+#define REG_BLEND_SIZE	0x24
+#define REG_BG_COLOR	0x2C
+
+/* Layer0 control registers */
+#define REG_LAY_BASE_ADDR0	0x30
+#define REG_LAY_BASE_ADDR1	0x34
+#define REG_LAY_BASE_ADDR2	0x38
+#define REG_LAY_CTRL		0x40
+#define REG_LAY_SIZE		0x44
+#define REG_LAY_PITCH		0x48
+#define REG_LAY_POS		0x4C
+#define REG_LAY_ALPHA		0x50
+#define REG_LAY_CROP_START	0x5C
+
+/* Interrupt control registers */
+#define REG_DPU_INT_EN		0x1E0
+#define REG_DPU_INT_CLR		0x1E4
+#define REG_DPU_INT_STS		0x1E8
+
+/* DPI control registers */
+#define REG_DPI_CTRL		0x1F0
+#define REG_DPI_H_TIMING	0x1F4
+#define REG_DPI_V_TIMING	0x1F8
+
+/* MMU control registers */
+#define REG_MMU_EN			0x800
+#define REG_MMU_VPN_RANGE		0x80C
+#define REG_MMU_VAOR_ADDR_RD		0x818
+#define REG_MMU_VAOR_ADDR_WR		0x81C
+#define REG_MMU_INV_ADDR_RD		0x820
+#define REG_MMU_INV_ADDR_WR		0x824
+#define REG_MMU_PPN1			0x83C
+#define REG_MMU_RANGE1			0x840
+#define REG_MMU_PPN2			0x844
+#define REG_MMU_RANGE2			0x848
+
+/* Global control bits */
+#define BIT_DPU_RUN			BIT(0)
+#define BIT_DPU_STOP			BIT(1)
+#define BIT_DPU_REG_UPDATE		BIT(2)
+#define BIT_DPU_IF_EDPI			BIT(0)
+
+/* Layer control bits */
+#define BIT_DPU_LAY_EN				BIT(0)
+#define BIT_DPU_LAY_LAYER_ALPHA			(0x01 << 2)
+#define BIT_DPU_LAY_COMBO_ALPHA			(0x02 << 2)
+#define BIT_DPU_LAY_FORMAT_YUV422_2PLANE		(0x00 << 4)
+#define BIT_DPU_LAY_FORMAT_YUV420_2PLANE		(0x01 << 4)
+#define BIT_DPU_LAY_FORMAT_YUV420_3PLANE		(0x02 << 4)
+#define BIT_DPU_LAY_FORMAT_ARGB8888			(0x03 << 4)
+#define BIT_DPU_LAY_FORMAT_RGB565			(0x04 << 4)
+#define BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3		(0x00 << 8)
+#define BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0		(0x01 << 8)
+#define BIT_DPU_LAY_NO_SWITCH			(0x00 << 10)
+#define BIT_DPU_LAY_RB_OR_UV_SWITCH		(0x01 << 10)
+#define BIT_DPU_LAY_MODE_BLEND_NORMAL		(0x00 << 16)
+#define BIT_DPU_LAY_MODE_BLEND_PREMULT		(0x01 << 16)
+#define BIT_DPU_LAY_ROTATION_0		(0x00 << 20)
+#define BIT_DPU_LAY_ROTATION_90		(0x01 << 20)
+#define BIT_DPU_LAY_ROTATION_180	(0x02 << 20)
+#define BIT_DPU_LAY_ROTATION_270	(0x03 << 20)
+#define BIT_DPU_LAY_ROTATION_0_M	(0x04 << 20)
+#define BIT_DPU_LAY_ROTATION_90_M	(0x05 << 20)
+#define BIT_DPU_LAY_ROTATION_180_M	(0x06 << 20)
+#define BIT_DPU_LAY_ROTATION_270_M	(0x07 << 20)
+
+/* Interrupt control & status bits */
+#define BIT_DPU_INT_DONE		BIT(0)
+#define BIT_DPU_INT_TE			BIT(1)
+#define BIT_DPU_INT_ERR			BIT(2)
+#define BIT_DPU_INT_UPDATE_DONE		BIT(4)
+#define BIT_DPU_INT_VSYNC		BIT(5)
+#define BIT_DPU_INT_MMU_VAOR_RD		BIT(16)
+#define BIT_DPU_INT_MMU_VAOR_WR		BIT(17)
+#define BIT_DPU_INT_MMU_INV_RD		BIT(18)
+#define BIT_DPU_INT_MMU_INV_WR		BIT(19)
+
+/* DPI control bits */
+#define BIT_DPU_EDPI_TE_EN		BIT(8)
+#define BIT_DPU_EDPI_FROM_EXTERNAL_PAD	BIT(10)
+#define BIT_DPU_DPI_HALT_EN		BIT(16)
+
+static const u32 layer_fmts[] = {
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_RGBA8888,
+	DRM_FORMAT_BGRA8888,
+	DRM_FORMAT_RGBX8888,
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_BGR565,
+	DRM_FORMAT_NV12,
+	DRM_FORMAT_NV21,
+	DRM_FORMAT_NV16,
+	DRM_FORMAT_NV61,
+	DRM_FORMAT_YUV420,
+	DRM_FORMAT_YVU420,
+};
+
+struct sprd_plane {
+	struct drm_plane base;
+};
+
+static u32 check_mmu_isr(struct sprd_dpu *dpu, u32 reg_val)
+{
+	struct dpu_context *ctx = &dpu->ctx;
+	u32 mmu_mask = BIT_DPU_INT_MMU_VAOR_RD |
+			BIT_DPU_INT_MMU_VAOR_WR |
+			BIT_DPU_INT_MMU_INV_RD |
+			BIT_DPU_INT_MMU_INV_WR;
+	u32 val = reg_val & mmu_mask;
+	int i;
+
+	if (val) {
+		drm_err(dpu->drm, "--- iommu interrupt err: 0x%04x ---\n", val);
+
+		if (val & BIT_DPU_INT_MMU_INV_RD)
+			drm_err(dpu->drm, "iommu invalid read error, addr: 0x%08x\n",
+				readl(ctx->base + REG_MMU_INV_ADDR_RD));
+		if (val & BIT_DPU_INT_MMU_INV_WR)
+			drm_err(dpu->drm, "iommu invalid write error, addr: 0x%08x\n",
+				readl(ctx->base + REG_MMU_INV_ADDR_WR));
+		if (val & BIT_DPU_INT_MMU_VAOR_RD)
+			drm_err(dpu->drm, "iommu va out of range read error, addr: 0x%08x\n",
+				readl(ctx->base + REG_MMU_VAOR_ADDR_RD));
+		if (val & BIT_DPU_INT_MMU_VAOR_WR)
+			drm_err(dpu->drm, "iommu va out of range write error, addr: 0x%08x\n",
+				readl(ctx->base + REG_MMU_VAOR_ADDR_WR));
+
+		for (i = 0; i < 8; i++) {
+			reg_val = layer_reg_rd(ctx, REG_LAY_CTRL, i);
+			if (reg_val & 0x1)
+				drm_info(dpu->drm, "layer%d: 0x%x 0x%x 0x%x ctrl: 0x%x\n", i,
+					layer_reg_rd(ctx, REG_LAY_BASE_ADDR0, i),
+					layer_reg_rd(ctx, REG_LAY_BASE_ADDR1, i),
+					layer_reg_rd(ctx, REG_LAY_BASE_ADDR2, i),
+					layer_reg_rd(ctx, REG_LAY_CTRL, i));
+		}
+	}
+
+	return val;
+}
+
+static int dpu_wait_stop_done(struct sprd_dpu *dpu)
+{
+	struct dpu_context *ctx = &dpu->ctx;
+	int rc;
+
+	if (ctx->stopped)
+		return 0;
+
+	rc = wait_event_interruptible_timeout(ctx->wait_queue, ctx->evt_stop,
+					       msecs_to_jiffies(500));
+	ctx->evt_stop = false;
+
+	ctx->stopped = true;
+
+	if (!rc) {
+		drm_err(dpu->drm, "dpu wait for stop done time out!\n");
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+static int dpu_wait_update_done(struct sprd_dpu *dpu)
+{
+	struct dpu_context *ctx = &dpu->ctx;
+	int rc;
+
+	ctx->evt_update = false;
+
+	rc = wait_event_interruptible_timeout(ctx->wait_queue, ctx->evt_update,
+					       msecs_to_jiffies(500));
+
+	if (!rc) {
+		drm_err(dpu->drm, "dpu wait for reg update done time out!\n");
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+static u32 drm_format_to_dpu(struct drm_framebuffer *fb)
+{
+	u32 format = 0;
+
+	switch (fb->format->format) {
+	case DRM_FORMAT_BGRA8888:
+		/* BGRA8888 -> ARGB8888 */
+		format |= BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0;
+		format |= BIT_DPU_LAY_FORMAT_ARGB8888;
+		break;
+	case DRM_FORMAT_RGBX8888:
+	case DRM_FORMAT_RGBA8888:
+		/* RGBA8888 -> ABGR8888 */
+		format |= BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0;
+		fallthrough;
+	case DRM_FORMAT_ABGR8888:
+		/* RB switch */
+		format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
+		fallthrough;
+	case DRM_FORMAT_ARGB8888:
+		format |= BIT_DPU_LAY_FORMAT_ARGB8888;
+		break;
+	case DRM_FORMAT_XBGR8888:
+		/* RB switch */
+		format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
+		fallthrough;
+	case DRM_FORMAT_XRGB8888:
+		format |= BIT_DPU_LAY_FORMAT_ARGB8888;
+		break;
+	case DRM_FORMAT_BGR565:
+		/* RB switch */
+		format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
+		fallthrough;
+	case DRM_FORMAT_RGB565:
+		format |= BIT_DPU_LAY_FORMAT_RGB565;
+		break;
+	case DRM_FORMAT_NV12:
+		/* 2-Lane: Yuv420 */
+		format |= BIT_DPU_LAY_FORMAT_YUV420_2PLANE;
+		/* Y endian */
+		format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
+		/* UV endian */
+		format |= BIT_DPU_LAY_NO_SWITCH;
+		break;
+	case DRM_FORMAT_NV21:
+		/* 2-Lane: Yuv420 */
+		format |= BIT_DPU_LAY_FORMAT_YUV420_2PLANE;
+		/* Y endian */
+		format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
+		/* UV endian */
+		format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
+		break;
+	case DRM_FORMAT_NV16:
+		/* 2-Lane: Yuv422 */
+		format |= BIT_DPU_LAY_FORMAT_YUV422_2PLANE;
+		/* Y endian */
+		format |= BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0;
+		/* UV endian */
+		format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
+		break;
+	case DRM_FORMAT_NV61:
+		/* 2-Lane: Yuv422 */
+		format |= BIT_DPU_LAY_FORMAT_YUV422_2PLANE;
+		/* Y endian */
+		format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
+		/* UV endian */
+		format |= BIT_DPU_LAY_NO_SWITCH;
+		break;
+	case DRM_FORMAT_YUV420:
+		format |= BIT_DPU_LAY_FORMAT_YUV420_3PLANE;
+		/* Y endian */
+		format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
+		/* UV endian */
+		format |= BIT_DPU_LAY_NO_SWITCH;
+		break;
+	case DRM_FORMAT_YVU420:
+		format |= BIT_DPU_LAY_FORMAT_YUV420_3PLANE;
+		/* Y endian */
+		format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
+		/* UV endian */
+		format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
+		break;
+	default:
+		break;
+	}
+
+	return format;
+}
+
+static u32 drm_rotation_to_dpu(struct drm_plane_state *state)
+{
+	u32 rotation = 0;
+
+	switch (state->rotation) {
+	default:
+	case DRM_MODE_ROTATE_0:
+		rotation = BIT_DPU_LAY_ROTATION_0;
+		break;
+	case DRM_MODE_ROTATE_90:
+		rotation = BIT_DPU_LAY_ROTATION_90;
+		break;
+	case DRM_MODE_ROTATE_180:
+		rotation = BIT_DPU_LAY_ROTATION_180;
+		break;
+	case DRM_MODE_ROTATE_270:
+		rotation = BIT_DPU_LAY_ROTATION_270;
+		break;
+	case DRM_MODE_REFLECT_Y:
+		rotation = BIT_DPU_LAY_ROTATION_180_M;
+		break;
+	case (DRM_MODE_REFLECT_Y | DRM_MODE_ROTATE_90):
+		rotation = BIT_DPU_LAY_ROTATION_90_M;
+		break;
+	case DRM_MODE_REFLECT_X:
+		rotation = BIT_DPU_LAY_ROTATION_0_M;
+		break;
+	case (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90):
+		rotation = BIT_DPU_LAY_ROTATION_270_M;
+		break;
+	}
+
+	return rotation;
+}
+
+static u32 drm_blend_to_dpu(struct drm_plane_state *state)
+{
+	u32 blend = 0;
+
+	switch (state->pixel_blend_mode) {
+	case DRM_MODE_BLEND_COVERAGE:
+		/* alpha mode select - combo alpha */
+		blend |= BIT_DPU_LAY_COMBO_ALPHA;
+		/* Normal mode */
+		blend |= BIT_DPU_LAY_MODE_BLEND_NORMAL;
+		break;
+	case DRM_MODE_BLEND_PREMULTI:
+		/* alpha mode select - combo alpha */
+		blend |= BIT_DPU_LAY_COMBO_ALPHA;
+		/* Pre-mult mode */
+		blend |= BIT_DPU_LAY_MODE_BLEND_PREMULT;
+		break;
+	case DRM_MODE_BLEND_PIXEL_NONE:
+	default:
+		/* don't do blending, maybe RGBX */
+		/* alpha mode select - layer alpha */
+		blend |= BIT_DPU_LAY_LAYER_ALPHA;
+		break;
+	}
+
+	return blend;
+}
+
+static void sprd_dpu_layer(struct sprd_dpu *dpu, struct drm_plane_state *state)
+{
+	struct dpu_context *ctx = &dpu->ctx;
+	struct drm_gem_cma_object *cma_obj;
+	struct drm_framebuffer *fb = state->fb;
+	u32 addr, size, offset, pitch, blend, format, rotation;
+	u32 src_x = state->src_x >> 16;
+	u32 src_y = state->src_y >> 16;
+	u32 src_w = state->src_w >> 16;
+	u32 src_h = state->src_h >> 16;
+	u32 dst_x = state->crtc_x;
+	u32 dst_y = state->crtc_y;
+	u32 alpha = state->alpha;
+	u32 index = state->zpos;
+	int i;
+
+	offset = (dst_x & 0xffff) | (dst_y << 16);
+	size = (src_w & 0xffff) | (src_h << 16);
+
+	for (i = 0; i < fb->format->num_planes; i++) {
+		cma_obj = drm_fb_cma_get_gem_obj(fb, i);
+		addr = cma_obj->paddr + fb->offsets[i];
+
+		if (i == 0)
+			layer_reg_wr(ctx, REG_LAY_BASE_ADDR0, addr, index);
+		else if (i == 1)
+			layer_reg_wr(ctx, REG_LAY_BASE_ADDR1, addr, index);
+		else
+			layer_reg_wr(ctx, REG_LAY_BASE_ADDR2, addr, index);
+	}
+
+	if (fb->format->num_planes == 3) {
+		/* UV pitch is 1/2 of Y pitch */
+		pitch = (fb->pitches[0] / fb->format->cpp[0]) |
+				(fb->pitches[0] / fb->format->cpp[0] << 15);
+	} else {
+		pitch = fb->pitches[0] / fb->format->cpp[0];
+	}
+
+	layer_reg_wr(ctx, REG_LAY_POS, offset, index);
+	layer_reg_wr(ctx, REG_LAY_SIZE, size, index);
+	layer_reg_wr(ctx, REG_LAY_CROP_START,
+			src_y << 16 | src_x, index);
+	layer_reg_wr(ctx, REG_LAY_ALPHA, alpha, index);
+	layer_reg_wr(ctx, REG_LAY_PITCH, pitch, index);
+
+	format = drm_format_to_dpu(fb);
+	blend = drm_blend_to_dpu(state);
+	rotation = drm_rotation_to_dpu(state);
+
+	layer_reg_wr(ctx, REG_LAY_CTRL, BIT_DPU_LAY_EN |
+				format |
+				blend |
+				rotation,
+				index);
+}
+
+static void sprd_dpu_flip(struct sprd_dpu *dpu)
+{
+	struct dpu_context *ctx = &dpu->ctx;
+	u32 reg_val;
+
+	/*
+	 * Make sure the dpu is in stop status. DPU has no shadow
+	 * registers in EDPI mode. So the config registers can only be
+	 * updated in the rising edge of DPU_RUN bit.
+	 */
+	if (ctx->if_type == SPRD_DPU_IF_EDPI)
+		dpu_wait_stop_done(dpu);
+
+	/* update trigger and wait */
+	if (ctx->if_type == SPRD_DPU_IF_DPI) {
+		if (!ctx->stopped) {
+			dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_REG_UPDATE);
+			dpu_wait_update_done(dpu);
+		}
+
+		dpu_reg_set(ctx, REG_DPU_INT_EN, BIT_DPU_INT_ERR);
+	} else if (ctx->if_type == SPRD_DPU_IF_EDPI) {
+		dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_RUN);
+
+		ctx->stopped = false;
+	}
+
+	/*
+	 * If the following interrupt was disabled in isr,
+	 * re-enable it.
+	 */
+	reg_val = BIT_DPU_INT_MMU_VAOR_RD |
+		  BIT_DPU_INT_MMU_VAOR_WR |
+		  BIT_DPU_INT_MMU_INV_RD |
+		  BIT_DPU_INT_MMU_INV_WR;
+	dpu_reg_set(ctx, REG_DPU_INT_EN, reg_val);
+}
+
+static void sprd_dpu_init(struct sprd_dpu *dpu)
+{
+	struct dpu_context *ctx = &dpu->ctx;
+	u32 int_mask = 0;
+
+	writel(0x00, ctx->base + REG_BG_COLOR);
+	writel(0x00, ctx->base + REG_MMU_EN);
+	writel(0x00, ctx->base + REG_MMU_PPN1);
+	writel(0xffff, ctx->base + REG_MMU_RANGE1);
+	writel(0x00, ctx->base + REG_MMU_PPN2);
+	writel(0xffff, ctx->base + REG_MMU_RANGE2);
+	writel(0x1ffff, ctx->base + REG_MMU_VPN_RANGE);
+
+	if (ctx->if_type == SPRD_DPU_IF_DPI) {
+		/* use dpi as interface */
+		dpu_reg_clr(ctx, REG_DPU_CFG0, BIT_DPU_IF_EDPI);
+		/* disable Halt function for SPRD DSI */
+		dpu_reg_clr(ctx, REG_DPI_CTRL, BIT_DPU_DPI_HALT_EN);
+		/* select te from external pad */
+		dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_EDPI_FROM_EXTERNAL_PAD);
+
+		/* enable dpu update done INT */
+		int_mask |= BIT_DPU_INT_UPDATE_DONE;
+		/* enable dpu done INT */
+		int_mask |= BIT_DPU_INT_DONE;
+		/* enable dpu dpi vsync */
+		int_mask |= BIT_DPU_INT_VSYNC;
+		/* enable dpu TE INT */
+		int_mask |= BIT_DPU_INT_TE;
+		/* enable underflow err INT */
+		int_mask |= BIT_DPU_INT_ERR;
+	} else if (ctx->if_type == SPRD_DPU_IF_EDPI) {
+		/* use edpi as interface */
+		dpu_reg_set(ctx, REG_DPU_CFG0, BIT_DPU_IF_EDPI);
+		/* use external te */
+		dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_EDPI_FROM_EXTERNAL_PAD);
+		/* enable te */
+		dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_EDPI_TE_EN);
+
+		/* enable stop done INT */
+		int_mask |= BIT_DPU_INT_DONE;
+		/* enable TE INT */
+		int_mask |= BIT_DPU_INT_TE;
+	}
+
+	/* enable iommu va out of range read error INT */
+	int_mask |= BIT_DPU_INT_MMU_VAOR_RD;
+	/* enable iommu va out of range write error INT */
+	int_mask |= BIT_DPU_INT_MMU_VAOR_WR;
+	/* enable iommu invalid read error INT */
+	int_mask |= BIT_DPU_INT_MMU_INV_RD;
+	/* enable iommu invalid write error INT */
+	int_mask |= BIT_DPU_INT_MMU_INV_WR;
+
+	writel(int_mask, ctx->base + REG_DPU_INT_EN);
+}
+
+static void sprd_dpu_fini(struct sprd_dpu *dpu)
+{
+	struct dpu_context *ctx = &dpu->ctx;
+
+	writel(0x00, ctx->base + REG_DPU_INT_EN);
+	writel(0xff, ctx->base + REG_DPU_INT_CLR);
+}
+
+static void sprd_dpi_init(struct sprd_dpu *dpu)
+{
+	struct dpu_context *ctx = &dpu->ctx;
+	u32 reg_val;
+	u32 size;
+
+	size = (ctx->vm.vactive << 16) | ctx->vm.hactive;
+	writel(size, ctx->base + REG_PANEL_SIZE);
+	writel(size, ctx->base + REG_BLEND_SIZE);
+
+	if (ctx->if_type == SPRD_DPU_IF_DPI) {
+		/* set dpi timing */
+		reg_val = ctx->vm.hsync_len << 0 |
+			  ctx->vm.hback_porch << 8 |
+			  ctx->vm.hfront_porch << 20;
+		writel(reg_val, ctx->base + REG_DPI_H_TIMING);
+
+		reg_val = ctx->vm.vsync_len << 0 |
+			  ctx->vm.vback_porch << 8 |
+			  ctx->vm.vfront_porch << 20;
+		writel(reg_val, ctx->base + REG_DPI_V_TIMING);
+	}
+}
+
+void sprd_dpu_run(struct sprd_dpu *dpu)
+{
+	struct dpu_context *ctx = &dpu->ctx;
+
+	dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_RUN);
+
+	ctx->stopped = false;
+}
+
+void sprd_dpu_stop(struct sprd_dpu *dpu)
+{
+	struct dpu_context *ctx = &dpu->ctx;
+
+	if (ctx->if_type == SPRD_DPU_IF_DPI)
+		dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_STOP);
+
+	dpu_wait_stop_done(dpu);
+}
+
+static int sprd_plane_atomic_check(struct drm_plane *plane,
+				  struct drm_atomic_state *state)
+{
+	struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state,
+									     plane);
+	struct drm_crtc_state *crtc_state;
+	u32 fmt;
+
+	if (!plane_state->fb || !plane_state->crtc)
+		return 0;
+
+	fmt = drm_format_to_dpu(plane_state->fb);
+	if (!fmt)
+		return -EINVAL;
+
+	crtc_state = drm_atomic_get_crtc_state(plane_state->state, plane_state->crtc);
+	if (IS_ERR(crtc_state))
+		return PTR_ERR(crtc_state);
+
+	return drm_atomic_helper_check_plane_state(plane_state, crtc_state,
+						  DRM_PLANE_HELPER_NO_SCALING,
+						  DRM_PLANE_HELPER_NO_SCALING,
+						  true, true);
+}
+
+static void sprd_plane_atomic_update(struct drm_plane *drm_plane,
+				    struct drm_atomic_state *state)
+{
+	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
+									   drm_plane);
+	struct sprd_dpu *dpu = to_sprd_crtc(new_state->crtc);
+
+	/* start configure dpu layers */
+	sprd_dpu_layer(dpu, new_state);
+}
+
+static void sprd_plane_atomic_disable(struct drm_plane *drm_plane,
+				     struct drm_atomic_state *state)
+{
+	struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
+									   drm_plane);
+	struct sprd_dpu *dpu = to_sprd_crtc(old_state->crtc);
+
+	layer_reg_wr(&dpu->ctx, REG_LAY_CTRL, 0x00, old_state->zpos);
+}
+
+static void sprd_plane_create_properties(struct sprd_plane *plane, int index)
+{
+	unsigned int supported_modes = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
+				       BIT(DRM_MODE_BLEND_PREMULTI) |
+				       BIT(DRM_MODE_BLEND_COVERAGE);
+
+	/* create rotation property */
+	drm_plane_create_rotation_property(&plane->base,
+					   DRM_MODE_ROTATE_0,
+					   DRM_MODE_ROTATE_MASK |
+					   DRM_MODE_REFLECT_MASK);
+
+	/* create alpha property */
+	drm_plane_create_alpha_property(&plane->base);
+
+	/* create blend mode property */
+	drm_plane_create_blend_mode_property(&plane->base, supported_modes);
+
+	/* create zpos property */
+	drm_plane_create_zpos_immutable_property(&plane->base, index);
+}
+
+static const struct drm_plane_helper_funcs sprd_plane_helper_funcs = {
+	.atomic_check = sprd_plane_atomic_check,
+	.atomic_update = sprd_plane_atomic_update,
+	.atomic_disable = sprd_plane_atomic_disable,
+};
+
+static const struct drm_plane_funcs sprd_plane_funcs = {
+	.update_plane = drm_atomic_helper_update_plane,
+	.disable_plane	= drm_atomic_helper_disable_plane,
+	.destroy = drm_plane_cleanup,
+	.reset = drm_atomic_helper_plane_reset,
+	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
+	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
+};
+
+static struct sprd_plane *sprd_planes_init(struct drm_device *drm)
+{
+	struct sprd_plane *plane, *primary;
+	enum drm_plane_type plane_type;
+	int i;
+
+	for (i = 0; i < 6; i++) {
+		plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY :
+					DRM_PLANE_TYPE_OVERLAY;
+
+		plane = drmm_universal_plane_alloc(drm, struct sprd_plane, base,
+					       1, &sprd_plane_funcs,
+					       layer_fmts, ARRAY_SIZE(layer_fmts),
+					       NULL, plane_type, NULL);
+		if (IS_ERR(plane)) {
+			drm_err(drm, "failed to init drm plane: %d\n", i);
+			return plane;
+		}
+
+		drm_plane_helper_add(&plane->base, &sprd_plane_helper_funcs);
+
+		sprd_plane_create_properties(plane, i);
+
+		if (i == 0)
+			primary = plane;
+	}
+
+	return primary;
+}
+
+static void sprd_crtc_mode_set_nofb(struct drm_crtc *crtc)
+{
+	struct sprd_dpu *dpu = to_sprd_crtc(crtc);
+	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
+
+	drm_display_mode_to_videomode(mode, &dpu->ctx.vm);
+
+	sprd_dpi_init(dpu);
+}
+
+static void sprd_crtc_atomic_enable(struct drm_crtc *crtc,
+				   struct drm_atomic_state *state)
+{
+	struct sprd_dpu *dpu = to_sprd_crtc(crtc);
+
+	sprd_dpu_init(dpu);
+
+	drm_crtc_vblank_on(&dpu->base);
+}
+
+static void sprd_crtc_atomic_disable(struct drm_crtc *crtc,
+				    struct drm_atomic_state *state)
+{
+	struct sprd_dpu *dpu = to_sprd_crtc(crtc);
+	struct drm_device *drm = dpu->base.dev;
+
+	drm_crtc_vblank_off(&dpu->base);
+
+	sprd_dpu_fini(dpu);
+
+	spin_lock_irq(&drm->event_lock);
+	if (crtc->state->event) {
+		drm_crtc_send_vblank_event(crtc, crtc->state->event);
+		crtc->state->event = NULL;
+	}
+	spin_unlock_irq(&drm->event_lock);
+}
+
+static void sprd_crtc_atomic_flush(struct drm_crtc *crtc,
+				  struct drm_atomic_state *state)
+
+{
+	struct sprd_dpu *dpu = to_sprd_crtc(crtc);
+	struct drm_device *drm = dpu->base.dev;
+
+	sprd_dpu_flip(dpu);
+
+	spin_lock_irq(&drm->event_lock);
+	if (crtc->state->event) {
+		drm_crtc_send_vblank_event(crtc, crtc->state->event);
+		crtc->state->event = NULL;
+	}
+	spin_unlock_irq(&drm->event_lock);
+}
+
+static int sprd_crtc_enable_vblank(struct drm_crtc *crtc)
+{
+	struct sprd_dpu *dpu = to_sprd_crtc(crtc);
+
+	dpu_reg_set(&dpu->ctx, REG_DPU_INT_EN, BIT_DPU_INT_VSYNC);
+
+	return 0;
+}
+
+static void sprd_crtc_disable_vblank(struct drm_crtc *crtc)
+{
+	struct sprd_dpu *dpu = to_sprd_crtc(crtc);
+
+	dpu_reg_clr(&dpu->ctx, REG_DPU_INT_EN, BIT_DPU_INT_VSYNC);
+}
+
+static const struct drm_crtc_helper_funcs sprd_crtc_helper_funcs = {
+	.mode_set_nofb	= sprd_crtc_mode_set_nofb,
+	.atomic_flush	= sprd_crtc_atomic_flush,
+	.atomic_enable	= sprd_crtc_atomic_enable,
+	.atomic_disable	= sprd_crtc_atomic_disable,
+};
+
+static const struct drm_crtc_funcs sprd_crtc_funcs = {
+	.destroy	= drm_crtc_cleanup,
+	.set_config	= drm_atomic_helper_set_config,
+	.page_flip	= drm_atomic_helper_page_flip,
+	.reset		= drm_atomic_helper_crtc_reset,
+	.atomic_duplicate_state	= drm_atomic_helper_crtc_duplicate_state,
+	.atomic_destroy_state	= drm_atomic_helper_crtc_destroy_state,
+	.enable_vblank	= sprd_crtc_enable_vblank,
+	.disable_vblank	= sprd_crtc_disable_vblank,
+};
+
+static struct sprd_dpu *sprd_crtc_init(struct drm_device *drm,
+			 struct drm_plane *primary, struct device *dev)
+{
+	struct device_node *port;
+	struct sprd_dpu *dpu;
+
+	dpu = drmm_crtc_alloc_with_planes(drm, struct sprd_dpu, base,
+					primary, NULL,
+					&sprd_crtc_funcs, NULL);
+	if (IS_ERR(dpu)) {
+		drm_err(drm, "failed to init crtc\n");
+		return dpu;
+	}
+	drm_crtc_helper_add(&dpu->base, &sprd_crtc_helper_funcs);
+
+	/*
+	 * set crtc port so that drm_of_find_possible_crtcs call works
+	 */
+	port = of_graph_get_port_by_id(dev->of_node, 0);
+	if (!port) {
+		drm_err(drm, "failed to found crtc output port for %s\n",
+			  dev->of_node->full_name);
+		return ERR_PTR(-EINVAL);
+	}
+	dpu->base.port = port;
+	of_node_put(port);
+
+	return dpu;
+}
+
+static irqreturn_t sprd_dpu_isr(int irq, void *data)
+{
+	struct sprd_dpu *dpu = data;
+	struct dpu_context *ctx = &dpu->ctx;
+	u32 reg_val, int_mask = 0;
+
+	reg_val = readl(ctx->base + REG_DPU_INT_STS);
+
+	/* disable err interrupt */
+	if (reg_val & BIT_DPU_INT_ERR) {
+		int_mask |= BIT_DPU_INT_ERR;
+		drm_warn(dpu->drm, "Warning: dpu underflow!\n");
+	}
+
+	/* dpu update done isr */
+	if (reg_val & BIT_DPU_INT_UPDATE_DONE) {
+		ctx->evt_update = true;
+		wake_up_interruptible_all(&ctx->wait_queue);
+	}
+
+	/* dpu stop done isr */
+	if (reg_val & BIT_DPU_INT_DONE) {
+		ctx->evt_stop = true;
+		wake_up_interruptible_all(&ctx->wait_queue);
+	}
+
+	if (reg_val & BIT_DPU_INT_VSYNC)
+		drm_crtc_handle_vblank(&dpu->base);
+
+	int_mask |= check_mmu_isr(dpu, reg_val);
+
+	writel(reg_val, ctx->base + REG_DPU_INT_CLR);
+	dpu_reg_clr(ctx, REG_DPU_INT_EN, int_mask);
+
+	return IRQ_HANDLED;
+}
+
+static int sprd_dpu_context_init(struct sprd_dpu *dpu,
+				struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct dpu_context *ctx = &dpu->ctx;
+	struct resource *res;
+	int ret;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	ctx->base = devm_ioremap(dev, res->start, resource_size(res));
+	if (!ctx->base) {
+		dev_err(dev, "failed to map dpu registers\n");
+		return -EFAULT;
+	}
+
+	ctx->irq = platform_get_irq(pdev, 0);
+	if (ctx->irq < 0) {
+		dev_err(dev, "failed to get dpu irq\n");
+		return ctx->irq;
+	}
+
+	/* disable and clear interrupts before register dpu IRQ. */
+	writel(0x00, ctx->base + REG_DPU_INT_EN);
+	writel(0xff, ctx->base + REG_DPU_INT_CLR);
+
+	ret = devm_request_irq(dev, ctx->irq, sprd_dpu_isr,
+					IRQF_TRIGGER_NONE, "DPU", dpu);
+	if (ret) {
+		dev_err(dev, "failed to register dpu irq handler\n");
+		return ret;
+	}
+
+	init_waitqueue_head(&ctx->wait_queue);
+
+	return 0;
+}
+
+static int sprd_dpu_bind(struct device *dev, struct device *master, void *data)
+{
+	struct drm_device *drm = data;
+	struct sprd_dpu *dpu;
+	struct sprd_plane *plane;
+	int ret;
+
+	plane = sprd_planes_init(drm);
+	if (IS_ERR(plane))
+		return PTR_ERR(plane);
+
+	dpu = sprd_crtc_init(drm, &plane->base, dev);
+	if (IS_ERR(dpu))
+		return PTR_ERR(dpu);
+
+	dpu->drm = drm;
+	dev_set_drvdata(dev, dpu);
+
+	ret = sprd_dpu_context_init(dpu, dev);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static const struct component_ops dpu_component_ops = {
+	.bind = sprd_dpu_bind,
+};
+
+static const struct of_device_id dpu_match_table[] = {
+	{ .compatible = "sprd,sharkl3-dpu" },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, dpu_match_table);
+
+static int sprd_dpu_probe(struct platform_device *pdev)
+{
+	return component_add(&pdev->dev, &dpu_component_ops);
+}
+
+static int sprd_dpu_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &dpu_component_ops);
+
+	return 0;
+}
+
+struct platform_driver sprd_dpu_driver = {
+	.probe = sprd_dpu_probe,
+	.remove = sprd_dpu_remove,
+	.driver = {
+		.name = "sprd-dpu-drv",
+		.of_match_table = dpu_match_table,
+	},
+};
+
+MODULE_AUTHOR("Leon He <leon.he@unisoc.com>");
+MODULE_AUTHOR("Kevin Tang <kevin.tang@unisoc.com>");
+MODULE_DESCRIPTION("Unisoc Display Controller Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/sprd/sprd_dpu.h b/drivers/gpu/drm/sprd/sprd_dpu.h
new file mode 100644
index 000000000..157a78f24
--- /dev/null
+++ b/drivers/gpu/drm/sprd/sprd_dpu.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Unisoc Inc.
+ */
+
+#ifndef __SPRD_DPU_H__
+#define __SPRD_DPU_H__
+
+#include <linux/bug.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/string.h>
+#include <video/videomode.h>
+
+#include <drm/drm_crtc.h>
+#include <drm/drm_fourcc.h>
+#include <drm/drm_print.h>
+#include <drm/drm_vblank.h>
+#include <uapi/drm/drm_mode.h>
+
+/* DPU Layer registers offset */
+#define DPU_LAY_REG_OFFSET	0x30
+
+enum {
+	SPRD_DPU_IF_DPI,
+	SPRD_DPU_IF_EDPI,
+	SPRD_DPU_IF_LIMIT
+};
+
+/**
+ * Sprd DPU context structure
+ *
+ * @base: DPU controller base address
+ * @irq: IRQ number to install the handler for
+ * @if_type: The type of DPI interface, default is DPI mode.
+ * @vm: videomode structure to use for DPU and DPI initialization
+ * @stopped: indicates whether DPU are stopped
+ * @wait_queue: wait queue, used to wait for DPU shadow register update done and
+ * DPU stop register done interrupt signal.
+ * @evt_update: wait queue condition for DPU shadow register
+ * @evt_stop: wait queue condition for DPU stop register
+ */
+struct dpu_context {
+	void __iomem *base;
+	int irq;
+	u8 if_type;
+	struct videomode vm;
+	bool stopped;
+	wait_queue_head_t wait_queue;
+	bool evt_update;
+	bool evt_stop;
+};
+
+/**
+ * Sprd DPU device structure
+ *
+ * @crtc: crtc object
+ * @drm: A point to drm device
+ * @ctx: DPU's implementation specific context object
+ */
+struct sprd_dpu {
+	struct drm_crtc base;
+	struct drm_device *drm;
+	struct dpu_context ctx;
+};
+
+static inline struct sprd_dpu *to_sprd_crtc(struct drm_crtc *crtc)
+{
+	return container_of(crtc, struct sprd_dpu, base);
+}
+
+static inline void
+dpu_reg_set(struct dpu_context *ctx, u32 offset, u32 set_bits)
+{
+	u32 bits = readl_relaxed(ctx->base + offset);
+
+	writel(bits | set_bits, ctx->base + offset);
+}
+
+static inline void
+dpu_reg_clr(struct dpu_context *ctx, u32 offset, u32 clr_bits)
+{
+	u32 bits = readl_relaxed(ctx->base + offset);
+
+	writel(bits & ~clr_bits, ctx->base + offset);
+}
+
+static inline u32
+layer_reg_rd(struct dpu_context *ctx, u32 offset, int index)
+{
+	u32 layer_offset = offset + index * DPU_LAY_REG_OFFSET;
+
+	return readl(ctx->base + layer_offset);
+}
+
+static inline void
+layer_reg_wr(struct dpu_context *ctx, u32 offset, u32 cfg_bits, int index)
+{
+	u32 layer_offset =  offset + index * DPU_LAY_REG_OFFSET;
+
+	writel(cfg_bits, ctx->base + layer_offset);
+}
+
+void sprd_dpu_run(struct sprd_dpu *dpu);
+void sprd_dpu_stop(struct sprd_dpu *dpu);
+
+#endif
diff --git a/drivers/gpu/drm/sprd/sprd_drm.c b/drivers/gpu/drm/sprd/sprd_drm.c
index 6b00a6f27..549b71278 100644
--- a/drivers/gpu/drm/sprd/sprd_drm.c
+++ b/drivers/gpu/drm/sprd/sprd_drm.c
@@ -182,6 +182,7 @@ static struct platform_driver sprd_drm_driver = {
 
 static struct platform_driver *sprd_drm_drivers[]  = {
 	&sprd_drm_driver,
+	&sprd_dpu_driver,
 };
 
 static int __init sprd_drm_init(void)
diff --git a/drivers/gpu/drm/sprd/sprd_drm.h b/drivers/gpu/drm/sprd/sprd_drm.h
index 9781fd591..85d4a8b9f 100644
--- a/drivers/gpu/drm/sprd/sprd_drm.h
+++ b/drivers/gpu/drm/sprd/sprd_drm.h
@@ -13,4 +13,6 @@ struct sprd_drm {
 	struct drm_device drm;
 };
 
+extern struct platform_driver sprd_dpu_driver;
+
 #endif /* _SPRD_DRM_H_ */
-- 
2.29.0

[PATCH v6 5/6] dt-bindings: display: add Unisoc's mipi dsi controller bindings

[Kevin Tang]

From: Kevin Tang <kevin.tang@unisoc.com>

Adds MIPI DSI Controller
support for Unisoc's display subsystem.

v5:
  - Remove panel_in port for dsi node.

Cc: Orson Zhai <orsonzhai@gmail.com>
Cc: Chunyan Zhang <zhang.lyra@gmail.com>
Signed-off-by: Kevin Tang <kevin.tang@unisoc.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../display/sprd/sprd,sharkl3-dsi-host.yaml   | 88 +++++++++++++++++++
 1 file changed, 88 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dsi-host.yaml

diff --git a/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dsi-host.yaml b/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dsi-host.yaml
new file mode 100644
index 000000000..bc5594d18
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dsi-host.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/sprd/sprd,sharkl3-dsi-host.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Unisoc MIPI DSI Controller
+
+maintainers:
+  - Kevin Tang <kevin.tang@unisoc.com>
+
+properties:
+  compatible:
+    const: sprd,sharkl3-dsi-host
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 2
+
+  clocks:
+    minItems: 1
+
+  clock-names:
+    items:
+      - const: clk_src_96m
+
+  power-domains:
+    maxItems: 1
+
+  ports:
+    type: object
+
+    properties:
+      "#address-cells":
+        const: 1
+
+      "#size-cells":
+        const: 0
+
+      port@0:
+        type: object
+        description:
+          A port node with endpoint definitions as defined in
+          Documentation/devicetree/bindings/media/video-interfaces.txt.
+          That port should be the input endpoint, usually coming from
+          the associated DPU.
+
+    required:
+      - "#address-cells"
+      - "#size-cells"
+      - port@0
+
+    additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/sprd,sc9860-clk.h>
+    dsi: dsi@63100000 {
+        compatible = "sprd,sharkl3-dsi-host";
+        reg = <0x63100000 0x1000>;
+        interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+          <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+        clock-names = "clk_src_96m";
+        clocks = <&pll CLK_TWPLL_96M>;
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+            port@0 {
+                reg = <0>;
+                dsi_in: endpoint {
+                    remote-endpoint = <&dpu_out>;
+                };
+            };
+        };
+    };
-- 
2.29.0

[PATCH v6 6/6] drm/sprd: add Unisoc's drm mipi dsi&dphy driver

[Kevin Tang]

Adds dsi host controller support for the Unisoc's display subsystem.
Adds dsi phy support for the Unisoc's display subsystem.
Only MIPI DSI Displays supported, DP/TV/HMDI will be support
in the feature.

v1:
  - Remove dphy and dsi graph binding, merge the dphy driver into the dsi.

v2:
  - Use drm_xxx to replace all DRM_XXX.
  - Use kzalloc to replace devm_kzalloc for sprd_dsi structure init.

v4:
  - Use drmm_helpers to allocate encoder.
  - Move allocate encoder and connector to bind function.

v5:
  - Drop the dsi ip file prefix.
  - Fix the checkpatch warnings.
  - Add Signed-off-by for dsi&dphy patch.
  - Use the mode_flags of mipi_dsi_device to setup crtc DPI and EDPI mode.

v6:
  - Redesign the way to access the dsi register.
  - Reduce the dsi_context member variables.
---
 drivers/gpu/drm/sprd/Kconfig         |    1 +
 drivers/gpu/drm/sprd/Makefile        |    4 +-
 drivers/gpu/drm/sprd/megacores_pll.c |  317 +++++++
 drivers/gpu/drm/sprd/megacores_pll.h |  146 +++
 drivers/gpu/drm/sprd/sprd_dpu.c      |   17 +
 drivers/gpu/drm/sprd/sprd_drm.c      |    1 +
 drivers/gpu/drm/sprd/sprd_drm.h      |    1 +
 drivers/gpu/drm/sprd/sprd_dsi.c      | 1260 ++++++++++++++++++++++++++
 drivers/gpu/drm/sprd/sprd_dsi.h      |   94 ++
 9 files changed, 1840 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/sprd/megacores_pll.c
 create mode 100644 drivers/gpu/drm/sprd/megacores_pll.h
 create mode 100644 drivers/gpu/drm/sprd/sprd_dsi.c
 create mode 100644 drivers/gpu/drm/sprd/sprd_dsi.h

diff --git a/drivers/gpu/drm/sprd/Kconfig b/drivers/gpu/drm/sprd/Kconfig
index 37762c333..3edeaeca0 100644
--- a/drivers/gpu/drm/sprd/Kconfig
+++ b/drivers/gpu/drm/sprd/Kconfig
@@ -5,6 +5,7 @@ config DRM_SPRD
 	select DRM_GEM_CMA_HELPER
 	select DRM_KMS_CMA_HELPER
 	select DRM_KMS_HELPER
+	select DRM_MIPI_DSI
 	select VIDEOMODE_HELPERS
 	help
 	  Choose this option if you have a Unisoc chipset.
diff --git a/drivers/gpu/drm/sprd/Makefile b/drivers/gpu/drm/sprd/Makefile
index ab12b95e6..73f96c459 100644
--- a/drivers/gpu/drm/sprd/Makefile
+++ b/drivers/gpu/drm/sprd/Makefile
@@ -1,4 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 
 obj-y := sprd_drm.o \
-	sprd_dpu.o
+	sprd_dpu.o \
+	sprd_dsi.o \
+	megacores_pll.o
diff --git a/drivers/gpu/drm/sprd/megacores_pll.c b/drivers/gpu/drm/sprd/megacores_pll.c
new file mode 100644
index 000000000..0dfd3c372
--- /dev/null
+++ b/drivers/gpu/drm/sprd/megacores_pll.c
@@ -0,0 +1,317 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Unisoc Inc.
+ */
+
+#include <asm/div64.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/regmap.h>
+#include <linux/string.h>
+
+#include "megacores_pll.h"
+
+#define L						0
+#define H						1
+#define CLK						0
+#define DATA					1
+#define INFINITY				0xffffffff
+#define MIN_OUTPUT_FREQ			(100)
+
+#define AVERAGE(a, b) (min(a, b) + abs((b) - (a)) / 2)
+
+/* sharkle */
+#define VCO_BAND_LOW	750
+#define VCO_BAND_MID	1100
+#define VCO_BAND_HIGH	1500
+#define PHY_REF_CLK	26000
+
+static int dphy_calc_pll_param(struct dphy_pll *pll)
+{
+	const u32 khz = 1000;
+	const u32 mhz = 1000000;
+	const unsigned long long factor = 100;
+	unsigned long long tmp;
+	int i;
+
+	pll->potential_fvco = pll->freq / khz;
+	pll->ref_clk = PHY_REF_CLK / khz;
+
+	for (i = 0; i < 4; ++i) {
+		if (pll->potential_fvco >= VCO_BAND_LOW &&
+			pll->potential_fvco <= VCO_BAND_HIGH) {
+			pll->fvco = pll->potential_fvco;
+			pll->out_sel = BIT(i);
+			break;
+		}
+		pll->potential_fvco <<= 1;
+	}
+	if (pll->fvco == 0)
+		return -EINVAL;
+
+	if (pll->fvco >= VCO_BAND_LOW && pll->fvco <= VCO_BAND_MID) {
+		/* vco band control */
+		pll->vco_band = 0x0;
+		/* low pass filter control */
+		pll->lpf_sel = 1;
+	} else if (pll->fvco > VCO_BAND_MID && pll->fvco <= VCO_BAND_HIGH) {
+		pll->vco_band = 0x1;
+		pll->lpf_sel = 0;
+	} else
+		return -EINVAL;
+
+	pll->nint = pll->fvco / pll->ref_clk;
+	tmp = pll->fvco * factor * mhz;
+	do_div(tmp, pll->ref_clk);
+	tmp = tmp - pll->nint * factor * mhz;
+	tmp *= BIT(20);
+	do_div(tmp, 100000000);
+	pll->kint = (u32)tmp;
+	pll->refin = 3; /* pre-divider bypass */
+	pll->sdm_en = true; /* use fraction N PLL */
+	pll->fdk_s = 0x1; /* fraction */
+	pll->cp_s = 0x0;
+	pll->det_delay = 0x1;
+
+	return 0;
+}
+
+static void dphy_set_pll_reg(struct dphy_pll *pll, struct regmap *regmap)
+{
+	struct pll_reg *reg = &pll->reg;
+	u8 *val;
+	int i;
+
+	u8 reg_addr[] = {
+		0x03, 0x04, 0x06, 0x08, 0x09,
+		0x0a, 0x0b, 0x0e, 0x0f
+	};
+
+	reg->_03.bits.prbs_bist = 1;
+	reg->_03.bits.en_lp_treot = true;
+	reg->_03.bits.lpf_sel = pll->lpf_sel;
+	reg->_03.bits.txfifo_bypass = 0;
+	reg->_04.bits.div = pll->div;
+	reg->_04.bits.masterof8lane = 1;
+	reg->_04.bits.cp_s = pll->cp_s;
+	reg->_04.bits.fdk_s = pll->fdk_s;
+	reg->_06.bits.nint = pll->nint;
+	reg->_08.bits.vco_band = pll->vco_band;
+	reg->_08.bits.sdm_en = pll->sdm_en;
+	reg->_08.bits.refin = pll->refin;
+	reg->_09.bits.kint_h = pll->kint >> 12;
+	reg->_0a.bits.kint_m = (pll->kint >> 4) & 0xff;
+	reg->_0b.bits.out_sel = pll->out_sel;
+	reg->_0b.bits.kint_l = pll->kint & 0xf;
+	reg->_0e.bits.pll_pu_byp = 0;
+	reg->_0e.bits.pll_pu = 0;
+	reg->_0e.bits.stopstate_sel = 1;
+	reg->_0f.bits.det_delay = pll->det_delay;
+
+	val = (u8 *)&reg;
+
+	for (i = 0; i < sizeof(reg_addr); ++i) {
+		regmap_write(regmap, reg_addr[i], val[i]);
+		DRM_DEBUG("%02x: %02x\n", reg_addr[i], val[i]);
+	}
+}
+
+int dphy_pll_config(struct dsi_context *ctx)
+{
+	struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
+	struct regmap *regmap = ctx->regmap;
+	struct dphy_pll *pll = ctx->pll;
+	int ret;
+
+	pll->freq = dsi->slave->hs_rate;
+
+	/* FREQ = 26M * (NINT + KINT / 2^20) / out_sel */
+	ret = dphy_calc_pll_param(pll);
+	if (ret) {
+		drm_err(dsi->drm, "failed to calculate dphy pll parameters\n");
+		return ret;
+	}
+	dphy_set_pll_reg(pll, regmap);
+
+	return 0;
+}
+
+static void dphy_set_timing_reg(struct regmap *regmap, int type, u8 val[])
+{
+	switch (type) {
+	case REQUEST_TIME:
+		regmap_write(regmap, 0x31, val[CLK]);
+		regmap_write(regmap, 0x41, val[DATA]);
+		regmap_write(regmap, 0x51, val[DATA]);
+		regmap_write(regmap, 0x61, val[DATA]);
+		regmap_write(regmap, 0x71, val[DATA]);
+
+		regmap_write(regmap, 0x90, val[CLK]);
+		regmap_write(regmap, 0xa0, val[DATA]);
+		regmap_write(regmap, 0xb0, val[DATA]);
+		regmap_write(regmap, 0xc0, val[DATA]);
+		regmap_write(regmap, 0xd0, val[DATA]);
+		break;
+	case PREPARE_TIME:
+		regmap_write(regmap, 0x32, val[CLK]);
+		regmap_write(regmap, 0x42, val[DATA]);
+		regmap_write(regmap, 0x52, val[DATA]);
+		regmap_write(regmap, 0x62, val[DATA]);
+		regmap_write(regmap, 0x72, val[DATA]);
+
+		regmap_write(regmap, 0x91, val[CLK]);
+		regmap_write(regmap, 0xa1, val[DATA]);
+		regmap_write(regmap, 0xb1, val[DATA]);
+		regmap_write(regmap, 0xc1, val[DATA]);
+		regmap_write(regmap, 0xd1, val[DATA]);
+		break;
+	case ZERO_TIME:
+		regmap_write(regmap, 0x33, val[CLK]);
+		regmap_write(regmap, 0x43, val[DATA]);
+		regmap_write(regmap, 0x53, val[DATA]);
+		regmap_write(regmap, 0x63, val[DATA]);
+		regmap_write(regmap, 0x73, val[DATA]);
+
+		regmap_write(regmap, 0x92, val[CLK]);
+		regmap_write(regmap, 0xa2, val[DATA]);
+		regmap_write(regmap, 0xb2, val[DATA]);
+		regmap_write(regmap, 0xc2, val[DATA]);
+		regmap_write(regmap, 0xd2, val[DATA]);
+		break;
+	case TRAIL_TIME:
+		regmap_write(regmap, 0x34, val[CLK]);
+		regmap_write(regmap, 0x44, val[DATA]);
+		regmap_write(regmap, 0x54, val[DATA]);
+		regmap_write(regmap, 0x64, val[DATA]);
+		regmap_write(regmap, 0x74, val[DATA]);
+
+		regmap_write(regmap, 0x93, val[CLK]);
+		regmap_write(regmap, 0xa3, val[DATA]);
+		regmap_write(regmap, 0xb3, val[DATA]);
+		regmap_write(regmap, 0xc3, val[DATA]);
+		regmap_write(regmap, 0xd3, val[DATA]);
+		break;
+	case EXIT_TIME:
+		regmap_write(regmap, 0x36, val[CLK]);
+		regmap_write(regmap, 0x46, val[DATA]);
+		regmap_write(regmap, 0x56, val[DATA]);
+		regmap_write(regmap, 0x66, val[DATA]);
+		regmap_write(regmap, 0x76, val[DATA]);
+
+		regmap_write(regmap, 0x95, val[CLK]);
+		regmap_write(regmap, 0xA5, val[DATA]);
+		regmap_write(regmap, 0xB5, val[DATA]);
+		regmap_write(regmap, 0xc5, val[DATA]);
+		regmap_write(regmap, 0xd5, val[DATA]);
+		break;
+	case CLKPOST_TIME:
+		regmap_write(regmap, 0x35, val[CLK]);
+		regmap_write(regmap, 0x94, val[CLK]);
+		break;
+
+	/* the following just use default value */
+	case SETTLE_TIME:
+	case TA_GET:
+	case TA_GO:
+	case TA_SURE:
+		break;
+	default:
+		break;
+	}
+}
+
+void dphy_timing_config(struct dsi_context *ctx)
+{
+	struct regmap *regmap = ctx->regmap;
+	struct dphy_pll *pll = ctx->pll;
+	const u32 factor = 2;
+	const u32 scale = 100;
+	u32 t_ui, t_byteck, t_half_byteck;
+	u32 range[2], constant;
+	u8 val[2];
+	u32 tmp = 0;
+
+	/* t_ui: 1 ui, byteck: 8 ui, half byteck: 4 ui */
+	t_ui = 1000 * scale / (pll->freq / 1000);
+	t_byteck = t_ui << 3;
+	t_half_byteck = t_ui << 2;
+	constant = t_ui << 1;
+
+	/* REQUEST_TIME: HS T-LPX: LP-01
+	 * For T-LPX, mipi spec defined min value is 50ns,
+	 * but maybe it shouldn't be too small, because BTA,
+	 * LP-10, LP-00, LP-01, all of this is related to T-LPX.
+	 */
+	range[L] = 50 * scale;
+	range[H] = INFINITY;
+	val[CLK] = DIV_ROUND_UP(range[L] * (factor << 1), t_byteck) - 2;
+	val[DATA] = val[CLK];
+	dphy_set_timing_reg(regmap, REQUEST_TIME, val);
+
+	/* PREPARE_TIME: HS sequence: LP-00 */
+	range[L] = 38 * scale;
+	range[H] = 95 * scale;
+	tmp = AVERAGE(range[L], range[H]);
+	val[CLK] = DIV_ROUND_UP(AVERAGE(range[L], range[H]),
+			t_half_byteck) - 1;
+	range[L] = 40 * scale + 4 * t_ui;
+	range[H] = 85 * scale + 6 * t_ui;
+	tmp |= AVERAGE(range[L], range[H]) << 16;
+	val[DATA] = DIV_ROUND_UP(AVERAGE(range[L], range[H]),
+			t_half_byteck) - 1;
+	dphy_set_timing_reg(regmap, PREPARE_TIME, val);
+
+	/* ZERO_TIME: HS-ZERO */
+	range[L] = 300 * scale;
+	range[H] = INFINITY;
+	val[CLK] = DIV_ROUND_UP(range[L] * factor + (tmp & 0xffff)
+			- 525 * t_byteck / 100, t_byteck) - 2;
+	range[L] = 145 * scale + 10 * t_ui;
+	val[DATA] = DIV_ROUND_UP(range[L] * factor
+			+ ((tmp >> 16) & 0xffff) - 525 * t_byteck / 100,
+			t_byteck) - 2;
+	dphy_set_timing_reg(regmap, ZERO_TIME, val);
+
+	/* TRAIL_TIME: HS-TRAIL */
+	range[L] = 60 * scale;
+	range[H] = INFINITY;
+	val[CLK] = DIV_ROUND_UP(range[L] * factor - constant, t_half_byteck);
+	range[L] = max(8 * t_ui, 60 * scale + 4 * t_ui);
+	val[DATA] = DIV_ROUND_UP(range[L] * 3 / 2 - constant, t_half_byteck) - 2;
+	dphy_set_timing_reg(regmap, TRAIL_TIME, val);
+
+	/* EXIT_TIME: */
+	range[L] = 100 * scale;
+	range[H] = INFINITY;
+	val[CLK] = DIV_ROUND_UP(range[L] * factor, t_byteck) - 2;
+	val[DATA] = val[CLK];
+	dphy_set_timing_reg(regmap, EXIT_TIME, val);
+
+	/* CLKPOST_TIME: */
+	range[L] = 60 * scale + 52 * t_ui;
+	range[H] = INFINITY;
+	val[CLK] = DIV_ROUND_UP(range[L] * factor, t_byteck) - 2;
+	val[DATA] = val[CLK];
+	dphy_set_timing_reg(regmap, CLKPOST_TIME, val);
+
+	/* SETTLE_TIME:
+	 * This time is used for receiver. So for transmitter,
+	 * it can be ignored.
+	 */
+
+	/* TA_GO:
+	 * transmitter drives bridge state(LP-00) before releasing control,
+	 * reg 0x1f default value: 0x04, which is good.
+	 */
+
+	/* TA_SURE:
+	 * After LP-10 state and before bridge state(LP-00),
+	 * reg 0x20 default value: 0x01, which is good.
+	 */
+
+	/* TA_GET:
+	 * receiver drives Bridge state(LP-00) before releasing control
+	 * reg 0x21 default value: 0x03, which is good.
+	 */
+}
diff --git a/drivers/gpu/drm/sprd/megacores_pll.h b/drivers/gpu/drm/sprd/megacores_pll.h
new file mode 100644
index 000000000..bf20aae65
--- /dev/null
+++ b/drivers/gpu/drm/sprd/megacores_pll.h
@@ -0,0 +1,146 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Unisoc Inc.
+ */
+
+#ifndef _MEGACORES_PLL_H_
+#define _MEGACORES_PLL_H_
+
+#include "sprd_dsi.h"
+
+enum PLL_TIMING {
+	NONE,
+	REQUEST_TIME,
+	PREPARE_TIME,
+	SETTLE_TIME,
+	ZERO_TIME,
+	TRAIL_TIME,
+	EXIT_TIME,
+	CLKPOST_TIME,
+	TA_GET,
+	TA_GO,
+	TA_SURE,
+	TA_WAIT,
+};
+
+struct pll_reg {
+	union __reg_03__ {
+		struct __03 {
+			u8 prbs_bist: 1;
+			u8 en_lp_treot: 1;
+			u8 lpf_sel: 4;
+			u8 txfifo_bypass: 1;
+			u8 freq_hopping: 1;
+		} bits;
+		u8 val;
+	} _03;
+	union __reg_04__ {
+		struct __04 {
+			u8 div: 3;
+			u8 masterof8lane: 1;
+			u8 hop_trig: 1;
+			u8 cp_s: 2;
+			u8 fdk_s: 1;
+		} bits;
+		u8 val;
+	} _04;
+	union __reg_06__ {
+		struct __06 {
+			u8 nint: 7;
+			u8 mod_en: 1;
+		} bits;
+		u8 val;
+	} _06;
+	union __reg_07__ {
+		struct __07 {
+			u8 kdelta_h: 8;
+		} bits;
+		u8 val;
+	} _07;
+	union __reg_08__ {
+		struct __08 {
+			u8 vco_band: 1;
+			u8 sdm_en: 1;
+			u8 refin: 2;
+			u8 kdelta_l: 4;
+		} bits;
+		u8 val;
+	} _08;
+	union __reg_09__ {
+		struct __09 {
+			u8 kint_h: 8;
+		} bits;
+		u8 val;
+	} _09;
+	union __reg_0a__ {
+		struct __0a {
+			u8 kint_m: 8;
+		} bits;
+		u8 val;
+	} _0a;
+	union __reg_0b__ {
+		struct __0b {
+			u8 out_sel: 4;
+			u8 kint_l: 4;
+		} bits;
+		u8 val;
+	} _0b;
+	union __reg_0c__ {
+		struct __0c {
+			u8 kstep_h: 8;
+		} bits;
+		u8 val;
+	} _0c;
+	union __reg_0d__ {
+		struct __0d {
+			u8 kstep_m: 8;
+		} bits;
+		u8 val;
+	} _0d;
+	union __reg_0e__ {
+		struct __0e {
+			u8 pll_pu_byp: 1;
+			u8 pll_pu: 1;
+			u8 hsbist_len: 2;
+			u8 stopstate_sel: 1;
+			u8 kstep_l: 3;
+		} bits;
+		u8 val;
+	} _0e;
+	union __reg_0f__ {
+		struct __0f {
+			u8 det_delay:2;
+			u8 kdelta: 4;
+			u8 ldo0p4:2;
+		} bits;
+		u8 val;
+	} _0f;
+};
+
+struct dphy_pll {
+	u8 refin; /* Pre-divider control signal */
+	u8 cp_s; /* 00: SDM_EN=1, 10: SDM_EN=0 */
+	u8 fdk_s; /* PLL mode control: integer or fraction */
+	u8 sdm_en;
+	u8 div;
+	u8 int_n; /* integer N PLL */
+	u32 ref_clk; /* dphy reference clock, unit: MHz */
+	u32 freq; /* panel config, unit: KHz */
+	u32 fvco;
+	u32 potential_fvco;
+	u32 nint; /* sigma delta modulator NINT control */
+	u32 kint; /* sigma delta modulator KINT control */
+	u8 lpf_sel; /* low pass filter control */
+	u8 out_sel; /* post divider control */
+	u8 vco_band; /* vco range */
+	u8 det_delay;
+
+	struct pll_reg reg;
+};
+
+struct dsi_context;
+
+int dphy_pll_config(struct dsi_context *ctx);
+void dphy_timing_config(struct dsi_context *ctx);
+
+#endif /* _MEGACORES_PLL_H_ */
diff --git a/drivers/gpu/drm/sprd/sprd_dpu.c b/drivers/gpu/drm/sprd/sprd_dpu.c
index 448dd4fb6..4e3b30abe 100644
--- a/drivers/gpu/drm/sprd/sprd_dpu.c
+++ b/drivers/gpu/drm/sprd/sprd_dpu.c
@@ -25,6 +25,7 @@
 
 #include "sprd_drm.h"
 #include "sprd_dpu.h"
+#include "sprd_dsi.h"
 
 /* Global control registers */
 #define REG_DPU_CTRL	0x04
@@ -686,9 +687,25 @@ static void sprd_crtc_mode_set_nofb(struct drm_crtc *crtc)
 {
 	struct sprd_dpu *dpu = to_sprd_crtc(crtc);
 	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
+	struct drm_encoder *encoder;
+	struct mipi_dsi_device *slave;
+	struct sprd_dsi *dsi;
 
 	drm_display_mode_to_videomode(mode, &dpu->ctx.vm);
 
+	drm_for_each_encoder(encoder, crtc->dev) {
+		if (encoder->crtc != crtc)
+			continue;
+
+		dsi = encoder_to_dsi(encoder);
+		slave = dsi->slave;
+
+		if (slave->mode_flags & MIPI_DSI_MODE_VIDEO)
+			dpu->ctx.if_type = SPRD_DPU_IF_DPI;
+		else
+			dpu->ctx.if_type = SPRD_DPU_IF_EDPI;
+	}
+
 	sprd_dpi_init(dpu);
 }
 
diff --git a/drivers/gpu/drm/sprd/sprd_drm.c b/drivers/gpu/drm/sprd/sprd_drm.c
index 549b71278..68cf0933c 100644
--- a/drivers/gpu/drm/sprd/sprd_drm.c
+++ b/drivers/gpu/drm/sprd/sprd_drm.c
@@ -183,6 +183,7 @@ static struct platform_driver sprd_drm_driver = {
 static struct platform_driver *sprd_drm_drivers[]  = {
 	&sprd_drm_driver,
 	&sprd_dpu_driver,
+	&sprd_dsi_driver,
 };
 
 static int __init sprd_drm_init(void)
diff --git a/drivers/gpu/drm/sprd/sprd_drm.h b/drivers/gpu/drm/sprd/sprd_drm.h
index 85d4a8b9f..95d1b972f 100644
--- a/drivers/gpu/drm/sprd/sprd_drm.h
+++ b/drivers/gpu/drm/sprd/sprd_drm.h
@@ -14,5 +14,6 @@ struct sprd_drm {
 };
 
 extern struct platform_driver sprd_dpu_driver;
+extern struct platform_driver sprd_dsi_driver;
 
 #endif /* _SPRD_DRM_H_ */
diff --git a/drivers/gpu/drm/sprd/sprd_dsi.c b/drivers/gpu/drm/sprd/sprd_dsi.c
new file mode 100644
index 000000000..5ce98fe90
--- /dev/null
+++ b/drivers/gpu/drm/sprd/sprd_dsi.c
@@ -0,0 +1,1260 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Unisoc Inc.
+ */
+
+#include <linux/component.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/of_graph.h>
+#include <video/mipi_display.h>
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_of.h>
+#include <drm/drm_probe_helper.h>
+
+#include "sprd_drm.h"
+#include "sprd_dpu.h"
+#include "sprd_dsi.h"
+
+#define SOFT_RESET 0x04
+#define MASK_PROTOCOL_INT 0x0C
+#define MASK_INTERNAL_INT 0x14
+#define DSI_MODE_CFG 0x18
+
+#define VIRTUAL_CHANNEL_ID 0x1C
+#define GEN_RX_VCID GENMASK(1, 0)
+#define VIDEO_PKT_VCID GENMASK(3, 2)
+
+#define DPI_VIDEO_FORMAT 0x20
+#define DPI_VIDEO_MODE_FORMAT GENMASK(5, 0)
+#define LOOSELY18_EN BIT(6)
+
+#define VIDEO_PKT_CONFIG 0x24
+#define VIDEO_PKT_SIZE GENMASK(15, 0)
+#define VIDEO_LINE_CHUNK_NUM GENMASK(31, 16)
+
+#define VIDEO_LINE_HBLK_TIME 0x28
+#define VIDEO_LINE_HBP_TIME GENMASK(15, 0)
+#define VIDEO_LINE_HSA_TIME GENMASK(31, 16)
+
+#define VIDEO_LINE_TIME 0x2C
+
+#define VIDEO_VBLK_LINES 0x30
+#define VFP_LINES GENMASK(9, 0)
+#define VBP_LINES GENMASK(19, 10)
+#define VSA_LINES GENMASK(29, 20)
+
+#define VIDEO_VACTIVE_LINES 0x34
+
+#define VID_MODE_CFG 0x38
+#define VID_MODE_TYPE GENMASK(1, 0)
+#define LP_VSA_EN BIT(8)
+#define LP_VBP_EN BIT(9)
+#define LP_VFP_EN BIT(10)
+#define LP_VACT_EN BIT(11)
+#define LP_HBP_EN BIT(12)
+#define LP_HFP_EN BIT(13)
+#define FRAME_BTA_ACK_EN BIT(14)
+#define LP_CMD_EN BIT(15)
+
+#define TIMEOUT_CNT_CLK_CONFIG 0x40
+#define HTX_TO_CONFIG 0x44
+#define LRX_H_TO_CONFIG 0x48
+
+#define TX_ESC_CLK_CONFIG 0x5C
+
+#define CMD_MODE_CFG 0x68
+#define TEAR_FX_EN BIT(0)
+#define ACK_RQST_EN BIT(1)
+#define PPS_TX BIT(5)
+#define EXQ_TX BIT(6)
+#define CMC_TX BIT(7)
+#define GEN_SW_0P_TX BIT(8)
+#define GEN_SW_1P_TX BIT(9)
+#define GEN_SW_2P_TX BIT(10)
+#define GEN_SR_0P_TX BIT(11)
+#define GEN_SR_1P_TX BIT(12)
+#define GEN_SR_2P_TX BIT(13)
+#define GEN_LW_TX BIT(14)
+#define DCS_SW_0P_TX BIT(16)
+#define DCS_SW_1P_TX BIT(17)
+#define DCS_SR_0P_TX BIT(18)
+#define DCS_LW_TX BIT(19)
+#define MAX_RD_PKT_SIZE BIT(24)
+
+#define GEN_HDR 0x6C
+#define GEN_DT GENMASK(5, 0)
+#define GEN_VC GENMASK(7, 6)
+#define GEN_WC_LSBYTE GENMASK(15, 8)
+#define GEN_WC_MSBYTE GENMASK(23, 16)
+
+#define GEN_PLD_DATA 0x70
+#define GEN_PLD_B1 GENMASK(7, 0)
+#define GEN_PLD_B2 GENMASK(15, 8)
+#define GEN_PLD_B3 GENMASK(23, 16)
+#define GEN_PLD_B4 GENMASK(31, 24)
+
+#define PHY_CLK_LANE_LP_CTRL 0x74
+#define PHY_CLKLANE_TX_REQ_HS BIT(0)
+#define AUTO_CLKLANE_CTRL_EN BIT(1)
+
+#define PHY_INTERFACE_CTRL 0x78
+#define RF_PHY_SHUTDOWN BIT(0)
+#define RF_PHY_RESET_N BIT(1)
+#define RF_PHY_CLK_EN BIT(2)
+
+#define CMD_MODE_STATUS 0x98
+#define GEN_CMD_RDCMD_ONGOING BIT(0)
+#define GEN_CMD_RDATA_FIFO_EMPTY BIT(1)
+#define GEN_CMD_RDATA_FIFO_FULL BIT(2)
+#define GEN_CMD_WDATA_FIFO_EMPTY BIT(3)
+#define GEN_CMD_WDATA_FIFO_FULL BIT(4)
+#define GEN_CMD_CMD_FIFO_EMPTY BIT(5)
+#define GEN_CMD_CMD_FIFO_FULL BIT(6)
+#define GEN_CMD_RDCMD_DONE BIT(7)
+
+#define PHY_STATUS 0x9C
+#define PHY_LOCK BIT(1)
+
+#define PHY_MIN_STOP_TIME 0xA0
+#define PHY_LANE_NUM_CONFIG 0xA4
+
+#define PHY_CLKLANE_TIME_CONFIG 0xA8
+#define PHY_CLKLANE_LP_TO_HS_TIME GENMASK(15, 0)
+#define PHY_CLKLANE_HS_TO_LP_TIME GENMASK(31, 16)
+
+#define PHY_DATALANE_TIME_CONFIG 0xAC
+#define PHY_DATALANE_LP_TO_HS_TIME GENMASK(15, 0)
+#define PHY_DATALANE_HS_TO_LP_TIME GENMASK(31, 16)
+
+#define MAX_READ_TIME 0xB0
+
+#define RX_PKT_CHECK_CONFIG 0xB4
+#define RX_PKT_ECC_EN BIT(0)
+#define RX_PKT_CRC_EN BIT(1)
+
+#define TA_EN 0xB8
+
+#define EOTP_EN 0xBC
+#define TX_EOTP_EN BIT(0)
+#define RX_EOTP_EN BIT(1)
+
+#define VIDEO_NULLPKT_SIZE 0xC0
+#define DCS_WM_PKT_SIZE 0xC4
+#define PROTOCOL_INT_CLR 0xC8
+#define INTERNAL_INT_CLR 0xCC
+
+#define VIDEO_SIG_DELAY_CONFIG 0xD0
+#define VIDEO_SIG_DELAY GENMASK(23, 0)
+#define VIDEO_SIG_DELAY_MODE BIT(24)
+
+#define PHY_TST_CTRL0 0xF0
+#define PHY_TESTCLR BIT(0)
+#define PHY_TESTCLK BIT(1)
+
+#define PHY_TST_CTRL1 0xF4
+#define PHY_TESTDIN GENMASK(7, 0)
+#define PHY_TESTDOUT GENMASK(15, 8)
+#define PHY_TESTEN BIT(16)
+
+#define host_to_dsi(host) \
+	container_of(host, struct sprd_dsi, host)
+#define connector_to_dsi(connector) \
+	container_of(connector, struct sprd_dsi, connector)
+
+static inline u32
+dsi_reg_rd(struct dsi_context *ctx, u32 offset, u32 mask,
+			u32 shift)
+{
+	return (readl(ctx->base + offset) & mask) >> shift;
+}
+
+static inline void
+dsi_reg_wr(struct dsi_context *ctx, u32 offset, u32 mask,
+			u32 shift, u32 val)
+{
+	u32 ret;
+
+	ret = readl(ctx->base + offset);
+	ret &= ~mask;
+	ret |= (val << shift) & mask;
+	writel(ret, ctx->base + offset);
+}
+
+static inline void
+dsi_reg_up(struct dsi_context *ctx, u32 offset, u32 mask,
+			u32 val)
+{
+	u32 ret = readl(ctx->base + offset);
+
+	writel((ret & ~mask) | (val & mask), ctx->base + offset);
+}
+
+static int regmap_tst_io_write(void *context, u32 reg, u32 val)
+{
+	struct sprd_dsi *dsi = context;
+	struct dsi_context *ctx = &dsi->ctx;
+
+	if (val > 0xff || reg > 0xff)
+		return -EINVAL;
+
+	drm_dbg(dsi->drm, "reg = 0x%02x, val = 0x%02x\n", reg, val);
+
+	dsi_reg_up(ctx, PHY_TST_CTRL1, PHY_TESTEN, PHY_TESTEN);
+	dsi_reg_wr(ctx, PHY_TST_CTRL1, PHY_TESTDIN, 0, reg);
+	dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, PHY_TESTCLK);
+	dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, 0);
+	dsi_reg_up(ctx, PHY_TST_CTRL1, PHY_TESTEN, 0);
+	dsi_reg_wr(ctx, PHY_TST_CTRL1, PHY_TESTDIN, 0, val);
+	dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, PHY_TESTCLK);
+	dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, 0);
+
+	return 0;
+}
+
+static int regmap_tst_io_read(void *context, u32 reg, u32 *val)
+{
+	struct sprd_dsi *dsi = context;
+	struct dsi_context *ctx = &dsi->ctx;
+	int ret;
+
+	if (reg > 0xff)
+		return -EINVAL;
+
+	dsi_reg_up(ctx, PHY_TST_CTRL1, PHY_TESTEN, PHY_TESTEN);
+	dsi_reg_wr(ctx, PHY_TST_CTRL1, PHY_TESTDIN, 0, reg);
+	dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, PHY_TESTCLK);
+	dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, 0);
+	dsi_reg_up(ctx, PHY_TST_CTRL1, PHY_TESTEN, 0);
+
+	udelay(1);
+
+	ret = dsi_reg_rd(ctx, PHY_TST_CTRL1, PHY_TESTDOUT, 8);
+	if (ret < 0)
+		return ret;
+
+	*val = ret;
+
+	drm_dbg(dsi->drm, "reg = 0x%02x, val = 0x%02x\n", reg, *val);
+	return 0;
+}
+
+static struct regmap_bus regmap_tst_io = {
+	.reg_write = regmap_tst_io_write,
+	.reg_read = regmap_tst_io_read,
+};
+
+static const struct regmap_config byte_config = {
+	.reg_bits = 8,
+	.val_bits = 8,
+};
+
+static int dphy_wait_pll_locked(struct dsi_context *ctx)
+{
+	struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
+	int i;
+
+	for (i = 0; i < 50000; i++) {
+		if (dsi_reg_rd(ctx, PHY_STATUS, PHY_LOCK, 1))
+			return 0;
+		udelay(3);
+	}
+
+	drm_err(dsi->drm, "dphy pll can not be locked\n");
+	return -ETIMEDOUT;
+}
+
+static int dsi_wait_tx_payload_fifo_empty(struct dsi_context *ctx)
+{
+	int i;
+
+	for (i = 0; i < 5000; i++) {
+		if (dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_WDATA_FIFO_EMPTY, 3))
+			return 0;
+		udelay(1);
+	}
+
+	return -ETIMEDOUT;
+}
+
+static int dsi_wait_tx_cmd_fifo_empty(struct dsi_context *ctx)
+{
+	int i;
+
+	for (i = 0; i < 5000; i++) {
+		if (dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_CMD_FIFO_EMPTY, 5))
+			return 0;
+		udelay(1);
+	}
+
+	return -ETIMEDOUT;
+}
+
+static int dsi_wait_rd_resp_completed(struct dsi_context *ctx)
+{
+	int i;
+
+	for (i = 0; i < 10000; i++) {
+		if (dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_RDCMD_DONE, 7))
+			return 0;
+		udelay(10);
+	}
+
+	return -ETIMEDOUT;
+}
+
+static u16 calc_bytes_per_pixel_x100(int coding)
+{
+	u16 Bpp_x100;
+
+	switch (coding) {
+	case COLOR_CODE_16BIT_CONFIG1:
+	case COLOR_CODE_16BIT_CONFIG2:
+	case COLOR_CODE_16BIT_CONFIG3:
+		Bpp_x100 = 200;
+		break;
+	case COLOR_CODE_18BIT_CONFIG1:
+	case COLOR_CODE_18BIT_CONFIG2:
+		Bpp_x100 = 225;
+		break;
+	case COLOR_CODE_24BIT:
+		Bpp_x100 = 300;
+		break;
+	case COLOR_CODE_COMPRESSTION:
+		Bpp_x100 = 100;
+		break;
+	case COLOR_CODE_20BIT_YCC422_LOOSELY:
+		Bpp_x100 = 250;
+		break;
+	case COLOR_CODE_24BIT_YCC422:
+		Bpp_x100 = 300;
+		break;
+	case COLOR_CODE_16BIT_YCC422:
+		Bpp_x100 = 200;
+		break;
+	case COLOR_CODE_30BIT:
+		Bpp_x100 = 375;
+		break;
+	case COLOR_CODE_36BIT:
+		Bpp_x100 = 450;
+		break;
+	case COLOR_CODE_12BIT_YCC420:
+		Bpp_x100 = 150;
+		break;
+	default:
+		DRM_ERROR("invalid color coding");
+		Bpp_x100 = 0;
+		break;
+	}
+
+	return Bpp_x100;
+}
+
+static u8 calc_video_size_step(int coding)
+{
+	u8 video_size_step;
+
+	switch (coding) {
+	case COLOR_CODE_16BIT_CONFIG1:
+	case COLOR_CODE_16BIT_CONFIG2:
+	case COLOR_CODE_16BIT_CONFIG3:
+	case COLOR_CODE_18BIT_CONFIG1:
+	case COLOR_CODE_18BIT_CONFIG2:
+	case COLOR_CODE_24BIT:
+	case COLOR_CODE_COMPRESSTION:
+		return video_size_step = 1;
+	case COLOR_CODE_20BIT_YCC422_LOOSELY:
+	case COLOR_CODE_24BIT_YCC422:
+	case COLOR_CODE_16BIT_YCC422:
+	case COLOR_CODE_30BIT:
+	case COLOR_CODE_36BIT:
+	case COLOR_CODE_12BIT_YCC420:
+		return video_size_step = 2;
+	default:
+		DRM_ERROR("invalid color coding");
+		return 0;
+	}
+}
+
+static u16 round_video_size(int coding, u16 video_size)
+{
+	switch (coding) {
+	case COLOR_CODE_16BIT_YCC422:
+	case COLOR_CODE_24BIT_YCC422:
+	case COLOR_CODE_20BIT_YCC422_LOOSELY:
+	case COLOR_CODE_12BIT_YCC420:
+		/* round up active H pixels to a multiple of 2 */
+		if ((video_size % 2) != 0)
+			video_size += 1;
+		break;
+	default:
+		break;
+	}
+
+	return video_size;
+}
+
+#define SPRD_MIPI_DSI_FMT_DSC 0xff
+static u32 fmt_to_coding(u32 fmt)
+{
+	switch (fmt) {
+	case MIPI_DSI_FMT_RGB565:
+		return COLOR_CODE_16BIT_CONFIG1;
+	case MIPI_DSI_FMT_RGB666:
+	case MIPI_DSI_FMT_RGB666_PACKED:
+		return COLOR_CODE_18BIT_CONFIG1;
+	case MIPI_DSI_FMT_RGB888:
+		return COLOR_CODE_24BIT;
+	case SPRD_MIPI_DSI_FMT_DSC:
+		return COLOR_CODE_COMPRESSTION;
+	default:
+		DRM_ERROR("Unsupported format (%d)\n", fmt);
+		return COLOR_CODE_24BIT;
+	}
+}
+
+#define ns_to_cycle(ns, byte_clk) \
+	DIV_ROUND_UP((ns) * (byte_clk), 1000000)
+
+static void sprd_dsi_init(struct dsi_context *ctx)
+{
+	struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
+	u32 byte_clk = dsi->slave->hs_rate / 8;
+	u16 data_hs2lp, data_lp2hs, clk_hs2lp, clk_lp2hs;
+	u16 max_rd_time;
+	int div;
+
+	writel(0, ctx->base + SOFT_RESET);
+	writel(0xffffffff, ctx->base + MASK_PROTOCOL_INT);
+	writel(0xffffffff, ctx->base + MASK_INTERNAL_INT);
+	writel(1, ctx->base + DSI_MODE_CFG);
+	dsi_reg_up(ctx, EOTP_EN, RX_EOTP_EN, 0);
+	dsi_reg_up(ctx, EOTP_EN, TX_EOTP_EN, 0);
+	dsi_reg_up(ctx, RX_PKT_CHECK_CONFIG, RX_PKT_ECC_EN, RX_PKT_ECC_EN);
+	dsi_reg_up(ctx, RX_PKT_CHECK_CONFIG, RX_PKT_CRC_EN, RX_PKT_CRC_EN);
+	writel(1, ctx->base + TA_EN);
+	dsi_reg_up(ctx, VIRTUAL_CHANNEL_ID, VIDEO_PKT_VCID, 0);
+	dsi_reg_up(ctx, VIRTUAL_CHANNEL_ID, GEN_RX_VCID, 0);
+
+	div = DIV_ROUND_UP(byte_clk, dsi->slave->lp_rate);
+	writel(div, ctx->base + TX_ESC_CLK_CONFIG);
+
+	max_rd_time = ns_to_cycle(ctx->max_rd_time, byte_clk);
+	writel(max_rd_time, ctx->base + MAX_READ_TIME);
+
+	data_hs2lp = ns_to_cycle(ctx->data_hs2lp, byte_clk);
+	data_lp2hs = ns_to_cycle(ctx->data_lp2hs, byte_clk);
+	clk_hs2lp = ns_to_cycle(ctx->clk_hs2lp, byte_clk);
+	clk_lp2hs = ns_to_cycle(ctx->clk_lp2hs, byte_clk);
+	dsi_reg_wr(ctx, PHY_DATALANE_TIME_CONFIG,
+		PHY_DATALANE_HS_TO_LP_TIME, 16, data_hs2lp);
+	dsi_reg_wr(ctx, PHY_DATALANE_TIME_CONFIG,
+		PHY_DATALANE_LP_TO_HS_TIME, 0, data_lp2hs);
+	dsi_reg_wr(ctx, PHY_CLKLANE_TIME_CONFIG,
+		PHY_CLKLANE_HS_TO_LP_TIME, 16, clk_hs2lp);
+	dsi_reg_wr(ctx, PHY_CLKLANE_TIME_CONFIG,
+		PHY_CLKLANE_LP_TO_HS_TIME, 0, clk_lp2hs);
+
+	writel(1, ctx->base + SOFT_RESET);
+}
+
+/*
+ * Free up resources and shutdown host controller and PHY
+ */
+static void sprd_dsi_fini(struct dsi_context *ctx)
+{
+	writel(0xffffffff, ctx->base + MASK_PROTOCOL_INT);
+	writel(0xffffffff, ctx->base + MASK_INTERNAL_INT);
+	writel(0, ctx->base + SOFT_RESET);
+}
+
+/*
+ * If not in burst mode, it will compute the video and null packet sizes
+ * according to necessity.
+ * Configure timers for data lanes and/or clock lane to return to LP when
+ * bandwidth is not filled by data.
+ */
+static int sprd_dsi_dpi_video(struct dsi_context *ctx)
+{
+	struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
+	struct videomode *vm = &ctx->vm;
+	u32 byte_clk = dsi->slave->hs_rate / 8;
+	u16 Bpp_x100;
+	u16 video_size;
+	u32 ratio_x1000;
+	u16 null_pkt_size = 0;
+	u8 video_size_step;
+	u32 hs_to;
+	u32 total_bytes;
+	u32 bytes_per_chunk;
+	u32 chunks = 0;
+	u32 bytes_left = 0;
+	u32 chunk_overhead;
+	const u8 pkt_header = 6;
+	u8 coding;
+	int div;
+	u16 hline;
+	u16 byte_cycle;
+
+	coding = fmt_to_coding(dsi->slave->format);
+	video_size = round_video_size(coding, vm->hactive);
+	Bpp_x100 = calc_bytes_per_pixel_x100(coding);
+	video_size_step = calc_video_size_step(coding);
+	ratio_x1000 = byte_clk * 1000 / (vm->pixelclock / 1000);
+	hline = vm->hactive + vm->hsync_len + vm->hfront_porch +
+		vm->hback_porch;
+
+	writel(0, ctx->base + SOFT_RESET);
+	dsi_reg_wr(ctx, VID_MODE_CFG, FRAME_BTA_ACK_EN, 15, ctx->frame_ack_en);
+	dsi_reg_wr(ctx, DPI_VIDEO_FORMAT, DPI_VIDEO_MODE_FORMAT, 0, coding);
+	dsi_reg_wr(ctx, VID_MODE_CFG, VID_MODE_TYPE, 0, ctx->burst_mode);
+	byte_cycle = 95 * hline * ratio_x1000 / 100000;
+	dsi_reg_wr(ctx, VIDEO_SIG_DELAY_CONFIG, VIDEO_SIG_DELAY, 0, byte_cycle);
+	byte_cycle = hline * ratio_x1000 / 1000;
+	writel(byte_cycle, ctx->base + VIDEO_LINE_TIME);
+	byte_cycle = vm->hsync_len * ratio_x1000 / 1000;
+	dsi_reg_wr(ctx, VIDEO_LINE_HBLK_TIME, VIDEO_LINE_HSA_TIME, 16, byte_cycle);
+	byte_cycle = vm->hback_porch * ratio_x1000 / 1000;
+	dsi_reg_wr(ctx, VIDEO_LINE_HBLK_TIME, VIDEO_LINE_HBP_TIME, 0, byte_cycle);
+	writel(vm->vactive, ctx->base + VIDEO_VACTIVE_LINES);
+	dsi_reg_wr(ctx, VIDEO_VBLK_LINES, VFP_LINES, 0, vm->vfront_porch);
+	dsi_reg_wr(ctx, VIDEO_VBLK_LINES, VBP_LINES, 10, vm->vback_porch);
+	dsi_reg_wr(ctx, VIDEO_VBLK_LINES, VSA_LINES, 20, vm->vsync_len);
+	dsi_reg_up(ctx, VID_MODE_CFG, LP_HBP_EN | LP_HFP_EN | LP_VACT_EN |
+			LP_VFP_EN | LP_VBP_EN | LP_VSA_EN, LP_HBP_EN | LP_HFP_EN |
+			LP_VACT_EN | LP_VFP_EN | LP_VBP_EN | LP_VSA_EN);
+
+	hs_to = (hline * vm->vactive) + (2 * Bpp_x100) / 100;
+	for (div = 0x80; (div < hs_to) && (div > 2); div--) {
+		if ((hs_to % div) == 0) {
+			writel(div, ctx->base + TIMEOUT_CNT_CLK_CONFIG);
+			writel(hs_to / div, ctx->base + LRX_H_TO_CONFIG);
+			writel(hs_to / div, ctx->base + HTX_TO_CONFIG);
+			break;
+		}
+	}
+
+	if (ctx->burst_mode == VIDEO_BURST_WITH_SYNC_PULSES) {
+		dsi_reg_wr(ctx, VIDEO_PKT_CONFIG, VIDEO_PKT_SIZE, 0, video_size);
+		writel(0, ctx->base + VIDEO_NULLPKT_SIZE);
+		dsi_reg_up(ctx, VIDEO_PKT_CONFIG, VIDEO_LINE_CHUNK_NUM, 0);
+	} else {
+		/* non burst transmission */
+		null_pkt_size = 0;
+
+		/* bytes to be sent - first as one chunk */
+		bytes_per_chunk = vm->hactive * Bpp_x100 / 100 + pkt_header;
+
+		/* hline total bytes from the DPI interface */
+		total_bytes = (vm->hactive + vm->hfront_porch) *
+				ratio_x1000 / dsi->slave->lanes / 1000;
+
+		/* check if the pixels actually fit on the DSI link */
+		if (total_bytes < bytes_per_chunk) {
+			drm_err(dsi->drm, "current resolution can not be set\n");
+			return -EINVAL;
+		}
+
+		chunk_overhead = total_bytes - bytes_per_chunk;
+
+		/* overhead higher than 1 -> enable multi packets */
+		if (chunk_overhead > 1) {
+
+			/* multi packets */
+			for (video_size = video_size_step;
+			     video_size < vm->hactive;
+			     video_size += video_size_step) {
+
+				if (vm->hactive * 1000 / video_size % 1000)
+					continue;
+
+				chunks = vm->hactive / video_size;
+				bytes_per_chunk = Bpp_x100 * video_size / 100
+						  + pkt_header;
+				if (total_bytes >= (bytes_per_chunk * chunks)) {
+					bytes_left = total_bytes -
+						     bytes_per_chunk * chunks;
+					break;
+				}
+			}
+
+			/* prevent overflow (unsigned - unsigned) */
+			if (bytes_left > (pkt_header * chunks)) {
+				null_pkt_size = (bytes_left -
+						pkt_header * chunks) / chunks;
+				/* avoid register overflow */
+				if (null_pkt_size > 1023)
+					null_pkt_size = 1023;
+			}
+
+		} else {
+
+			/* single packet */
+			chunks = 1;
+
+			/* must be a multiple of 4 except 18 loosely */
+			for (video_size = vm->hactive;
+			    (video_size % video_size_step) != 0;
+			     video_size++)
+				;
+		}
+
+		dsi_reg_wr(ctx, VIDEO_PKT_CONFIG, VIDEO_PKT_SIZE, 0, video_size);
+		writel(null_pkt_size, ctx->base + VIDEO_NULLPKT_SIZE);
+		dsi_reg_wr(ctx, VIDEO_PKT_CONFIG, VIDEO_LINE_CHUNK_NUM, 16, chunks);
+	}
+
+	writel(ctx->int0_mask, ctx->base + MASK_PROTOCOL_INT);
+	writel(ctx->int1_mask, ctx->base + MASK_INTERNAL_INT);
+	writel(1, ctx->base + SOFT_RESET);
+
+	return 0;
+}
+
+static void sprd_dsi_edpi_video(struct dsi_context *ctx)
+{
+	struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
+	const u32 fifo_depth = 1096;
+	const u32 word_length = 4;
+	u32 hactive = ctx->vm.hactive;
+	u32 Bpp_x100;
+	u32 max_fifo_len;
+	u8 coding;
+
+	coding = fmt_to_coding(dsi->slave->format);
+	Bpp_x100 = calc_bytes_per_pixel_x100(coding);
+	max_fifo_len = word_length * fifo_depth * 100 / Bpp_x100;
+
+	writel(0, ctx->base + SOFT_RESET);
+	dsi_reg_wr(ctx, DPI_VIDEO_FORMAT, DPI_VIDEO_MODE_FORMAT, 0, coding);
+	dsi_reg_wr(ctx, CMD_MODE_CFG, TEAR_FX_EN, 0, ctx->te_ack_en);
+
+	if (max_fifo_len > hactive)
+		writel(hactive, ctx->base + DCS_WM_PKT_SIZE);
+	else
+		writel(max_fifo_len, ctx->base + DCS_WM_PKT_SIZE);
+
+	writel(ctx->int0_mask, ctx->base + MASK_PROTOCOL_INT);
+	writel(ctx->int1_mask, ctx->base + MASK_INTERNAL_INT);
+	writel(1, ctx->base + SOFT_RESET);
+}
+
+/*
+ * Send a packet on the generic interface,
+ * this function has an active delay to wait for the buffer to clear.
+ * The delay is limited to:
+ * (param_length / 4) x DSIH_FIFO_ACTIVE_WAIT x register access time
+ * the controller restricts the sending of.
+ *
+ * This function will not be able to send Null and Blanking packets due to
+ * controller restriction
+ */
+static int sprd_dsi_wr_pkt(struct dsi_context *ctx, u8 vc, u8 type,
+			const u8 *param, u16 len)
+{
+	struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
+	u8 wc_lsbyte, wc_msbyte;
+	u32 payload;
+	int i, j, ret;
+
+	if (vc > 3)
+		return -EINVAL;
+
+
+	/* 1st: for long packet, must config payload first */
+	ret = dsi_wait_tx_payload_fifo_empty(ctx);
+	if (ret) {
+		drm_err(dsi->drm, "tx payload fifo is not empty\n");
+		return ret;
+	}
+
+	if (len > 2) {
+		for (i = 0, j = 0; i < len; i += j) {
+			payload = 0;
+			for (j = 0; (j < 4) && ((j + i) < (len)); j++)
+				payload |= param[i + j] << (j * 8);
+
+			writel(payload, ctx->base + GEN_PLD_DATA);
+		}
+		wc_lsbyte = len & 0xff;
+		wc_msbyte = len >> 8;
+	} else {
+		wc_lsbyte = (len > 0) ? param[0] : 0;
+		wc_msbyte = (len > 1) ? param[1] : 0;
+	}
+
+	/* 2nd: then set packet header */
+	ret = dsi_wait_tx_cmd_fifo_empty(ctx);
+	if (ret) {
+		drm_err(dsi->drm, "tx cmd fifo is not empty\n");
+		return ret;
+	}
+
+	writel(type | (vc << 6) | (wc_lsbyte << 8) | (wc_msbyte << 16),
+			ctx->base + GEN_HDR);
+
+	return 0;
+}
+
+/*
+ * Send READ packet to peripheral using the generic interface,
+ * this will force command mode and stop video mode (because of BTA).
+ *
+ * This function has an active delay to wait for the buffer to clear,
+ * the delay is limited to 2 x DSIH_FIFO_ACTIVE_WAIT
+ * (waiting for command buffer, and waiting for receiving)
+ * @note this function will enable BTA
+ */
+static int sprd_dsi_rd_pkt(struct dsi_context *ctx, u8 vc, u8 type,
+			u8 msb_byte, u8 lsb_byte,
+			u8 *buffer, u8 bytes_to_read)
+{
+	struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
+	int i, ret;
+	int count = 0;
+	u32 temp;
+
+	if (vc > 3)
+		return -EINVAL;
+
+	/* 1st: send read command to peripheral */
+	ret = dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_CMD_FIFO_EMPTY, 5);
+	if (!ret)
+		return -EIO;
+
+	writel(type | (vc << 6) | (lsb_byte << 8) | (msb_byte << 16),
+			ctx->base + GEN_HDR);
+
+	/* 2nd: wait peripheral response completed */
+	ret = dsi_wait_rd_resp_completed(ctx);
+	if (ret) {
+		drm_err(dsi->drm, "wait read response time out\n");
+		return ret;
+	}
+
+	/* 3rd: get data from rx payload fifo */
+	ret = dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_RDATA_FIFO_EMPTY, 1);
+	if (ret) {
+		drm_err(dsi->drm, "rx payload fifo empty\n");
+		return -EIO;
+	}
+
+	for (i = 0; i < 100; i++) {
+		temp = readl(ctx->base + GEN_PLD_DATA);
+
+		if (count < bytes_to_read)
+			buffer[count++] = temp & 0xff;
+		if (count < bytes_to_read)
+			buffer[count++] = (temp >> 8) & 0xff;
+		if (count < bytes_to_read)
+			buffer[count++] = (temp >> 16) & 0xff;
+		if (count < bytes_to_read)
+			buffer[count++] = (temp >> 24) & 0xff;
+
+		ret = dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_RDATA_FIFO_EMPTY, 1);
+		if (ret)
+			return count;
+	}
+
+	return 0;
+}
+
+static void sprd_dsi_set_work_mode(struct dsi_context *ctx, u8 mode)
+{
+	if (mode == DSI_MODE_CMD)
+		writel(1, ctx->base + DSI_MODE_CFG);
+	else
+		writel(0, ctx->base + DSI_MODE_CFG);
+}
+
+static void sprd_dsi_lp_cmd_enable(struct dsi_context *ctx)
+{
+	if (readl(ctx->base + DSI_MODE_CFG))
+		dsi_reg_up(ctx, CMD_MODE_CFG, GEN_SW_0P_TX | GEN_SW_1P_TX |
+			GEN_SW_2P_TX | GEN_SR_0P_TX | GEN_SR_1P_TX | GEN_SR_2P_TX |
+			GEN_LW_TX | DCS_SW_0P_TX | DCS_SW_1P_TX | DCS_SR_0P_TX |
+			DCS_LW_TX | MAX_RD_PKT_SIZE, GEN_SW_0P_TX | GEN_SW_1P_TX |
+			GEN_SW_2P_TX | GEN_SR_0P_TX | GEN_SR_1P_TX | GEN_SR_2P_TX |
+			GEN_LW_TX | DCS_SW_0P_TX | DCS_SW_1P_TX | DCS_SR_0P_TX |
+			DCS_LW_TX | MAX_RD_PKT_SIZE);
+	else
+		dsi_reg_up(ctx, VID_MODE_CFG, LP_CMD_EN, LP_CMD_EN);
+}
+
+static void sprd_dsi_state_reset(struct dsi_context *ctx)
+{
+	writel(0, ctx->base + SOFT_RESET);
+	udelay(100);
+	writel(1, ctx->base + SOFT_RESET);
+}
+
+static int sprd_dphy_init(struct dsi_context *ctx)
+{
+	struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
+	int ret;
+
+	dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_RESET_N, 0);
+	dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_SHUTDOWN, 0);
+	dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_CLK_EN, 0);
+
+	dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLR, 0);
+	dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLR, PHY_TESTCLR);
+	dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLR, 0);
+
+	dphy_pll_config(ctx);
+	dphy_timing_config(ctx);
+
+	dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_SHUTDOWN, RF_PHY_SHUTDOWN);
+	dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_RESET_N, RF_PHY_RESET_N);
+	writel(0x1C, ctx->base + PHY_MIN_STOP_TIME);
+	dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_CLK_EN, RF_PHY_CLK_EN);
+	writel(dsi->slave->lanes - 1, ctx->base + PHY_LANE_NUM_CONFIG);
+
+	ret = dphy_wait_pll_locked(ctx);
+	if (ret) {
+		drm_err(dsi->drm, "dphy initial failed\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static void sprd_dphy_fini(struct dsi_context *ctx)
+{
+	dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_RESET_N, 0);
+	dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_SHUTDOWN, 0);
+	dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_RESET_N, RF_PHY_RESET_N);
+}
+
+static void sprd_dsi_encoder_enable(struct drm_encoder *encoder)
+{
+	struct sprd_dsi *dsi = encoder_to_dsi(encoder);
+	struct sprd_dpu *dpu = to_sprd_crtc(encoder->crtc);
+	struct dsi_context *ctx = &dsi->ctx;
+
+	if (ctx->enabled) {
+		drm_warn(dsi->drm, "dsi is initialized\n");
+		return;
+	}
+
+	sprd_dsi_init(ctx);
+	if (ctx->work_mode == DSI_MODE_VIDEO)
+		sprd_dsi_dpi_video(ctx);
+	else
+		sprd_dsi_edpi_video(ctx);
+
+	sprd_dphy_init(ctx);
+
+	sprd_dsi_lp_cmd_enable(ctx);
+
+	if (dsi->panel) {
+		drm_panel_prepare(dsi->panel);
+		drm_panel_enable(dsi->panel);
+	}
+
+	sprd_dsi_set_work_mode(ctx, ctx->work_mode);
+	sprd_dsi_state_reset(ctx);
+
+	if (dsi->slave->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
+		dsi_reg_up(ctx, PHY_CLK_LANE_LP_CTRL, AUTO_CLKLANE_CTRL_EN,
+				AUTO_CLKLANE_CTRL_EN);
+	else {
+		dsi_reg_up(ctx, PHY_CLK_LANE_LP_CTRL, RF_PHY_CLK_EN, RF_PHY_CLK_EN);
+		dsi_reg_up(ctx, PHY_CLK_LANE_LP_CTRL, PHY_CLKLANE_TX_REQ_HS,
+				PHY_CLKLANE_TX_REQ_HS);
+		dphy_wait_pll_locked(ctx);
+	}
+
+	sprd_dpu_run(dpu);
+
+	ctx->enabled = true;
+}
+
+static void sprd_dsi_encoder_disable(struct drm_encoder *encoder)
+{
+	struct sprd_dsi *dsi = encoder_to_dsi(encoder);
+	struct sprd_dpu *dpu = to_sprd_crtc(encoder->crtc);
+	struct dsi_context *ctx = &dsi->ctx;
+
+	if (!ctx->enabled) {
+		drm_warn(dsi->drm, "dsi isn't initialized\n");
+		return;
+	}
+
+	sprd_dpu_stop(dpu);
+	sprd_dsi_set_work_mode(ctx, DSI_MODE_CMD);
+	sprd_dsi_lp_cmd_enable(ctx);
+
+	if (dsi->panel) {
+		drm_panel_disable(dsi->panel);
+		drm_panel_unprepare(dsi->panel);
+	}
+
+	sprd_dphy_fini(ctx);
+	sprd_dsi_fini(ctx);
+
+	ctx->enabled = false;
+}
+
+static void sprd_dsi_encoder_mode_set(struct drm_encoder *encoder,
+				 struct drm_display_mode *mode,
+				 struct drm_display_mode *adj_mode)
+{
+	struct sprd_dsi *dsi = encoder_to_dsi(encoder);
+
+	drm_dbg(dsi->drm, "%s() set mode: %s\n", __func__, dsi->mode->name);
+}
+
+static int sprd_dsi_encoder_atomic_check(struct drm_encoder *encoder,
+				    struct drm_crtc_state *crtc_state,
+				    struct drm_connector_state *conn_state)
+{
+	return 0;
+}
+
+static const struct drm_encoder_helper_funcs sprd_encoder_helper_funcs = {
+	.atomic_check	= sprd_dsi_encoder_atomic_check,
+	.mode_set	= sprd_dsi_encoder_mode_set,
+	.enable		= sprd_dsi_encoder_enable,
+	.disable	= sprd_dsi_encoder_disable
+};
+
+static const struct drm_encoder_funcs sprd_encoder_funcs = {
+	.destroy = drm_encoder_cleanup,
+};
+
+static struct sprd_dsi *sprd_dsi_encoder_init(struct drm_device *drm,
+			       struct device *dev)
+{
+	struct sprd_dsi *dsi;
+	u32 crtc_mask;
+
+	crtc_mask = drm_of_find_possible_crtcs(drm, dev->of_node);
+	if (!crtc_mask) {
+		drm_err(drm, "failed to find crtc mask\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	drm_dbg(drm, "find possible crtcs: 0x%08x\n", crtc_mask);
+
+	dsi = drmm_encoder_alloc(drm, struct sprd_dsi, encoder,
+			       &sprd_encoder_funcs, DRM_MODE_ENCODER_DSI, NULL);
+	if (IS_ERR(dsi)) {
+		drm_err(drm, "failed to init dsi encoder.\n");
+		return dsi;
+	}
+
+	dsi->encoder.possible_crtcs = crtc_mask;
+	drm_encoder_helper_add(&dsi->encoder, &sprd_encoder_helper_funcs);
+
+	return dsi;
+}
+
+static int sprd_dsi_find_panel(struct sprd_dsi *dsi)
+{
+	struct device *dev = dsi->host.dev;
+	struct device_node *child, *lcds_node;
+	struct drm_panel *panel;
+
+	/* search /lcds child node first */
+	lcds_node = of_find_node_by_path("/lcds");
+	for_each_child_of_node(lcds_node, child) {
+		panel = of_drm_find_panel(child);
+		if (!IS_ERR(panel)) {
+			dsi->panel = panel;
+			return 0;
+		}
+	}
+
+	/*
+	 * If /lcds child node search failed, we search
+	 * the child of dsi host node.
+	 */
+	for_each_child_of_node(dev->of_node, child) {
+		panel = of_drm_find_panel(child);
+		if (!IS_ERR(panel)) {
+			dsi->panel = panel;
+			return 0;
+		}
+	}
+
+	drm_err(dsi->drm, "of_drm_find_panel() failed\n");
+	return -ENODEV;
+}
+
+static int sprd_dsi_host_attach(struct mipi_dsi_host *host,
+			   struct mipi_dsi_device *slave)
+{
+	struct sprd_dsi *dsi = host_to_dsi(host);
+	struct dsi_context *ctx = &dsi->ctx;
+	int ret;
+
+	dsi->slave = slave;
+
+	if (slave->mode_flags & MIPI_DSI_MODE_VIDEO)
+		ctx->work_mode = DSI_MODE_VIDEO;
+	else
+		ctx->work_mode = DSI_MODE_CMD;
+
+	if (slave->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
+		ctx->burst_mode = VIDEO_BURST_WITH_SYNC_PULSES;
+	else if (slave->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
+		ctx->burst_mode = VIDEO_NON_BURST_WITH_SYNC_PULSES;
+	else
+		ctx->burst_mode = VIDEO_NON_BURST_WITH_SYNC_EVENTS;
+
+	ret = sprd_dsi_find_panel(dsi);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int sprd_dsi_host_detach(struct mipi_dsi_host *host,
+			   struct mipi_dsi_device *slave)
+{
+	/* do nothing */
+	return 0;
+}
+
+static ssize_t sprd_dsi_host_transfer(struct mipi_dsi_host *host,
+				const struct mipi_dsi_msg *msg)
+{
+	struct sprd_dsi *dsi = host_to_dsi(host);
+	const u8 *tx_buf = msg->tx_buf;
+
+	if (msg->rx_buf && msg->rx_len) {
+		u8 lsb = (msg->tx_len > 0) ? tx_buf[0] : 0;
+		u8 msb = (msg->tx_len > 1) ? tx_buf[1] : 0;
+
+		return sprd_dsi_rd_pkt(&dsi->ctx, msg->channel, msg->type,
+				msb, lsb, msg->rx_buf, msg->rx_len);
+	}
+
+	if (msg->tx_buf && msg->tx_len)
+		return sprd_dsi_wr_pkt(&dsi->ctx, msg->channel, msg->type,
+					tx_buf, msg->tx_len);
+
+	return 0;
+}
+
+static const struct mipi_dsi_host_ops sprd_dsi_host_ops = {
+	.attach = sprd_dsi_host_attach,
+	.detach = sprd_dsi_host_detach,
+	.transfer = sprd_dsi_host_transfer,
+};
+
+static int sprd_dsi_host_init(struct sprd_dsi *dsi, struct device *dev)
+{
+	int ret;
+
+	dsi->host.dev = dev;
+	dsi->host.ops = &sprd_dsi_host_ops;
+
+	ret = mipi_dsi_host_register(&dsi->host);
+	if (ret)
+		drm_err(dsi->drm, "failed to register dsi host\n");
+
+	return ret;
+}
+
+static int sprd_dsi_connector_get_modes(struct drm_connector *connector)
+{
+	struct sprd_dsi *dsi = connector_to_dsi(connector);
+
+	return drm_panel_get_modes(dsi->panel, connector);
+}
+
+static enum drm_mode_status
+sprd_dsi_connector_mode_valid(struct drm_connector *connector,
+			 struct drm_display_mode *mode)
+{
+	struct sprd_dsi *dsi = connector_to_dsi(connector);
+
+	drm_dbg(dsi->drm, "%s() mode: "DRM_MODE_FMT"\n", __func__, DRM_MODE_ARG(mode));
+
+	if (mode->type & DRM_MODE_TYPE_PREFERRED) {
+		dsi->mode = mode;
+		drm_display_mode_to_videomode(dsi->mode, &dsi->ctx.vm);
+	}
+
+	return MODE_OK;
+}
+
+static struct drm_encoder *
+sprd_dsi_connector_best_encoder(struct drm_connector *connector)
+{
+	struct sprd_dsi *dsi = connector_to_dsi(connector);
+
+	return &dsi->encoder;
+}
+
+static struct drm_connector_helper_funcs sprd_dsi_connector_helper_funcs = {
+	.get_modes = sprd_dsi_connector_get_modes,
+	.mode_valid = sprd_dsi_connector_mode_valid,
+	.best_encoder = sprd_dsi_connector_best_encoder,
+};
+
+static enum drm_connector_status
+sprd_dsi_connector_detect(struct drm_connector *connector, bool force)
+{
+	struct sprd_dsi *dsi = connector_to_dsi(connector);
+
+	if (dsi->panel) {
+		drm_panel_add(dsi->panel);
+		return connector_status_connected;
+	}
+
+	return connector_status_disconnected;
+}
+
+static void sprd_dsi_connector_destroy(struct drm_connector *connector)
+{
+	drm_connector_unregister(connector);
+	drm_connector_cleanup(connector);
+}
+
+static const struct drm_connector_funcs sprd_dsi_atomic_connector_funcs = {
+	.fill_modes = drm_helper_probe_single_connector_modes,
+	.detect = sprd_dsi_connector_detect,
+	.destroy = sprd_dsi_connector_destroy,
+	.reset = drm_atomic_helper_connector_reset,
+	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+static int sprd_dsi_connector_init(struct drm_device *drm, struct sprd_dsi *dsi)
+{
+	struct drm_encoder *encoder = &dsi->encoder;
+	struct drm_connector *connector = &dsi->connector;
+	int ret;
+
+	connector->polled = DRM_CONNECTOR_POLL_HPD;
+
+	ret = drm_connector_init(drm, connector,
+				 &sprd_dsi_atomic_connector_funcs,
+				 DRM_MODE_CONNECTOR_DSI);
+	if (ret) {
+		drm_err(drm, "drm_connector_init() failed\n");
+		return ret;
+	}
+
+	drm_connector_helper_add(connector,
+				 &sprd_dsi_connector_helper_funcs);
+
+	drm_connector_attach_encoder(connector, encoder);
+
+	return 0;
+}
+
+static int sprd_dsi_context_init(struct sprd_dsi *dsi,
+			struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct dsi_context *ctx = &dsi->ctx;
+	struct resource *res;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	ctx->base = devm_ioremap(dev, res->start, resource_size(res));
+	if (!ctx->base) {
+		drm_err(dsi->drm, "failed to map dsi host registers\n");
+		return -ENXIO;
+	}
+
+	ctx->pll = devm_kzalloc(dev, sizeof(*ctx->pll), GFP_KERNEL);
+	if (!ctx->pll)
+		return -ENOMEM;
+
+	ctx->regmap = devm_regmap_init(dev, &regmap_tst_io, dsi, &byte_config);
+	if (IS_ERR(ctx->regmap)) {
+		drm_err(dsi->drm, "dphy regmap init failed\n");
+		return PTR_ERR(ctx->regmap);
+	}
+
+	ctx->data_hs2lp = 120;
+	ctx->data_lp2hs = 500;
+	ctx->clk_hs2lp = 4;
+	ctx->clk_lp2hs = 15;
+	ctx->max_rd_time = 6000;
+	ctx->int0_mask = 0xffffffff;
+	ctx->int1_mask = 0xffffffff;
+	ctx->enabled = true;
+
+	return 0;
+}
+
+static int sprd_dsi_bind(struct device *dev, struct device *master, void *data)
+{
+	struct drm_device *drm = data;
+	struct sprd_dsi *dsi;
+	int ret;
+
+	dsi = sprd_dsi_encoder_init(drm, dev);
+	if (IS_ERR(dsi))
+		return PTR_ERR(dsi);
+
+	dsi->drm = drm;
+	dev_set_drvdata(dev, dsi);
+
+	ret = sprd_dsi_connector_init(drm, dsi);
+	if (ret)
+		return ret;
+
+	ret = sprd_dsi_context_init(dsi, dev);
+	if (ret)
+		return ret;
+
+	ret = sprd_dsi_host_init(dsi, dev);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static void sprd_dsi_unbind(struct device *dev,
+			struct device *master, void *data)
+{
+	struct sprd_dsi *dsi = dev_get_drvdata(dev);
+
+	mipi_dsi_host_unregister(&dsi->host);
+}
+
+static const struct component_ops dsi_component_ops = {
+	.bind	= sprd_dsi_bind,
+	.unbind	= sprd_dsi_unbind,
+};
+
+static const struct of_device_id dsi_match_table[] = {
+	{ .compatible = "sprd,sharkl3-dsi-host" },
+	{ /* sentinel */ },
+};
+
+static int sprd_dsi_probe(struct platform_device *pdev)
+{
+	return component_add(&pdev->dev, &dsi_component_ops);
+}
+
+static int sprd_dsi_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &dsi_component_ops);
+
+	return 0;
+}
+
+struct platform_driver sprd_dsi_driver = {
+	.probe = sprd_dsi_probe,
+	.remove = sprd_dsi_remove,
+	.driver = {
+		.name = "sprd-dsi-drv",
+		.of_match_table = dsi_match_table,
+	},
+};
+
+MODULE_AUTHOR("Leon He <leon.he@unisoc.com>");
+MODULE_AUTHOR("Kevin Tang <kevin.tang@unisoc.com>");
+MODULE_DESCRIPTION("Unisoc MIPI DSI HOST Controller Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/sprd/sprd_dsi.h b/drivers/gpu/drm/sprd/sprd_dsi.h
new file mode 100644
index 000000000..16628fb5c
--- /dev/null
+++ b/drivers/gpu/drm/sprd/sprd_dsi.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Unisoc Inc.
+ */
+
+#ifndef __SPRD_DSI_H__
+#define __SPRD_DSI_H__
+
+#include <linux/of.h>
+#include <linux/device.h>
+#include <linux/regmap.h>
+#include <video/videomode.h>
+
+#include <drm/drm_bridge.h>
+#include <drm/drm_connector.h>
+#include <drm/drm_encoder.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_print.h>
+#include <drm/drm_panel.h>
+
+#include "megacores_pll.h"
+
+#define encoder_to_dsi(encoder) \
+	container_of(encoder, struct sprd_dsi, encoder)
+
+enum dsi_work_mode {
+	DSI_MODE_CMD = 0,
+	DSI_MODE_VIDEO
+};
+
+enum video_burst_mode {
+	VIDEO_NON_BURST_WITH_SYNC_PULSES = 0,
+	VIDEO_NON_BURST_WITH_SYNC_EVENTS,
+	VIDEO_BURST_WITH_SYNC_PULSES
+};
+
+enum dsi_color_coding {
+	COLOR_CODE_16BIT_CONFIG1 = 0,
+	COLOR_CODE_16BIT_CONFIG2,
+	COLOR_CODE_16BIT_CONFIG3,
+	COLOR_CODE_18BIT_CONFIG1,
+	COLOR_CODE_18BIT_CONFIG2,
+	COLOR_CODE_24BIT,
+	COLOR_CODE_20BIT_YCC422_LOOSELY,
+	COLOR_CODE_24BIT_YCC422,
+	COLOR_CODE_16BIT_YCC422,
+	COLOR_CODE_30BIT,
+	COLOR_CODE_36BIT,
+	COLOR_CODE_12BIT_YCC420,
+	COLOR_CODE_COMPRESSTION,
+	COLOR_CODE_MAX
+};
+
+struct dsi_context {
+	void __iomem *base;
+	struct regmap *regmap;
+	struct dphy_pll *pll;
+	struct videomode vm;
+	bool enabled;
+
+	u8 work_mode;
+	u8 burst_mode;
+
+	u32 int0_mask;
+	u32 int1_mask;
+
+	/* maximum time (ns) for data lanes from HS to LP */
+	u16 data_hs2lp;
+	/* maximum time (ns) for data lanes from LP to HS */
+	u16 data_lp2hs;
+	/* maximum time (ns) for clk lanes from HS to LP */
+	u16 clk_hs2lp;
+	/* maximum time (ns) for clk lanes from LP to HS */
+	u16 clk_lp2hs;
+	/* maximum time (ns) for BTA operation - REQUIRED */
+	u16 max_rd_time;
+	/* enable receiving frame ack packets - for video mode */
+	bool frame_ack_en;
+	/* enable receiving tear effect ack packets - for cmd mode */
+	bool te_ack_en;
+};
+
+struct sprd_dsi {
+	struct drm_device *drm;
+	struct mipi_dsi_host host;
+	struct mipi_dsi_device *slave;
+	struct drm_encoder encoder;
+	struct drm_connector connector;
+	struct drm_panel *panel;
+	struct drm_display_mode *mode;
+	struct dsi_context ctx;
+};
+
+#endif /* __SPRD_DSI_H__ */
-- 
2.29.0

Re: [PATCH v6 4/6] drm/sprd: add Unisoc's drm display controller driver

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 24850 bytes --]

Hi,

On Fri, Aug 13, 2021 at 10:53:00PM +0800, Kevin Tang wrote:
> Adds DPU(Display Processor Unit) support for the Unisoc's display
> subsystem.
> It's support multi planes, scaler, rotation, PQ(Picture Quality) and more.
> 
> v2:
>   - Use drm_xxx to replace all DRM_XXX.
>   - Use kzalloc to replace devm_kzalloc for sprd_dpu structure init.
> 
> v3:
>   - Remove dpu_layer stuff layer and commit layers by aotmic_update
> 
> v4:
>   - Use drmm_helpers to allocate crtc and planes.
>   - Move rotation enum definitions to crtc layer reg bitfields.
>   - Move allocate crtc and planes to bind function.
> 
> v5:
>   - Fix the checkpatch warnings.
>   - Use mode_set_nofb instead of mode_valid callback.
>   - Follow the OF-Graph bindings, use of_graph_get_port_by_id
>     instead of of_parse_phandle.
>   - Use zpos to represent the layer position.
>   - Rebase to last drm misc branch.
> 
> v6:
>   - Disable and clear interrupts before register dpu IRQ
>   - Init dpi config used by crtc_state->adjusted_mode on mode_set_nofb
>   - Remove enable_irq and disable_irq function call.
>   - Remove drm_format_info function call.
> 
> Cc: Orson Zhai <orsonzhai@gmail.com>
> Cc: Chunyan Zhang <zhang.lyra@gmail.com>
> Signed-off-by: Kevin Tang <kevin.tang@unisoc.com>
> ---
>  drivers/gpu/drm/sprd/Kconfig    |   1 +
>  drivers/gpu/drm/sprd/Makefile   |   3 +-
>  drivers/gpu/drm/sprd/sprd_dpu.c | 937 ++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/sprd/sprd_dpu.h | 109 ++++
>  drivers/gpu/drm/sprd/sprd_drm.c |   1 +
>  drivers/gpu/drm/sprd/sprd_drm.h |   2 +
>  6 files changed, 1052 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/gpu/drm/sprd/sprd_dpu.c
>  create mode 100644 drivers/gpu/drm/sprd/sprd_dpu.h
> 
> diff --git a/drivers/gpu/drm/sprd/Kconfig b/drivers/gpu/drm/sprd/Kconfig
> index 726c3e76d..37762c333 100644
> --- a/drivers/gpu/drm/sprd/Kconfig
> +++ b/drivers/gpu/drm/sprd/Kconfig
> @@ -5,6 +5,7 @@ config DRM_SPRD
>  	select DRM_GEM_CMA_HELPER
>  	select DRM_KMS_CMA_HELPER
>  	select DRM_KMS_HELPER
> +	select VIDEOMODE_HELPERS
>  	help
>  	  Choose this option if you have a Unisoc chipset.
>  	  If M is selected the module will be called sprd_drm.
> diff --git a/drivers/gpu/drm/sprd/Makefile b/drivers/gpu/drm/sprd/Makefile
> index 9850f00b8..ab12b95e6 100644
> --- a/drivers/gpu/drm/sprd/Makefile
> +++ b/drivers/gpu/drm/sprd/Makefile
> @@ -1,3 +1,4 @@
>  # SPDX-License-Identifier: GPL-2.0
>  
> -obj-y := sprd_drm.o
> +obj-y := sprd_drm.o \
> +	sprd_dpu.o
> diff --git a/drivers/gpu/drm/sprd/sprd_dpu.c b/drivers/gpu/drm/sprd/sprd_dpu.c
> new file mode 100644
> index 000000000..448dd4fb6
> --- /dev/null
> +++ b/drivers/gpu/drm/sprd/sprd_dpu.c
> @@ -0,0 +1,937 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020 Unisoc Inc.
> + */
> +
> +#include <linux/component.h>
> +#include <linux/delay.h>
> +#include <linux/dma-buf.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/of_graph.h>
> +#include <linux/of_irq.h>
> +#include <linux/wait.h>
> +#include <linux/workqueue.h>
> +
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_fb_cma_helper.h>
> +#include <drm/drm_gem_cma_helper.h>
> +#include <drm/drm_gem_framebuffer_helper.h>
> +#include <drm/drm_plane_helper.h>
> +
> +#include "sprd_drm.h"
> +#include "sprd_dpu.h"
> +
> +/* Global control registers */
> +#define REG_DPU_CTRL	0x04
> +#define REG_DPU_CFG0	0x08
> +#define REG_PANEL_SIZE	0x20
> +#define REG_BLEND_SIZE	0x24
> +#define REG_BG_COLOR	0x2C
> +
> +/* Layer0 control registers */
> +#define REG_LAY_BASE_ADDR0	0x30
> +#define REG_LAY_BASE_ADDR1	0x34
> +#define REG_LAY_BASE_ADDR2	0x38
> +#define REG_LAY_CTRL		0x40
> +#define REG_LAY_SIZE		0x44
> +#define REG_LAY_PITCH		0x48
> +#define REG_LAY_POS		0x4C
> +#define REG_LAY_ALPHA		0x50
> +#define REG_LAY_CROP_START	0x5C
> +
> +/* Interrupt control registers */
> +#define REG_DPU_INT_EN		0x1E0
> +#define REG_DPU_INT_CLR		0x1E4
> +#define REG_DPU_INT_STS		0x1E8
> +
> +/* DPI control registers */
> +#define REG_DPI_CTRL		0x1F0
> +#define REG_DPI_H_TIMING	0x1F4
> +#define REG_DPI_V_TIMING	0x1F8
> +
> +/* MMU control registers */
> +#define REG_MMU_EN			0x800
> +#define REG_MMU_VPN_RANGE		0x80C
> +#define REG_MMU_VAOR_ADDR_RD		0x818
> +#define REG_MMU_VAOR_ADDR_WR		0x81C
> +#define REG_MMU_INV_ADDR_RD		0x820
> +#define REG_MMU_INV_ADDR_WR		0x824
> +#define REG_MMU_PPN1			0x83C
> +#define REG_MMU_RANGE1			0x840
> +#define REG_MMU_PPN2			0x844
> +#define REG_MMU_RANGE2			0x848
> +
> +/* Global control bits */
> +#define BIT_DPU_RUN			BIT(0)
> +#define BIT_DPU_STOP			BIT(1)
> +#define BIT_DPU_REG_UPDATE		BIT(2)
> +#define BIT_DPU_IF_EDPI			BIT(0)
> +
> +/* Layer control bits */
> +#define BIT_DPU_LAY_EN				BIT(0)
> +#define BIT_DPU_LAY_LAYER_ALPHA			(0x01 << 2)
> +#define BIT_DPU_LAY_COMBO_ALPHA			(0x02 << 2)
> +#define BIT_DPU_LAY_FORMAT_YUV422_2PLANE		(0x00 << 4)
> +#define BIT_DPU_LAY_FORMAT_YUV420_2PLANE		(0x01 << 4)
> +#define BIT_DPU_LAY_FORMAT_YUV420_3PLANE		(0x02 << 4)
> +#define BIT_DPU_LAY_FORMAT_ARGB8888			(0x03 << 4)
> +#define BIT_DPU_LAY_FORMAT_RGB565			(0x04 << 4)
> +#define BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3		(0x00 << 8)
> +#define BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0		(0x01 << 8)
> +#define BIT_DPU_LAY_NO_SWITCH			(0x00 << 10)
> +#define BIT_DPU_LAY_RB_OR_UV_SWITCH		(0x01 << 10)
> +#define BIT_DPU_LAY_MODE_BLEND_NORMAL		(0x00 << 16)
> +#define BIT_DPU_LAY_MODE_BLEND_PREMULT		(0x01 << 16)
> +#define BIT_DPU_LAY_ROTATION_0		(0x00 << 20)
> +#define BIT_DPU_LAY_ROTATION_90		(0x01 << 20)
> +#define BIT_DPU_LAY_ROTATION_180	(0x02 << 20)
> +#define BIT_DPU_LAY_ROTATION_270	(0x03 << 20)
> +#define BIT_DPU_LAY_ROTATION_0_M	(0x04 << 20)
> +#define BIT_DPU_LAY_ROTATION_90_M	(0x05 << 20)
> +#define BIT_DPU_LAY_ROTATION_180_M	(0x06 << 20)
> +#define BIT_DPU_LAY_ROTATION_270_M	(0x07 << 20)
> +
> +/* Interrupt control & status bits */
> +#define BIT_DPU_INT_DONE		BIT(0)
> +#define BIT_DPU_INT_TE			BIT(1)
> +#define BIT_DPU_INT_ERR			BIT(2)
> +#define BIT_DPU_INT_UPDATE_DONE		BIT(4)
> +#define BIT_DPU_INT_VSYNC		BIT(5)
> +#define BIT_DPU_INT_MMU_VAOR_RD		BIT(16)
> +#define BIT_DPU_INT_MMU_VAOR_WR		BIT(17)
> +#define BIT_DPU_INT_MMU_INV_RD		BIT(18)
> +#define BIT_DPU_INT_MMU_INV_WR		BIT(19)
> +
> +/* DPI control bits */
> +#define BIT_DPU_EDPI_TE_EN		BIT(8)
> +#define BIT_DPU_EDPI_FROM_EXTERNAL_PAD	BIT(10)
> +#define BIT_DPU_DPI_HALT_EN		BIT(16)
> +
> +static const u32 layer_fmts[] = {
> +	DRM_FORMAT_XRGB8888,
> +	DRM_FORMAT_XBGR8888,
> +	DRM_FORMAT_ARGB8888,
> +	DRM_FORMAT_ABGR8888,
> +	DRM_FORMAT_RGBA8888,
> +	DRM_FORMAT_BGRA8888,
> +	DRM_FORMAT_RGBX8888,
> +	DRM_FORMAT_RGB565,
> +	DRM_FORMAT_BGR565,
> +	DRM_FORMAT_NV12,
> +	DRM_FORMAT_NV21,
> +	DRM_FORMAT_NV16,
> +	DRM_FORMAT_NV61,
> +	DRM_FORMAT_YUV420,
> +	DRM_FORMAT_YVU420,
> +};
> +
> +struct sprd_plane {
> +	struct drm_plane base;
> +};
> +
> +static u32 check_mmu_isr(struct sprd_dpu *dpu, u32 reg_val)
> +{
> +	struct dpu_context *ctx = &dpu->ctx;
> +	u32 mmu_mask = BIT_DPU_INT_MMU_VAOR_RD |
> +			BIT_DPU_INT_MMU_VAOR_WR |
> +			BIT_DPU_INT_MMU_INV_RD |
> +			BIT_DPU_INT_MMU_INV_WR;
> +	u32 val = reg_val & mmu_mask;
> +	int i;
> +
> +	if (val) {
> +		drm_err(dpu->drm, "--- iommu interrupt err: 0x%04x ---\n", val);
> +
> +		if (val & BIT_DPU_INT_MMU_INV_RD)
> +			drm_err(dpu->drm, "iommu invalid read error, addr: 0x%08x\n",
> +				readl(ctx->base + REG_MMU_INV_ADDR_RD));
> +		if (val & BIT_DPU_INT_MMU_INV_WR)
> +			drm_err(dpu->drm, "iommu invalid write error, addr: 0x%08x\n",
> +				readl(ctx->base + REG_MMU_INV_ADDR_WR));
> +		if (val & BIT_DPU_INT_MMU_VAOR_RD)
> +			drm_err(dpu->drm, "iommu va out of range read error, addr: 0x%08x\n",
> +				readl(ctx->base + REG_MMU_VAOR_ADDR_RD));
> +		if (val & BIT_DPU_INT_MMU_VAOR_WR)
> +			drm_err(dpu->drm, "iommu va out of range write error, addr: 0x%08x\n",
> +				readl(ctx->base + REG_MMU_VAOR_ADDR_WR));
> +
> +		for (i = 0; i < 8; i++) {
> +			reg_val = layer_reg_rd(ctx, REG_LAY_CTRL, i);
> +			if (reg_val & 0x1)
> +				drm_info(dpu->drm, "layer%d: 0x%x 0x%x 0x%x ctrl: 0x%x\n", i,
> +					layer_reg_rd(ctx, REG_LAY_BASE_ADDR0, i),
> +					layer_reg_rd(ctx, REG_LAY_BASE_ADDR1, i),
> +					layer_reg_rd(ctx, REG_LAY_BASE_ADDR2, i),
> +					layer_reg_rd(ctx, REG_LAY_CTRL, i));
> +		}
> +	}
> +
> +	return val;
> +}

We'll still want an Acked-by from one of the IOMMU maintainers. Last
time they commented they were against that.

> +static int dpu_wait_stop_done(struct sprd_dpu *dpu)
> +{
> +	struct dpu_context *ctx = &dpu->ctx;
> +	int rc;
> +
> +	if (ctx->stopped)
> +		return 0;
> +
> +	rc = wait_event_interruptible_timeout(ctx->wait_queue, ctx->evt_stop,
> +					       msecs_to_jiffies(500));
> +	ctx->evt_stop = false;
> +
> +	ctx->stopped = true;
> +
> +	if (!rc) {
> +		drm_err(dpu->drm, "dpu wait for stop done time out!\n");
> +		return -ETIMEDOUT;
> +	}
> +
> +	return 0;
> +}
> +
> +static int dpu_wait_update_done(struct sprd_dpu *dpu)
> +{
> +	struct dpu_context *ctx = &dpu->ctx;
> +	int rc;
> +
> +	ctx->evt_update = false;
> +
> +	rc = wait_event_interruptible_timeout(ctx->wait_queue, ctx->evt_update,
> +					       msecs_to_jiffies(500));
> +
> +	if (!rc) {
> +		drm_err(dpu->drm, "dpu wait for reg update done time out!\n");
> +		return -ETIMEDOUT;
> +	}
> +
> +	return 0;
> +}
> +
> +static u32 drm_format_to_dpu(struct drm_framebuffer *fb)
> +{
> +	u32 format = 0;
> +
> +	switch (fb->format->format) {
> +	case DRM_FORMAT_BGRA8888:
> +		/* BGRA8888 -> ARGB8888 */
> +		format |= BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0;
> +		format |= BIT_DPU_LAY_FORMAT_ARGB8888;
> +		break;
> +	case DRM_FORMAT_RGBX8888:
> +	case DRM_FORMAT_RGBA8888:
> +		/* RGBA8888 -> ABGR8888 */
> +		format |= BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0;
> +		fallthrough;
> +	case DRM_FORMAT_ABGR8888:
> +		/* RB switch */
> +		format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
> +		fallthrough;
> +	case DRM_FORMAT_ARGB8888:
> +		format |= BIT_DPU_LAY_FORMAT_ARGB8888;
> +		break;
> +	case DRM_FORMAT_XBGR8888:
> +		/* RB switch */
> +		format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
> +		fallthrough;
> +	case DRM_FORMAT_XRGB8888:
> +		format |= BIT_DPU_LAY_FORMAT_ARGB8888;
> +		break;
> +	case DRM_FORMAT_BGR565:
> +		/* RB switch */
> +		format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
> +		fallthrough;
> +	case DRM_FORMAT_RGB565:
> +		format |= BIT_DPU_LAY_FORMAT_RGB565;
> +		break;
> +	case DRM_FORMAT_NV12:
> +		/* 2-Lane: Yuv420 */
> +		format |= BIT_DPU_LAY_FORMAT_YUV420_2PLANE;
> +		/* Y endian */
> +		format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
> +		/* UV endian */
> +		format |= BIT_DPU_LAY_NO_SWITCH;
> +		break;
> +	case DRM_FORMAT_NV21:
> +		/* 2-Lane: Yuv420 */
> +		format |= BIT_DPU_LAY_FORMAT_YUV420_2PLANE;
> +		/* Y endian */
> +		format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
> +		/* UV endian */
> +		format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
> +		break;
> +	case DRM_FORMAT_NV16:
> +		/* 2-Lane: Yuv422 */
> +		format |= BIT_DPU_LAY_FORMAT_YUV422_2PLANE;
> +		/* Y endian */
> +		format |= BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0;
> +		/* UV endian */
> +		format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
> +		break;
> +	case DRM_FORMAT_NV61:
> +		/* 2-Lane: Yuv422 */
> +		format |= BIT_DPU_LAY_FORMAT_YUV422_2PLANE;
> +		/* Y endian */
> +		format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
> +		/* UV endian */
> +		format |= BIT_DPU_LAY_NO_SWITCH;
> +		break;
> +	case DRM_FORMAT_YUV420:
> +		format |= BIT_DPU_LAY_FORMAT_YUV420_3PLANE;
> +		/* Y endian */
> +		format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
> +		/* UV endian */
> +		format |= BIT_DPU_LAY_NO_SWITCH;
> +		break;
> +	case DRM_FORMAT_YVU420:
> +		format |= BIT_DPU_LAY_FORMAT_YUV420_3PLANE;
> +		/* Y endian */
> +		format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
> +		/* UV endian */
> +		format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
> +		break;
> +	default:
> +		break;
> +	}
> +
> +	return format;
> +}
> +
> +static u32 drm_rotation_to_dpu(struct drm_plane_state *state)
> +{
> +	u32 rotation = 0;
> +
> +	switch (state->rotation) {
> +	default:
> +	case DRM_MODE_ROTATE_0:
> +		rotation = BIT_DPU_LAY_ROTATION_0;
> +		break;
> +	case DRM_MODE_ROTATE_90:
> +		rotation = BIT_DPU_LAY_ROTATION_90;
> +		break;
> +	case DRM_MODE_ROTATE_180:
> +		rotation = BIT_DPU_LAY_ROTATION_180;
> +		break;
> +	case DRM_MODE_ROTATE_270:
> +		rotation = BIT_DPU_LAY_ROTATION_270;
> +		break;
> +	case DRM_MODE_REFLECT_Y:
> +		rotation = BIT_DPU_LAY_ROTATION_180_M;
> +		break;
> +	case (DRM_MODE_REFLECT_Y | DRM_MODE_ROTATE_90):
> +		rotation = BIT_DPU_LAY_ROTATION_90_M;
> +		break;
> +	case DRM_MODE_REFLECT_X:
> +		rotation = BIT_DPU_LAY_ROTATION_0_M;
> +		break;
> +	case (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90):
> +		rotation = BIT_DPU_LAY_ROTATION_270_M;
> +		break;
> +	}
> +
> +	return rotation;
> +}
> +
> +static u32 drm_blend_to_dpu(struct drm_plane_state *state)
> +{
> +	u32 blend = 0;
> +
> +	switch (state->pixel_blend_mode) {
> +	case DRM_MODE_BLEND_COVERAGE:
> +		/* alpha mode select - combo alpha */
> +		blend |= BIT_DPU_LAY_COMBO_ALPHA;
> +		/* Normal mode */
> +		blend |= BIT_DPU_LAY_MODE_BLEND_NORMAL;
> +		break;
> +	case DRM_MODE_BLEND_PREMULTI:
> +		/* alpha mode select - combo alpha */
> +		blend |= BIT_DPU_LAY_COMBO_ALPHA;
> +		/* Pre-mult mode */
> +		blend |= BIT_DPU_LAY_MODE_BLEND_PREMULT;
> +		break;
> +	case DRM_MODE_BLEND_PIXEL_NONE:
> +	default:
> +		/* don't do blending, maybe RGBX */
> +		/* alpha mode select - layer alpha */
> +		blend |= BIT_DPU_LAY_LAYER_ALPHA;
> +		break;
> +	}
> +
> +	return blend;
> +}
> +
> +static void sprd_dpu_layer(struct sprd_dpu *dpu, struct drm_plane_state *state)
> +{
> +	struct dpu_context *ctx = &dpu->ctx;
> +	struct drm_gem_cma_object *cma_obj;
> +	struct drm_framebuffer *fb = state->fb;
> +	u32 addr, size, offset, pitch, blend, format, rotation;
> +	u32 src_x = state->src_x >> 16;
> +	u32 src_y = state->src_y >> 16;
> +	u32 src_w = state->src_w >> 16;
> +	u32 src_h = state->src_h >> 16;
> +	u32 dst_x = state->crtc_x;
> +	u32 dst_y = state->crtc_y;
> +	u32 alpha = state->alpha;
> +	u32 index = state->zpos;
> +	int i;
> +
> +	offset = (dst_x & 0xffff) | (dst_y << 16);
> +	size = (src_w & 0xffff) | (src_h << 16);
> +
> +	for (i = 0; i < fb->format->num_planes; i++) {
> +		cma_obj = drm_fb_cma_get_gem_obj(fb, i);
> +		addr = cma_obj->paddr + fb->offsets[i];
> +
> +		if (i == 0)
> +			layer_reg_wr(ctx, REG_LAY_BASE_ADDR0, addr, index);
> +		else if (i == 1)
> +			layer_reg_wr(ctx, REG_LAY_BASE_ADDR1, addr, index);
> +		else
> +			layer_reg_wr(ctx, REG_LAY_BASE_ADDR2, addr, index);
> +	}
> +
> +	if (fb->format->num_planes == 3) {
> +		/* UV pitch is 1/2 of Y pitch */
> +		pitch = (fb->pitches[0] / fb->format->cpp[0]) |
> +				(fb->pitches[0] / fb->format->cpp[0] << 15);
> +	} else {
> +		pitch = fb->pitches[0] / fb->format->cpp[0];
> +	}
> +
> +	layer_reg_wr(ctx, REG_LAY_POS, offset, index);
> +	layer_reg_wr(ctx, REG_LAY_SIZE, size, index);
> +	layer_reg_wr(ctx, REG_LAY_CROP_START,
> +			src_y << 16 | src_x, index);
> +	layer_reg_wr(ctx, REG_LAY_ALPHA, alpha, index);
> +	layer_reg_wr(ctx, REG_LAY_PITCH, pitch, index);
> +
> +	format = drm_format_to_dpu(fb);
> +	blend = drm_blend_to_dpu(state);
> +	rotation = drm_rotation_to_dpu(state);
> +
> +	layer_reg_wr(ctx, REG_LAY_CTRL, BIT_DPU_LAY_EN |
> +				format |
> +				blend |
> +				rotation,
> +				index);
> +}
> +
> +static void sprd_dpu_flip(struct sprd_dpu *dpu)
> +{
> +	struct dpu_context *ctx = &dpu->ctx;
> +	u32 reg_val;
> +
> +	/*
> +	 * Make sure the dpu is in stop status. DPU has no shadow
> +	 * registers in EDPI mode. So the config registers can only be
> +	 * updated in the rising edge of DPU_RUN bit.
> +	 */
> +	if (ctx->if_type == SPRD_DPU_IF_EDPI)
> +		dpu_wait_stop_done(dpu);
> +
> +	/* update trigger and wait */
> +	if (ctx->if_type == SPRD_DPU_IF_DPI) {
> +		if (!ctx->stopped) {
> +			dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_REG_UPDATE);
> +			dpu_wait_update_done(dpu);
> +		}
> +
> +		dpu_reg_set(ctx, REG_DPU_INT_EN, BIT_DPU_INT_ERR);
> +	} else if (ctx->if_type == SPRD_DPU_IF_EDPI) {
> +		dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_RUN);
> +
> +		ctx->stopped = false;
> +	}
> +
> +	/*
> +	 * If the following interrupt was disabled in isr,
> +	 * re-enable it.
> +	 */
> +	reg_val = BIT_DPU_INT_MMU_VAOR_RD |
> +		  BIT_DPU_INT_MMU_VAOR_WR |
> +		  BIT_DPU_INT_MMU_INV_RD |
> +		  BIT_DPU_INT_MMU_INV_WR;
> +	dpu_reg_set(ctx, REG_DPU_INT_EN, reg_val);
> +}
> +
> +static void sprd_dpu_init(struct sprd_dpu *dpu)
> +{
> +	struct dpu_context *ctx = &dpu->ctx;
> +	u32 int_mask = 0;
> +
> +	writel(0x00, ctx->base + REG_BG_COLOR);
> +	writel(0x00, ctx->base + REG_MMU_EN);
> +	writel(0x00, ctx->base + REG_MMU_PPN1);
> +	writel(0xffff, ctx->base + REG_MMU_RANGE1);
> +	writel(0x00, ctx->base + REG_MMU_PPN2);
> +	writel(0xffff, ctx->base + REG_MMU_RANGE2);
> +	writel(0x1ffff, ctx->base + REG_MMU_VPN_RANGE);
> +
> +	if (ctx->if_type == SPRD_DPU_IF_DPI) {
> +		/* use dpi as interface */
> +		dpu_reg_clr(ctx, REG_DPU_CFG0, BIT_DPU_IF_EDPI);
> +		/* disable Halt function for SPRD DSI */
> +		dpu_reg_clr(ctx, REG_DPI_CTRL, BIT_DPU_DPI_HALT_EN);
> +		/* select te from external pad */
> +		dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_EDPI_FROM_EXTERNAL_PAD);
> +
> +		/* enable dpu update done INT */
> +		int_mask |= BIT_DPU_INT_UPDATE_DONE;
> +		/* enable dpu done INT */
> +		int_mask |= BIT_DPU_INT_DONE;
> +		/* enable dpu dpi vsync */
> +		int_mask |= BIT_DPU_INT_VSYNC;
> +		/* enable dpu TE INT */
> +		int_mask |= BIT_DPU_INT_TE;
> +		/* enable underflow err INT */
> +		int_mask |= BIT_DPU_INT_ERR;
> +	} else if (ctx->if_type == SPRD_DPU_IF_EDPI) {
> +		/* use edpi as interface */
> +		dpu_reg_set(ctx, REG_DPU_CFG0, BIT_DPU_IF_EDPI);
> +		/* use external te */
> +		dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_EDPI_FROM_EXTERNAL_PAD);
> +		/* enable te */
> +		dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_EDPI_TE_EN);
> +
> +		/* enable stop done INT */
> +		int_mask |= BIT_DPU_INT_DONE;
> +		/* enable TE INT */
> +		int_mask |= BIT_DPU_INT_TE;
> +	}
> +
> +	/* enable iommu va out of range read error INT */
> +	int_mask |= BIT_DPU_INT_MMU_VAOR_RD;
> +	/* enable iommu va out of range write error INT */
> +	int_mask |= BIT_DPU_INT_MMU_VAOR_WR;
> +	/* enable iommu invalid read error INT */
> +	int_mask |= BIT_DPU_INT_MMU_INV_RD;
> +	/* enable iommu invalid write error INT */
> +	int_mask |= BIT_DPU_INT_MMU_INV_WR;
> +
> +	writel(int_mask, ctx->base + REG_DPU_INT_EN);
> +}
> +
> +static void sprd_dpu_fini(struct sprd_dpu *dpu)
> +{
> +	struct dpu_context *ctx = &dpu->ctx;
> +
> +	writel(0x00, ctx->base + REG_DPU_INT_EN);
> +	writel(0xff, ctx->base + REG_DPU_INT_CLR);
> +}
> +
> +static void sprd_dpi_init(struct sprd_dpu *dpu)
> +{
> +	struct dpu_context *ctx = &dpu->ctx;
> +	u32 reg_val;
> +	u32 size;
> +
> +	size = (ctx->vm.vactive << 16) | ctx->vm.hactive;
> +	writel(size, ctx->base + REG_PANEL_SIZE);
> +	writel(size, ctx->base + REG_BLEND_SIZE);
> +
> +	if (ctx->if_type == SPRD_DPU_IF_DPI) {
> +		/* set dpi timing */
> +		reg_val = ctx->vm.hsync_len << 0 |
> +			  ctx->vm.hback_porch << 8 |
> +			  ctx->vm.hfront_porch << 20;
> +		writel(reg_val, ctx->base + REG_DPI_H_TIMING);
> +
> +		reg_val = ctx->vm.vsync_len << 0 |
> +			  ctx->vm.vback_porch << 8 |
> +			  ctx->vm.vfront_porch << 20;
> +		writel(reg_val, ctx->base + REG_DPI_V_TIMING);
> +	}
> +}
> +
> +void sprd_dpu_run(struct sprd_dpu *dpu)
> +{
> +	struct dpu_context *ctx = &dpu->ctx;
> +
> +	dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_RUN);
> +
> +	ctx->stopped = false;
> +}
> +
> +void sprd_dpu_stop(struct sprd_dpu *dpu)
> +{
> +	struct dpu_context *ctx = &dpu->ctx;
> +
> +	if (ctx->if_type == SPRD_DPU_IF_DPI)
> +		dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_STOP);
> +
> +	dpu_wait_stop_done(dpu);
> +}
> +
> +static int sprd_plane_atomic_check(struct drm_plane *plane,
> +				  struct drm_atomic_state *state)
> +{
> +	struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state,
> +									     plane);
> +	struct drm_crtc_state *crtc_state;
> +	u32 fmt;
> +
> +	if (!plane_state->fb || !plane_state->crtc)
> +		return 0;
> +
> +	fmt = drm_format_to_dpu(plane_state->fb);
> +	if (!fmt)
> +		return -EINVAL;
> +
> +	crtc_state = drm_atomic_get_crtc_state(plane_state->state, plane_state->crtc);
> +	if (IS_ERR(crtc_state))
> +		return PTR_ERR(crtc_state);
> +
> +	return drm_atomic_helper_check_plane_state(plane_state, crtc_state,
> +						  DRM_PLANE_HELPER_NO_SCALING,
> +						  DRM_PLANE_HELPER_NO_SCALING,
> +						  true, true);
> +}
> +
> +static void sprd_plane_atomic_update(struct drm_plane *drm_plane,
> +				    struct drm_atomic_state *state)
> +{
> +	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
> +									   drm_plane);
> +	struct sprd_dpu *dpu = to_sprd_crtc(new_state->crtc);
> +
> +	/* start configure dpu layers */
> +	sprd_dpu_layer(dpu, new_state);
> +}
> +
> +static void sprd_plane_atomic_disable(struct drm_plane *drm_plane,
> +				     struct drm_atomic_state *state)
> +{
> +	struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
> +									   drm_plane);
> +	struct sprd_dpu *dpu = to_sprd_crtc(old_state->crtc);
> +
> +	layer_reg_wr(&dpu->ctx, REG_LAY_CTRL, 0x00, old_state->zpos);
> +}
> +
> +static void sprd_plane_create_properties(struct sprd_plane *plane, int index)
> +{
> +	unsigned int supported_modes = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
> +				       BIT(DRM_MODE_BLEND_PREMULTI) |
> +				       BIT(DRM_MODE_BLEND_COVERAGE);
> +
> +	/* create rotation property */
> +	drm_plane_create_rotation_property(&plane->base,
> +					   DRM_MODE_ROTATE_0,
> +					   DRM_MODE_ROTATE_MASK |
> +					   DRM_MODE_REFLECT_MASK);
> +
> +	/* create alpha property */
> +	drm_plane_create_alpha_property(&plane->base);
> +
> +	/* create blend mode property */
> +	drm_plane_create_blend_mode_property(&plane->base, supported_modes);
> +
> +	/* create zpos property */
> +	drm_plane_create_zpos_immutable_property(&plane->base, index);
> +}
> +
> +static const struct drm_plane_helper_funcs sprd_plane_helper_funcs = {
> +	.atomic_check = sprd_plane_atomic_check,
> +	.atomic_update = sprd_plane_atomic_update,
> +	.atomic_disable = sprd_plane_atomic_disable,
> +};
> +
> +static const struct drm_plane_funcs sprd_plane_funcs = {
> +	.update_plane = drm_atomic_helper_update_plane,
> +	.disable_plane	= drm_atomic_helper_disable_plane,
> +	.destroy = drm_plane_cleanup,
> +	.reset = drm_atomic_helper_plane_reset,
> +	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
> +	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
> +};
> +
> +static struct sprd_plane *sprd_planes_init(struct drm_device *drm)
> +{
> +	struct sprd_plane *plane, *primary;
> +	enum drm_plane_type plane_type;
> +	int i;
> +
> +	for (i = 0; i < 6; i++) {
> +		plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY :
> +					DRM_PLANE_TYPE_OVERLAY;
> +
> +		plane = drmm_universal_plane_alloc(drm, struct sprd_plane, base,
> +					       1, &sprd_plane_funcs,
> +					       layer_fmts, ARRAY_SIZE(layer_fmts),
> +					       NULL, plane_type, NULL);
> +		if (IS_ERR(plane)) {
> +			drm_err(drm, "failed to init drm plane: %d\n", i);
> +			return plane;
> +		}
> +
> +		drm_plane_helper_add(&plane->base, &sprd_plane_helper_funcs);
> +
> +		sprd_plane_create_properties(plane, i);
> +
> +		if (i == 0)
> +			primary = plane;
> +	}
> +
> +	return primary;
> +}
> +
> +static void sprd_crtc_mode_set_nofb(struct drm_crtc *crtc)
> +{
> +	struct sprd_dpu *dpu = to_sprd_crtc(crtc);
> +	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
> +
> +	drm_display_mode_to_videomode(mode, &dpu->ctx.vm);

You don't need to store the videomode into you dpu structure, just pass
adjusted_mode to sprd_dpi_init.

> +	sprd_dpi_init(dpu);
> +}
> +
> +static void sprd_crtc_atomic_enable(struct drm_crtc *crtc,
> +				   struct drm_atomic_state *state)
> +{
> +	struct sprd_dpu *dpu = to_sprd_crtc(crtc);
> +
> +	sprd_dpu_init(dpu);

Do you need to do it on both mode_set_nofb and atomic_enable?

Maxime

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH v6 6/6] drm/sprd: add Unisoc's drm mipi dsi&dphy driver

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 56006 bytes --]

On Fri, Aug 13, 2021 at 10:53:02PM +0800, Kevin Tang wrote:
> Adds dsi host controller support for the Unisoc's display subsystem.
> Adds dsi phy support for the Unisoc's display subsystem.
> Only MIPI DSI Displays supported, DP/TV/HMDI will be support
> in the feature.
> 
> v1:
>   - Remove dphy and dsi graph binding, merge the dphy driver into the dsi.
> 
> v2:
>   - Use drm_xxx to replace all DRM_XXX.
>   - Use kzalloc to replace devm_kzalloc for sprd_dsi structure init.
> 
> v4:
>   - Use drmm_helpers to allocate encoder.
>   - Move allocate encoder and connector to bind function.
> 
> v5:
>   - Drop the dsi ip file prefix.
>   - Fix the checkpatch warnings.
>   - Add Signed-off-by for dsi&dphy patch.
>   - Use the mode_flags of mipi_dsi_device to setup crtc DPI and EDPI mode.
> 
> v6:
>   - Redesign the way to access the dsi register.
>   - Reduce the dsi_context member variables.
> ---
>  drivers/gpu/drm/sprd/Kconfig         |    1 +
>  drivers/gpu/drm/sprd/Makefile        |    4 +-
>  drivers/gpu/drm/sprd/megacores_pll.c |  317 +++++++
>  drivers/gpu/drm/sprd/megacores_pll.h |  146 +++
>  drivers/gpu/drm/sprd/sprd_dpu.c      |   17 +
>  drivers/gpu/drm/sprd/sprd_drm.c      |    1 +
>  drivers/gpu/drm/sprd/sprd_drm.h      |    1 +
>  drivers/gpu/drm/sprd/sprd_dsi.c      | 1260 ++++++++++++++++++++++++++
>  drivers/gpu/drm/sprd/sprd_dsi.h      |   94 ++
>  9 files changed, 1840 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/gpu/drm/sprd/megacores_pll.c
>  create mode 100644 drivers/gpu/drm/sprd/megacores_pll.h
>  create mode 100644 drivers/gpu/drm/sprd/sprd_dsi.c
>  create mode 100644 drivers/gpu/drm/sprd/sprd_dsi.h
> 
> diff --git a/drivers/gpu/drm/sprd/Kconfig b/drivers/gpu/drm/sprd/Kconfig
> index 37762c333..3edeaeca0 100644
> --- a/drivers/gpu/drm/sprd/Kconfig
> +++ b/drivers/gpu/drm/sprd/Kconfig
> @@ -5,6 +5,7 @@ config DRM_SPRD
>  	select DRM_GEM_CMA_HELPER
>  	select DRM_KMS_CMA_HELPER
>  	select DRM_KMS_HELPER
> +	select DRM_MIPI_DSI
>  	select VIDEOMODE_HELPERS
>  	help
>  	  Choose this option if you have a Unisoc chipset.
> diff --git a/drivers/gpu/drm/sprd/Makefile b/drivers/gpu/drm/sprd/Makefile
> index ab12b95e6..73f96c459 100644
> --- a/drivers/gpu/drm/sprd/Makefile
> +++ b/drivers/gpu/drm/sprd/Makefile
> @@ -1,4 +1,6 @@
>  # SPDX-License-Identifier: GPL-2.0
>  
>  obj-y := sprd_drm.o \
> -	sprd_dpu.o
> +	sprd_dpu.o \
> +	sprd_dsi.o \
> +	megacores_pll.o
> diff --git a/drivers/gpu/drm/sprd/megacores_pll.c b/drivers/gpu/drm/sprd/megacores_pll.c
> new file mode 100644
> index 000000000..0dfd3c372
> --- /dev/null
> +++ b/drivers/gpu/drm/sprd/megacores_pll.c
> @@ -0,0 +1,317 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020 Unisoc Inc.
> + */
> +
> +#include <asm/div64.h>
> +#include <linux/delay.h>
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/regmap.h>
> +#include <linux/string.h>
> +
> +#include "megacores_pll.h"
> +
> +#define L						0
> +#define H						1
> +#define CLK						0
> +#define DATA					1
> +#define INFINITY				0xffffffff
> +#define MIN_OUTPUT_FREQ			(100)
> +
> +#define AVERAGE(a, b) (min(a, b) + abs((b) - (a)) / 2)
> +
> +/* sharkle */
> +#define VCO_BAND_LOW	750
> +#define VCO_BAND_MID	1100
> +#define VCO_BAND_HIGH	1500
> +#define PHY_REF_CLK	26000
> +
> +static int dphy_calc_pll_param(struct dphy_pll *pll)
> +{
> +	const u32 khz = 1000;
> +	const u32 mhz = 1000000;
> +	const unsigned long long factor = 100;
> +	unsigned long long tmp;
> +	int i;
> +
> +	pll->potential_fvco = pll->freq / khz;
> +	pll->ref_clk = PHY_REF_CLK / khz;
> +
> +	for (i = 0; i < 4; ++i) {
> +		if (pll->potential_fvco >= VCO_BAND_LOW &&
> +			pll->potential_fvco <= VCO_BAND_HIGH) {
> +			pll->fvco = pll->potential_fvco;
> +			pll->out_sel = BIT(i);
> +			break;
> +		}
> +		pll->potential_fvco <<= 1;
> +	}
> +	if (pll->fvco == 0)
> +		return -EINVAL;
> +
> +	if (pll->fvco >= VCO_BAND_LOW && pll->fvco <= VCO_BAND_MID) {
> +		/* vco band control */
> +		pll->vco_band = 0x0;
> +		/* low pass filter control */
> +		pll->lpf_sel = 1;
> +	} else if (pll->fvco > VCO_BAND_MID && pll->fvco <= VCO_BAND_HIGH) {
> +		pll->vco_band = 0x1;
> +		pll->lpf_sel = 0;
> +	} else
> +		return -EINVAL;

This doesn't follow the kernel coding style, make sure all the issues
with checkpatch.pl --strict are fixed.

> +
> +	pll->nint = pll->fvco / pll->ref_clk;
> +	tmp = pll->fvco * factor * mhz;
> +	do_div(tmp, pll->ref_clk);
> +	tmp = tmp - pll->nint * factor * mhz;
> +	tmp *= BIT(20);
> +	do_div(tmp, 100000000);
> +	pll->kint = (u32)tmp;
> +	pll->refin = 3; /* pre-divider bypass */
> +	pll->sdm_en = true; /* use fraction N PLL */
> +	pll->fdk_s = 0x1; /* fraction */
> +	pll->cp_s = 0x0;
> +	pll->det_delay = 0x1;
> +
> +	return 0;
> +}
> +
> +static void dphy_set_pll_reg(struct dphy_pll *pll, struct regmap *regmap)
> +{
> +	struct pll_reg *reg = &pll->reg;
> +	u8 *val;
> +	int i;
> +
> +	u8 reg_addr[] = {
> +		0x03, 0x04, 0x06, 0x08, 0x09,
> +		0x0a, 0x0b, 0x0e, 0x0f
> +	};
> +
> +	reg->_03.bits.prbs_bist = 1;
> +	reg->_03.bits.en_lp_treot = true;
> +	reg->_03.bits.lpf_sel = pll->lpf_sel;
> +	reg->_03.bits.txfifo_bypass = 0;
> +	reg->_04.bits.div = pll->div;
> +	reg->_04.bits.masterof8lane = 1;
> +	reg->_04.bits.cp_s = pll->cp_s;
> +	reg->_04.bits.fdk_s = pll->fdk_s;
> +	reg->_06.bits.nint = pll->nint;
> +	reg->_08.bits.vco_band = pll->vco_band;
> +	reg->_08.bits.sdm_en = pll->sdm_en;
> +	reg->_08.bits.refin = pll->refin;
> +	reg->_09.bits.kint_h = pll->kint >> 12;
> +	reg->_0a.bits.kint_m = (pll->kint >> 4) & 0xff;
> +	reg->_0b.bits.out_sel = pll->out_sel;
> +	reg->_0b.bits.kint_l = pll->kint & 0xf;
> +	reg->_0e.bits.pll_pu_byp = 0;
> +	reg->_0e.bits.pll_pu = 0;
> +	reg->_0e.bits.stopstate_sel = 1;
> +	reg->_0f.bits.det_delay = pll->det_delay;
> +
> +	val = (u8 *)&reg;
> +
> +	for (i = 0; i < sizeof(reg_addr); ++i) {
> +		regmap_write(regmap, reg_addr[i], val[i]);
> +		DRM_DEBUG("%02x: %02x\n", reg_addr[i], val[i]);
> +	}
> +}

It would be great to also convert this part to a pattern without
structures.

> +
> +int dphy_pll_config(struct dsi_context *ctx)
> +{
> +	struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
> +	struct regmap *regmap = ctx->regmap;
> +	struct dphy_pll *pll = ctx->pll;
> +	int ret;
> +
> +	pll->freq = dsi->slave->hs_rate;
> +
> +	/* FREQ = 26M * (NINT + KINT / 2^20) / out_sel */
> +	ret = dphy_calc_pll_param(pll);
> +	if (ret) {
> +		drm_err(dsi->drm, "failed to calculate dphy pll parameters\n");
> +		return ret;
> +	}
> +	dphy_set_pll_reg(pll, regmap);
> +
> +	return 0;
> +}
> +
> +static void dphy_set_timing_reg(struct regmap *regmap, int type, u8 val[])
> +{
> +	switch (type) {
> +	case REQUEST_TIME:
> +		regmap_write(regmap, 0x31, val[CLK]);
> +		regmap_write(regmap, 0x41, val[DATA]);
> +		regmap_write(regmap, 0x51, val[DATA]);
> +		regmap_write(regmap, 0x61, val[DATA]);
> +		regmap_write(regmap, 0x71, val[DATA]);
> +
> +		regmap_write(regmap, 0x90, val[CLK]);
> +		regmap_write(regmap, 0xa0, val[DATA]);
> +		regmap_write(regmap, 0xb0, val[DATA]);
> +		regmap_write(regmap, 0xc0, val[DATA]);
> +		regmap_write(regmap, 0xd0, val[DATA]);
> +		break;

defines and macros would help the readability here

> +	case PREPARE_TIME:
> +		regmap_write(regmap, 0x32, val[CLK]);
> +		regmap_write(regmap, 0x42, val[DATA]);
> +		regmap_write(regmap, 0x52, val[DATA]);
> +		regmap_write(regmap, 0x62, val[DATA]);
> +		regmap_write(regmap, 0x72, val[DATA]);
> +
> +		regmap_write(regmap, 0x91, val[CLK]);
> +		regmap_write(regmap, 0xa1, val[DATA]);
> +		regmap_write(regmap, 0xb1, val[DATA]);
> +		regmap_write(regmap, 0xc1, val[DATA]);
> +		regmap_write(regmap, 0xd1, val[DATA]);
> +		break;
> +	case ZERO_TIME:
> +		regmap_write(regmap, 0x33, val[CLK]);
> +		regmap_write(regmap, 0x43, val[DATA]);
> +		regmap_write(regmap, 0x53, val[DATA]);
> +		regmap_write(regmap, 0x63, val[DATA]);
> +		regmap_write(regmap, 0x73, val[DATA]);
> +
> +		regmap_write(regmap, 0x92, val[CLK]);
> +		regmap_write(regmap, 0xa2, val[DATA]);
> +		regmap_write(regmap, 0xb2, val[DATA]);
> +		regmap_write(regmap, 0xc2, val[DATA]);
> +		regmap_write(regmap, 0xd2, val[DATA]);
> +		break;
> +	case TRAIL_TIME:
> +		regmap_write(regmap, 0x34, val[CLK]);
> +		regmap_write(regmap, 0x44, val[DATA]);
> +		regmap_write(regmap, 0x54, val[DATA]);
> +		regmap_write(regmap, 0x64, val[DATA]);
> +		regmap_write(regmap, 0x74, val[DATA]);
> +
> +		regmap_write(regmap, 0x93, val[CLK]);
> +		regmap_write(regmap, 0xa3, val[DATA]);
> +		regmap_write(regmap, 0xb3, val[DATA]);
> +		regmap_write(regmap, 0xc3, val[DATA]);
> +		regmap_write(regmap, 0xd3, val[DATA]);
> +		break;
> +	case EXIT_TIME:
> +		regmap_write(regmap, 0x36, val[CLK]);
> +		regmap_write(regmap, 0x46, val[DATA]);
> +		regmap_write(regmap, 0x56, val[DATA]);
> +		regmap_write(regmap, 0x66, val[DATA]);
> +		regmap_write(regmap, 0x76, val[DATA]);
> +
> +		regmap_write(regmap, 0x95, val[CLK]);
> +		regmap_write(regmap, 0xA5, val[DATA]);
> +		regmap_write(regmap, 0xB5, val[DATA]);
> +		regmap_write(regmap, 0xc5, val[DATA]);
> +		regmap_write(regmap, 0xd5, val[DATA]);
> +		break;
> +	case CLKPOST_TIME:
> +		regmap_write(regmap, 0x35, val[CLK]);
> +		regmap_write(regmap, 0x94, val[CLK]);
> +		break;
> +
> +	/* the following just use default value */
> +	case SETTLE_TIME:
> +	case TA_GET:
> +	case TA_GO:
> +	case TA_SURE:
> +		break;

you need to use fallthrough; for all those cases

> +	default:
> +		break;
> +	}
> +}
> +
> +void dphy_timing_config(struct dsi_context *ctx)
> +{
> +	struct regmap *regmap = ctx->regmap;
> +	struct dphy_pll *pll = ctx->pll;
> +	const u32 factor = 2;
> +	const u32 scale = 100;
> +	u32 t_ui, t_byteck, t_half_byteck;
> +	u32 range[2], constant;
> +	u8 val[2];
> +	u32 tmp = 0;
> +
> +	/* t_ui: 1 ui, byteck: 8 ui, half byteck: 4 ui */
> +	t_ui = 1000 * scale / (pll->freq / 1000);
> +	t_byteck = t_ui << 3;
> +	t_half_byteck = t_ui << 2;
> +	constant = t_ui << 1;
> +
> +	/* REQUEST_TIME: HS T-LPX: LP-01
> +	 * For T-LPX, mipi spec defined min value is 50ns,
> +	 * but maybe it shouldn't be too small, because BTA,
> +	 * LP-10, LP-00, LP-01, all of this is related to T-LPX.
> +	 */
> +	range[L] = 50 * scale;
> +	range[H] = INFINITY;
> +	val[CLK] = DIV_ROUND_UP(range[L] * (factor << 1), t_byteck) - 2;
> +	val[DATA] = val[CLK];
> +	dphy_set_timing_reg(regmap, REQUEST_TIME, val);
> +
> +	/* PREPARE_TIME: HS sequence: LP-00 */
> +	range[L] = 38 * scale;
> +	range[H] = 95 * scale;
> +	tmp = AVERAGE(range[L], range[H]);
> +	val[CLK] = DIV_ROUND_UP(AVERAGE(range[L], range[H]),
> +			t_half_byteck) - 1;
> +	range[L] = 40 * scale + 4 * t_ui;
> +	range[H] = 85 * scale + 6 * t_ui;
> +	tmp |= AVERAGE(range[L], range[H]) << 16;
> +	val[DATA] = DIV_ROUND_UP(AVERAGE(range[L], range[H]),
> +			t_half_byteck) - 1;
> +	dphy_set_timing_reg(regmap, PREPARE_TIME, val);
> +
> +	/* ZERO_TIME: HS-ZERO */
> +	range[L] = 300 * scale;
> +	range[H] = INFINITY;
> +	val[CLK] = DIV_ROUND_UP(range[L] * factor + (tmp & 0xffff)
> +			- 525 * t_byteck / 100, t_byteck) - 2;
> +	range[L] = 145 * scale + 10 * t_ui;
> +	val[DATA] = DIV_ROUND_UP(range[L] * factor
> +			+ ((tmp >> 16) & 0xffff) - 525 * t_byteck / 100,
> +			t_byteck) - 2;
> +	dphy_set_timing_reg(regmap, ZERO_TIME, val);
> +
> +	/* TRAIL_TIME: HS-TRAIL */
> +	range[L] = 60 * scale;
> +	range[H] = INFINITY;
> +	val[CLK] = DIV_ROUND_UP(range[L] * factor - constant, t_half_byteck);
> +	range[L] = max(8 * t_ui, 60 * scale + 4 * t_ui);
> +	val[DATA] = DIV_ROUND_UP(range[L] * 3 / 2 - constant, t_half_byteck) - 2;
> +	dphy_set_timing_reg(regmap, TRAIL_TIME, val);
> +
> +	/* EXIT_TIME: */
> +	range[L] = 100 * scale;
> +	range[H] = INFINITY;
> +	val[CLK] = DIV_ROUND_UP(range[L] * factor, t_byteck) - 2;
> +	val[DATA] = val[CLK];
> +	dphy_set_timing_reg(regmap, EXIT_TIME, val);
> +
> +	/* CLKPOST_TIME: */
> +	range[L] = 60 * scale + 52 * t_ui;
> +	range[H] = INFINITY;
> +	val[CLK] = DIV_ROUND_UP(range[L] * factor, t_byteck) - 2;
> +	val[DATA] = val[CLK];
> +	dphy_set_timing_reg(regmap, CLKPOST_TIME, val);
> +
> +	/* SETTLE_TIME:
> +	 * This time is used for receiver. So for transmitter,
> +	 * it can be ignored.
> +	 */
> +
> +	/* TA_GO:
> +	 * transmitter drives bridge state(LP-00) before releasing control,
> +	 * reg 0x1f default value: 0x04, which is good.
> +	 */
> +
> +	/* TA_SURE:
> +	 * After LP-10 state and before bridge state(LP-00),
> +	 * reg 0x20 default value: 0x01, which is good.
> +	 */
> +
> +	/* TA_GET:
> +	 * receiver drives Bridge state(LP-00) before releasing control
> +	 * reg 0x21 default value: 0x03, which is good.
> +	 */
> +}
> diff --git a/drivers/gpu/drm/sprd/megacores_pll.h b/drivers/gpu/drm/sprd/megacores_pll.h
> new file mode 100644
> index 000000000..bf20aae65
> --- /dev/null
> +++ b/drivers/gpu/drm/sprd/megacores_pll.h
> @@ -0,0 +1,146 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2020 Unisoc Inc.
> + */
> +
> +#ifndef _MEGACORES_PLL_H_
> +#define _MEGACORES_PLL_H_
> +
> +#include "sprd_dsi.h"
> +
> +enum PLL_TIMING {
> +	NONE,
> +	REQUEST_TIME,
> +	PREPARE_TIME,
> +	SETTLE_TIME,
> +	ZERO_TIME,
> +	TRAIL_TIME,
> +	EXIT_TIME,
> +	CLKPOST_TIME,
> +	TA_GET,
> +	TA_GO,
> +	TA_SURE,
> +	TA_WAIT,
> +};
> +
> +struct pll_reg {
> +	union __reg_03__ {
> +		struct __03 {
> +			u8 prbs_bist: 1;
> +			u8 en_lp_treot: 1;
> +			u8 lpf_sel: 4;
> +			u8 txfifo_bypass: 1;
> +			u8 freq_hopping: 1;
> +		} bits;
> +		u8 val;
> +	} _03;
> +	union __reg_04__ {
> +		struct __04 {
> +			u8 div: 3;
> +			u8 masterof8lane: 1;
> +			u8 hop_trig: 1;
> +			u8 cp_s: 2;
> +			u8 fdk_s: 1;
> +		} bits;
> +		u8 val;
> +	} _04;
> +	union __reg_06__ {
> +		struct __06 {
> +			u8 nint: 7;
> +			u8 mod_en: 1;
> +		} bits;
> +		u8 val;
> +	} _06;
> +	union __reg_07__ {
> +		struct __07 {
> +			u8 kdelta_h: 8;
> +		} bits;
> +		u8 val;
> +	} _07;
> +	union __reg_08__ {
> +		struct __08 {
> +			u8 vco_band: 1;
> +			u8 sdm_en: 1;
> +			u8 refin: 2;
> +			u8 kdelta_l: 4;
> +		} bits;
> +		u8 val;
> +	} _08;
> +	union __reg_09__ {
> +		struct __09 {
> +			u8 kint_h: 8;
> +		} bits;
> +		u8 val;
> +	} _09;
> +	union __reg_0a__ {
> +		struct __0a {
> +			u8 kint_m: 8;
> +		} bits;
> +		u8 val;
> +	} _0a;
> +	union __reg_0b__ {
> +		struct __0b {
> +			u8 out_sel: 4;
> +			u8 kint_l: 4;
> +		} bits;
> +		u8 val;
> +	} _0b;
> +	union __reg_0c__ {
> +		struct __0c {
> +			u8 kstep_h: 8;
> +		} bits;
> +		u8 val;
> +	} _0c;
> +	union __reg_0d__ {
> +		struct __0d {
> +			u8 kstep_m: 8;
> +		} bits;
> +		u8 val;
> +	} _0d;
> +	union __reg_0e__ {
> +		struct __0e {
> +			u8 pll_pu_byp: 1;
> +			u8 pll_pu: 1;
> +			u8 hsbist_len: 2;
> +			u8 stopstate_sel: 1;
> +			u8 kstep_l: 3;
> +		} bits;
> +		u8 val;
> +	} _0e;
> +	union __reg_0f__ {
> +		struct __0f {
> +			u8 det_delay:2;
> +			u8 kdelta: 4;
> +			u8 ldo0p4:2;
> +		} bits;
> +		u8 val;
> +	} _0f;
> +};
> +
> +struct dphy_pll {
> +	u8 refin; /* Pre-divider control signal */
> +	u8 cp_s; /* 00: SDM_EN=1, 10: SDM_EN=0 */
> +	u8 fdk_s; /* PLL mode control: integer or fraction */
> +	u8 sdm_en;
> +	u8 div;
> +	u8 int_n; /* integer N PLL */
> +	u32 ref_clk; /* dphy reference clock, unit: MHz */
> +	u32 freq; /* panel config, unit: KHz */
> +	u32 fvco;
> +	u32 potential_fvco;
> +	u32 nint; /* sigma delta modulator NINT control */
> +	u32 kint; /* sigma delta modulator KINT control */
> +	u8 lpf_sel; /* low pass filter control */
> +	u8 out_sel; /* post divider control */
> +	u8 vco_band; /* vco range */
> +	u8 det_delay;
> +
> +	struct pll_reg reg;
> +};
> +
> +struct dsi_context;
> +
> +int dphy_pll_config(struct dsi_context *ctx);
> +void dphy_timing_config(struct dsi_context *ctx);
> +
> +#endif /* _MEGACORES_PLL_H_ */
> diff --git a/drivers/gpu/drm/sprd/sprd_dpu.c b/drivers/gpu/drm/sprd/sprd_dpu.c
> index 448dd4fb6..4e3b30abe 100644
> --- a/drivers/gpu/drm/sprd/sprd_dpu.c
> +++ b/drivers/gpu/drm/sprd/sprd_dpu.c
> @@ -25,6 +25,7 @@
>  
>  #include "sprd_drm.h"
>  #include "sprd_dpu.h"
> +#include "sprd_dsi.h"
>  
>  /* Global control registers */
>  #define REG_DPU_CTRL	0x04
> @@ -686,9 +687,25 @@ static void sprd_crtc_mode_set_nofb(struct drm_crtc *crtc)
>  {
>  	struct sprd_dpu *dpu = to_sprd_crtc(crtc);
>  	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
> +	struct drm_encoder *encoder;
> +	struct mipi_dsi_device *slave;
> +	struct sprd_dsi *dsi;
>  
>  	drm_display_mode_to_videomode(mode, &dpu->ctx.vm);
>  
> +	drm_for_each_encoder(encoder, crtc->dev) {
> +		if (encoder->crtc != crtc)
> +			continue;
> +
> +		dsi = encoder_to_dsi(encoder);
> +		slave = dsi->slave;
> +
> +		if (slave->mode_flags & MIPI_DSI_MODE_VIDEO)
> +			dpu->ctx.if_type = SPRD_DPU_IF_DPI;
> +		else
> +			dpu->ctx.if_type = SPRD_DPU_IF_EDPI;
> +	}
> +

You're not using if_type anywhere

>  	sprd_dpi_init(dpu);
>  }
>  
> diff --git a/drivers/gpu/drm/sprd/sprd_drm.c b/drivers/gpu/drm/sprd/sprd_drm.c
> index 549b71278..68cf0933c 100644
> --- a/drivers/gpu/drm/sprd/sprd_drm.c
> +++ b/drivers/gpu/drm/sprd/sprd_drm.c
> @@ -183,6 +183,7 @@ static struct platform_driver sprd_drm_driver = {
>  static struct platform_driver *sprd_drm_drivers[]  = {
>  	&sprd_drm_driver,
>  	&sprd_dpu_driver,
> +	&sprd_dsi_driver,
>  };
>  
>  static int __init sprd_drm_init(void)
> diff --git a/drivers/gpu/drm/sprd/sprd_drm.h b/drivers/gpu/drm/sprd/sprd_drm.h
> index 85d4a8b9f..95d1b972f 100644
> --- a/drivers/gpu/drm/sprd/sprd_drm.h
> +++ b/drivers/gpu/drm/sprd/sprd_drm.h
> @@ -14,5 +14,6 @@ struct sprd_drm {
>  };
>  
>  extern struct platform_driver sprd_dpu_driver;
> +extern struct platform_driver sprd_dsi_driver;
>  
>  #endif /* _SPRD_DRM_H_ */
> diff --git a/drivers/gpu/drm/sprd/sprd_dsi.c b/drivers/gpu/drm/sprd/sprd_dsi.c
> new file mode 100644
> index 000000000..5ce98fe90
> --- /dev/null
> +++ b/drivers/gpu/drm/sprd/sprd_dsi.c
> @@ -0,0 +1,1260 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020 Unisoc Inc.
> + */
> +
> +#include <linux/component.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_graph.h>
> +#include <video/mipi_display.h>
> +
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_of.h>
> +#include <drm/drm_probe_helper.h>
> +
> +#include "sprd_drm.h"
> +#include "sprd_dpu.h"
> +#include "sprd_dsi.h"
> +
> +#define SOFT_RESET 0x04
> +#define MASK_PROTOCOL_INT 0x0C
> +#define MASK_INTERNAL_INT 0x14
> +#define DSI_MODE_CFG 0x18
> +
> +#define VIRTUAL_CHANNEL_ID 0x1C
> +#define GEN_RX_VCID GENMASK(1, 0)
> +#define VIDEO_PKT_VCID GENMASK(3, 2)
> +
> +#define DPI_VIDEO_FORMAT 0x20
> +#define DPI_VIDEO_MODE_FORMAT GENMASK(5, 0)
> +#define LOOSELY18_EN BIT(6)
> +
> +#define VIDEO_PKT_CONFIG 0x24
> +#define VIDEO_PKT_SIZE GENMASK(15, 0)
> +#define VIDEO_LINE_CHUNK_NUM GENMASK(31, 16)
> +
> +#define VIDEO_LINE_HBLK_TIME 0x28
> +#define VIDEO_LINE_HBP_TIME GENMASK(15, 0)
> +#define VIDEO_LINE_HSA_TIME GENMASK(31, 16)
> +
> +#define VIDEO_LINE_TIME 0x2C
> +
> +#define VIDEO_VBLK_LINES 0x30
> +#define VFP_LINES GENMASK(9, 0)
> +#define VBP_LINES GENMASK(19, 10)
> +#define VSA_LINES GENMASK(29, 20)
> +
> +#define VIDEO_VACTIVE_LINES 0x34
> +
> +#define VID_MODE_CFG 0x38
> +#define VID_MODE_TYPE GENMASK(1, 0)
> +#define LP_VSA_EN BIT(8)
> +#define LP_VBP_EN BIT(9)
> +#define LP_VFP_EN BIT(10)
> +#define LP_VACT_EN BIT(11)
> +#define LP_HBP_EN BIT(12)
> +#define LP_HFP_EN BIT(13)
> +#define FRAME_BTA_ACK_EN BIT(14)
> +#define LP_CMD_EN BIT(15)
> +
> +#define TIMEOUT_CNT_CLK_CONFIG 0x40
> +#define HTX_TO_CONFIG 0x44
> +#define LRX_H_TO_CONFIG 0x48
> +
> +#define TX_ESC_CLK_CONFIG 0x5C
> +
> +#define CMD_MODE_CFG 0x68
> +#define TEAR_FX_EN BIT(0)
> +#define ACK_RQST_EN BIT(1)
> +#define PPS_TX BIT(5)
> +#define EXQ_TX BIT(6)
> +#define CMC_TX BIT(7)
> +#define GEN_SW_0P_TX BIT(8)
> +#define GEN_SW_1P_TX BIT(9)
> +#define GEN_SW_2P_TX BIT(10)
> +#define GEN_SR_0P_TX BIT(11)
> +#define GEN_SR_1P_TX BIT(12)
> +#define GEN_SR_2P_TX BIT(13)
> +#define GEN_LW_TX BIT(14)
> +#define DCS_SW_0P_TX BIT(16)
> +#define DCS_SW_1P_TX BIT(17)
> +#define DCS_SR_0P_TX BIT(18)
> +#define DCS_LW_TX BIT(19)
> +#define MAX_RD_PKT_SIZE BIT(24)
> +
> +#define GEN_HDR 0x6C
> +#define GEN_DT GENMASK(5, 0)
> +#define GEN_VC GENMASK(7, 6)
> +#define GEN_WC_LSBYTE GENMASK(15, 8)
> +#define GEN_WC_MSBYTE GENMASK(23, 16)
> +
> +#define GEN_PLD_DATA 0x70
> +#define GEN_PLD_B1 GENMASK(7, 0)
> +#define GEN_PLD_B2 GENMASK(15, 8)
> +#define GEN_PLD_B3 GENMASK(23, 16)
> +#define GEN_PLD_B4 GENMASK(31, 24)
> +
> +#define PHY_CLK_LANE_LP_CTRL 0x74
> +#define PHY_CLKLANE_TX_REQ_HS BIT(0)
> +#define AUTO_CLKLANE_CTRL_EN BIT(1)
> +
> +#define PHY_INTERFACE_CTRL 0x78
> +#define RF_PHY_SHUTDOWN BIT(0)
> +#define RF_PHY_RESET_N BIT(1)
> +#define RF_PHY_CLK_EN BIT(2)
> +
> +#define CMD_MODE_STATUS 0x98
> +#define GEN_CMD_RDCMD_ONGOING BIT(0)
> +#define GEN_CMD_RDATA_FIFO_EMPTY BIT(1)
> +#define GEN_CMD_RDATA_FIFO_FULL BIT(2)
> +#define GEN_CMD_WDATA_FIFO_EMPTY BIT(3)
> +#define GEN_CMD_WDATA_FIFO_FULL BIT(4)
> +#define GEN_CMD_CMD_FIFO_EMPTY BIT(5)
> +#define GEN_CMD_CMD_FIFO_FULL BIT(6)
> +#define GEN_CMD_RDCMD_DONE BIT(7)
> +
> +#define PHY_STATUS 0x9C
> +#define PHY_LOCK BIT(1)
> +
> +#define PHY_MIN_STOP_TIME 0xA0
> +#define PHY_LANE_NUM_CONFIG 0xA4
> +
> +#define PHY_CLKLANE_TIME_CONFIG 0xA8
> +#define PHY_CLKLANE_LP_TO_HS_TIME GENMASK(15, 0)
> +#define PHY_CLKLANE_HS_TO_LP_TIME GENMASK(31, 16)
> +
> +#define PHY_DATALANE_TIME_CONFIG 0xAC
> +#define PHY_DATALANE_LP_TO_HS_TIME GENMASK(15, 0)
> +#define PHY_DATALANE_HS_TO_LP_TIME GENMASK(31, 16)
> +
> +#define MAX_READ_TIME 0xB0
> +
> +#define RX_PKT_CHECK_CONFIG 0xB4
> +#define RX_PKT_ECC_EN BIT(0)
> +#define RX_PKT_CRC_EN BIT(1)
> +
> +#define TA_EN 0xB8
> +
> +#define EOTP_EN 0xBC
> +#define TX_EOTP_EN BIT(0)
> +#define RX_EOTP_EN BIT(1)
> +
> +#define VIDEO_NULLPKT_SIZE 0xC0
> +#define DCS_WM_PKT_SIZE 0xC4
> +#define PROTOCOL_INT_CLR 0xC8
> +#define INTERNAL_INT_CLR 0xCC
> +
> +#define VIDEO_SIG_DELAY_CONFIG 0xD0
> +#define VIDEO_SIG_DELAY GENMASK(23, 0)
> +#define VIDEO_SIG_DELAY_MODE BIT(24)
> +
> +#define PHY_TST_CTRL0 0xF0
> +#define PHY_TESTCLR BIT(0)
> +#define PHY_TESTCLK BIT(1)
> +
> +#define PHY_TST_CTRL1 0xF4
> +#define PHY_TESTDIN GENMASK(7, 0)
> +#define PHY_TESTDOUT GENMASK(15, 8)
> +#define PHY_TESTEN BIT(16)
> +
> +#define host_to_dsi(host) \
> +	container_of(host, struct sprd_dsi, host)
> +#define connector_to_dsi(connector) \
> +	container_of(connector, struct sprd_dsi, connector)
> +
> +static inline u32
> +dsi_reg_rd(struct dsi_context *ctx, u32 offset, u32 mask,
> +			u32 shift)
> +{
> +	return (readl(ctx->base + offset) & mask) >> shift;
> +}
> +
> +static inline void
> +dsi_reg_wr(struct dsi_context *ctx, u32 offset, u32 mask,
> +			u32 shift, u32 val)
> +{
> +	u32 ret;
> +
> +	ret = readl(ctx->base + offset);
> +	ret &= ~mask;
> +	ret |= (val << shift) & mask;
> +	writel(ret, ctx->base + offset);
> +}
> +
> +static inline void
> +dsi_reg_up(struct dsi_context *ctx, u32 offset, u32 mask,
> +			u32 val)
> +{
> +	u32 ret = readl(ctx->base + offset);
> +
> +	writel((ret & ~mask) | (val & mask), ctx->base + offset);
> +}
> +
> +static int regmap_tst_io_write(void *context, u32 reg, u32 val)
> +{
> +	struct sprd_dsi *dsi = context;
> +	struct dsi_context *ctx = &dsi->ctx;
> +
> +	if (val > 0xff || reg > 0xff)
> +		return -EINVAL;
> +
> +	drm_dbg(dsi->drm, "reg = 0x%02x, val = 0x%02x\n", reg, val);
> +
> +	dsi_reg_up(ctx, PHY_TST_CTRL1, PHY_TESTEN, PHY_TESTEN);
> +	dsi_reg_wr(ctx, PHY_TST_CTRL1, PHY_TESTDIN, 0, reg);
> +	dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, PHY_TESTCLK);
> +	dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, 0);
> +	dsi_reg_up(ctx, PHY_TST_CTRL1, PHY_TESTEN, 0);
> +	dsi_reg_wr(ctx, PHY_TST_CTRL1, PHY_TESTDIN, 0, val);
> +	dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, PHY_TESTCLK);
> +	dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, 0);
> +
> +	return 0;
> +}
> +
> +static int regmap_tst_io_read(void *context, u32 reg, u32 *val)
> +{
> +	struct sprd_dsi *dsi = context;
> +	struct dsi_context *ctx = &dsi->ctx;
> +	int ret;
> +
> +	if (reg > 0xff)
> +		return -EINVAL;
> +
> +	dsi_reg_up(ctx, PHY_TST_CTRL1, PHY_TESTEN, PHY_TESTEN);
> +	dsi_reg_wr(ctx, PHY_TST_CTRL1, PHY_TESTDIN, 0, reg);
> +	dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, PHY_TESTCLK);
> +	dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, 0);
> +	dsi_reg_up(ctx, PHY_TST_CTRL1, PHY_TESTEN, 0);
> +
> +	udelay(1);
> +
> +	ret = dsi_reg_rd(ctx, PHY_TST_CTRL1, PHY_TESTDOUT, 8);
> +	if (ret < 0)
> +		return ret;
> +
> +	*val = ret;
> +
> +	drm_dbg(dsi->drm, "reg = 0x%02x, val = 0x%02x\n", reg, *val);
> +	return 0;
> +}
> +
> +static struct regmap_bus regmap_tst_io = {
> +	.reg_write = regmap_tst_io_write,
> +	.reg_read = regmap_tst_io_read,
> +};
> +
> +static const struct regmap_config byte_config = {
> +	.reg_bits = 8,
> +	.val_bits = 8,
> +};
> +
> +static int dphy_wait_pll_locked(struct dsi_context *ctx)
> +{
> +	struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
> +	int i;
> +
> +	for (i = 0; i < 50000; i++) {
> +		if (dsi_reg_rd(ctx, PHY_STATUS, PHY_LOCK, 1))
> +			return 0;
> +		udelay(3);
> +	}
> +
> +	drm_err(dsi->drm, "dphy pll can not be locked\n");
> +	return -ETIMEDOUT;
> +}
> +
> +static int dsi_wait_tx_payload_fifo_empty(struct dsi_context *ctx)
> +{
> +	int i;
> +
> +	for (i = 0; i < 5000; i++) {
> +		if (dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_WDATA_FIFO_EMPTY, 3))
> +			return 0;
> +		udelay(1);
> +	}
> +
> +	return -ETIMEDOUT;
> +}
> +
> +static int dsi_wait_tx_cmd_fifo_empty(struct dsi_context *ctx)
> +{
> +	int i;
> +
> +	for (i = 0; i < 5000; i++) {
> +		if (dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_CMD_FIFO_EMPTY, 5))
> +			return 0;
> +		udelay(1);
> +	}
> +
> +	return -ETIMEDOUT;
> +}
> +
> +static int dsi_wait_rd_resp_completed(struct dsi_context *ctx)
> +{
> +	int i;
> +
> +	for (i = 0; i < 10000; i++) {
> +		if (dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_RDCMD_DONE, 7))
> +			return 0;
> +		udelay(10);
> +	}
> +
> +	return -ETIMEDOUT;
> +}
> +
> +static u16 calc_bytes_per_pixel_x100(int coding)
> +{
> +	u16 Bpp_x100;
> +
> +	switch (coding) {
> +	case COLOR_CODE_16BIT_CONFIG1:
> +	case COLOR_CODE_16BIT_CONFIG2:
> +	case COLOR_CODE_16BIT_CONFIG3:
> +		Bpp_x100 = 200;
> +		break;
> +	case COLOR_CODE_18BIT_CONFIG1:
> +	case COLOR_CODE_18BIT_CONFIG2:
> +		Bpp_x100 = 225;
> +		break;
> +	case COLOR_CODE_24BIT:
> +		Bpp_x100 = 300;
> +		break;
> +	case COLOR_CODE_COMPRESSTION:
> +		Bpp_x100 = 100;
> +		break;
> +	case COLOR_CODE_20BIT_YCC422_LOOSELY:
> +		Bpp_x100 = 250;
> +		break;
> +	case COLOR_CODE_24BIT_YCC422:
> +		Bpp_x100 = 300;
> +		break;
> +	case COLOR_CODE_16BIT_YCC422:
> +		Bpp_x100 = 200;
> +		break;
> +	case COLOR_CODE_30BIT:
> +		Bpp_x100 = 375;
> +		break;
> +	case COLOR_CODE_36BIT:
> +		Bpp_x100 = 450;
> +		break;
> +	case COLOR_CODE_12BIT_YCC420:
> +		Bpp_x100 = 150;
> +		break;
> +	default:
> +		DRM_ERROR("invalid color coding");
> +		Bpp_x100 = 0;
> +		break;
> +	}
> +
> +	return Bpp_x100;
> +}
> +
> +static u8 calc_video_size_step(int coding)
> +{
> +	u8 video_size_step;
> +
> +	switch (coding) {
> +	case COLOR_CODE_16BIT_CONFIG1:
> +	case COLOR_CODE_16BIT_CONFIG2:
> +	case COLOR_CODE_16BIT_CONFIG3:
> +	case COLOR_CODE_18BIT_CONFIG1:
> +	case COLOR_CODE_18BIT_CONFIG2:
> +	case COLOR_CODE_24BIT:
> +	case COLOR_CODE_COMPRESSTION:
> +		return video_size_step = 1;
> +	case COLOR_CODE_20BIT_YCC422_LOOSELY:
> +	case COLOR_CODE_24BIT_YCC422:
> +	case COLOR_CODE_16BIT_YCC422:
> +	case COLOR_CODE_30BIT:
> +	case COLOR_CODE_36BIT:
> +	case COLOR_CODE_12BIT_YCC420:
> +		return video_size_step = 2;
> +	default:
> +		DRM_ERROR("invalid color coding");
> +		return 0;
> +	}
> +}
> +
> +static u16 round_video_size(int coding, u16 video_size)
> +{
> +	switch (coding) {
> +	case COLOR_CODE_16BIT_YCC422:
> +	case COLOR_CODE_24BIT_YCC422:
> +	case COLOR_CODE_20BIT_YCC422_LOOSELY:
> +	case COLOR_CODE_12BIT_YCC420:
> +		/* round up active H pixels to a multiple of 2 */
> +		if ((video_size % 2) != 0)
> +			video_size += 1;
> +		break;
> +	default:
> +		break;
> +	}
> +
> +	return video_size;
> +}
> +
> +#define SPRD_MIPI_DSI_FMT_DSC 0xff
> +static u32 fmt_to_coding(u32 fmt)
> +{
> +	switch (fmt) {
> +	case MIPI_DSI_FMT_RGB565:
> +		return COLOR_CODE_16BIT_CONFIG1;
> +	case MIPI_DSI_FMT_RGB666:
> +	case MIPI_DSI_FMT_RGB666_PACKED:
> +		return COLOR_CODE_18BIT_CONFIG1;
> +	case MIPI_DSI_FMT_RGB888:
> +		return COLOR_CODE_24BIT;
> +	case SPRD_MIPI_DSI_FMT_DSC:
> +		return COLOR_CODE_COMPRESSTION;
> +	default:
> +		DRM_ERROR("Unsupported format (%d)\n", fmt);
> +		return COLOR_CODE_24BIT;
> +	}
> +}
> +
> +#define ns_to_cycle(ns, byte_clk) \
> +	DIV_ROUND_UP((ns) * (byte_clk), 1000000)
> +
> +static void sprd_dsi_init(struct dsi_context *ctx)
> +{
> +	struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
> +	u32 byte_clk = dsi->slave->hs_rate / 8;
> +	u16 data_hs2lp, data_lp2hs, clk_hs2lp, clk_lp2hs;
> +	u16 max_rd_time;
> +	int div;
> +
> +	writel(0, ctx->base + SOFT_RESET);
> +	writel(0xffffffff, ctx->base + MASK_PROTOCOL_INT);
> +	writel(0xffffffff, ctx->base + MASK_INTERNAL_INT);
> +	writel(1, ctx->base + DSI_MODE_CFG);
> +	dsi_reg_up(ctx, EOTP_EN, RX_EOTP_EN, 0);
> +	dsi_reg_up(ctx, EOTP_EN, TX_EOTP_EN, 0);
> +	dsi_reg_up(ctx, RX_PKT_CHECK_CONFIG, RX_PKT_ECC_EN, RX_PKT_ECC_EN);
> +	dsi_reg_up(ctx, RX_PKT_CHECK_CONFIG, RX_PKT_CRC_EN, RX_PKT_CRC_EN);
> +	writel(1, ctx->base + TA_EN);
> +	dsi_reg_up(ctx, VIRTUAL_CHANNEL_ID, VIDEO_PKT_VCID, 0);
> +	dsi_reg_up(ctx, VIRTUAL_CHANNEL_ID, GEN_RX_VCID, 0);
> +
> +	div = DIV_ROUND_UP(byte_clk, dsi->slave->lp_rate);
> +	writel(div, ctx->base + TX_ESC_CLK_CONFIG);
> +
> +	max_rd_time = ns_to_cycle(ctx->max_rd_time, byte_clk);
> +	writel(max_rd_time, ctx->base + MAX_READ_TIME);
> +
> +	data_hs2lp = ns_to_cycle(ctx->data_hs2lp, byte_clk);
> +	data_lp2hs = ns_to_cycle(ctx->data_lp2hs, byte_clk);
> +	clk_hs2lp = ns_to_cycle(ctx->clk_hs2lp, byte_clk);
> +	clk_lp2hs = ns_to_cycle(ctx->clk_lp2hs, byte_clk);
> +	dsi_reg_wr(ctx, PHY_DATALANE_TIME_CONFIG,
> +		PHY_DATALANE_HS_TO_LP_TIME, 16, data_hs2lp);
> +	dsi_reg_wr(ctx, PHY_DATALANE_TIME_CONFIG,
> +		PHY_DATALANE_LP_TO_HS_TIME, 0, data_lp2hs);
> +	dsi_reg_wr(ctx, PHY_CLKLANE_TIME_CONFIG,
> +		PHY_CLKLANE_HS_TO_LP_TIME, 16, clk_hs2lp);
> +	dsi_reg_wr(ctx, PHY_CLKLANE_TIME_CONFIG,
> +		PHY_CLKLANE_LP_TO_HS_TIME, 0, clk_lp2hs);
> +
> +	writel(1, ctx->base + SOFT_RESET);
> +}
> +
> +/*
> + * Free up resources and shutdown host controller and PHY
> + */
> +static void sprd_dsi_fini(struct dsi_context *ctx)
> +{
> +	writel(0xffffffff, ctx->base + MASK_PROTOCOL_INT);
> +	writel(0xffffffff, ctx->base + MASK_INTERNAL_INT);
> +	writel(0, ctx->base + SOFT_RESET);
> +}
> +
> +/*
> + * If not in burst mode, it will compute the video and null packet sizes
> + * according to necessity.
> + * Configure timers for data lanes and/or clock lane to return to LP when
> + * bandwidth is not filled by data.
> + */
> +static int sprd_dsi_dpi_video(struct dsi_context *ctx)
> +{
> +	struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
> +	struct videomode *vm = &ctx->vm;
> +	u32 byte_clk = dsi->slave->hs_rate / 8;
> +	u16 Bpp_x100;
> +	u16 video_size;
> +	u32 ratio_x1000;
> +	u16 null_pkt_size = 0;
> +	u8 video_size_step;
> +	u32 hs_to;
> +	u32 total_bytes;
> +	u32 bytes_per_chunk;
> +	u32 chunks = 0;
> +	u32 bytes_left = 0;
> +	u32 chunk_overhead;
> +	const u8 pkt_header = 6;
> +	u8 coding;
> +	int div;
> +	u16 hline;
> +	u16 byte_cycle;
> +
> +	coding = fmt_to_coding(dsi->slave->format);
> +	video_size = round_video_size(coding, vm->hactive);
> +	Bpp_x100 = calc_bytes_per_pixel_x100(coding);
> +	video_size_step = calc_video_size_step(coding);
> +	ratio_x1000 = byte_clk * 1000 / (vm->pixelclock / 1000);
> +	hline = vm->hactive + vm->hsync_len + vm->hfront_porch +
> +		vm->hback_porch;
> +
> +	writel(0, ctx->base + SOFT_RESET);
> +	dsi_reg_wr(ctx, VID_MODE_CFG, FRAME_BTA_ACK_EN, 15, ctx->frame_ack_en);
> +	dsi_reg_wr(ctx, DPI_VIDEO_FORMAT, DPI_VIDEO_MODE_FORMAT, 0, coding);
> +	dsi_reg_wr(ctx, VID_MODE_CFG, VID_MODE_TYPE, 0, ctx->burst_mode);
> +	byte_cycle = 95 * hline * ratio_x1000 / 100000;
> +	dsi_reg_wr(ctx, VIDEO_SIG_DELAY_CONFIG, VIDEO_SIG_DELAY, 0, byte_cycle);
> +	byte_cycle = hline * ratio_x1000 / 1000;
> +	writel(byte_cycle, ctx->base + VIDEO_LINE_TIME);
> +	byte_cycle = vm->hsync_len * ratio_x1000 / 1000;
> +	dsi_reg_wr(ctx, VIDEO_LINE_HBLK_TIME, VIDEO_LINE_HSA_TIME, 16, byte_cycle);
> +	byte_cycle = vm->hback_porch * ratio_x1000 / 1000;
> +	dsi_reg_wr(ctx, VIDEO_LINE_HBLK_TIME, VIDEO_LINE_HBP_TIME, 0, byte_cycle);
> +	writel(vm->vactive, ctx->base + VIDEO_VACTIVE_LINES);
> +	dsi_reg_wr(ctx, VIDEO_VBLK_LINES, VFP_LINES, 0, vm->vfront_porch);
> +	dsi_reg_wr(ctx, VIDEO_VBLK_LINES, VBP_LINES, 10, vm->vback_porch);
> +	dsi_reg_wr(ctx, VIDEO_VBLK_LINES, VSA_LINES, 20, vm->vsync_len);
> +	dsi_reg_up(ctx, VID_MODE_CFG, LP_HBP_EN | LP_HFP_EN | LP_VACT_EN |
> +			LP_VFP_EN | LP_VBP_EN | LP_VSA_EN, LP_HBP_EN | LP_HFP_EN |
> +			LP_VACT_EN | LP_VFP_EN | LP_VBP_EN | LP_VSA_EN);
> +
> +	hs_to = (hline * vm->vactive) + (2 * Bpp_x100) / 100;
> +	for (div = 0x80; (div < hs_to) && (div > 2); div--) {
> +		if ((hs_to % div) == 0) {
> +			writel(div, ctx->base + TIMEOUT_CNT_CLK_CONFIG);
> +			writel(hs_to / div, ctx->base + LRX_H_TO_CONFIG);
> +			writel(hs_to / div, ctx->base + HTX_TO_CONFIG);
> +			break;
> +		}
> +	}
> +
> +	if (ctx->burst_mode == VIDEO_BURST_WITH_SYNC_PULSES) {
> +		dsi_reg_wr(ctx, VIDEO_PKT_CONFIG, VIDEO_PKT_SIZE, 0, video_size);
> +		writel(0, ctx->base + VIDEO_NULLPKT_SIZE);
> +		dsi_reg_up(ctx, VIDEO_PKT_CONFIG, VIDEO_LINE_CHUNK_NUM, 0);
> +	} else {
> +		/* non burst transmission */
> +		null_pkt_size = 0;
> +
> +		/* bytes to be sent - first as one chunk */
> +		bytes_per_chunk = vm->hactive * Bpp_x100 / 100 + pkt_header;
> +
> +		/* hline total bytes from the DPI interface */
> +		total_bytes = (vm->hactive + vm->hfront_porch) *
> +				ratio_x1000 / dsi->slave->lanes / 1000;
> +
> +		/* check if the pixels actually fit on the DSI link */
> +		if (total_bytes < bytes_per_chunk) {
> +			drm_err(dsi->drm, "current resolution can not be set\n");
> +			return -EINVAL;
> +		}
> +
> +		chunk_overhead = total_bytes - bytes_per_chunk;
> +
> +		/* overhead higher than 1 -> enable multi packets */
> +		if (chunk_overhead > 1) {
> +
> +			/* multi packets */
> +			for (video_size = video_size_step;
> +			     video_size < vm->hactive;
> +			     video_size += video_size_step) {
> +
> +				if (vm->hactive * 1000 / video_size % 1000)
> +					continue;
> +
> +				chunks = vm->hactive / video_size;
> +				bytes_per_chunk = Bpp_x100 * video_size / 100
> +						  + pkt_header;
> +				if (total_bytes >= (bytes_per_chunk * chunks)) {
> +					bytes_left = total_bytes -
> +						     bytes_per_chunk * chunks;
> +					break;
> +				}
> +			}
> +
> +			/* prevent overflow (unsigned - unsigned) */
> +			if (bytes_left > (pkt_header * chunks)) {
> +				null_pkt_size = (bytes_left -
> +						pkt_header * chunks) / chunks;
> +				/* avoid register overflow */
> +				if (null_pkt_size > 1023)
> +					null_pkt_size = 1023;
> +			}
> +
> +		} else {
> +
> +			/* single packet */
> +			chunks = 1;
> +
> +			/* must be a multiple of 4 except 18 loosely */
> +			for (video_size = vm->hactive;
> +			    (video_size % video_size_step) != 0;
> +			     video_size++)
> +				;
> +		}
> +
> +		dsi_reg_wr(ctx, VIDEO_PKT_CONFIG, VIDEO_PKT_SIZE, 0, video_size);
> +		writel(null_pkt_size, ctx->base + VIDEO_NULLPKT_SIZE);
> +		dsi_reg_wr(ctx, VIDEO_PKT_CONFIG, VIDEO_LINE_CHUNK_NUM, 16, chunks);
> +	}
> +
> +	writel(ctx->int0_mask, ctx->base + MASK_PROTOCOL_INT);
> +	writel(ctx->int1_mask, ctx->base + MASK_INTERNAL_INT);
> +	writel(1, ctx->base + SOFT_RESET);
> +
> +	return 0;
> +}
> +
> +static void sprd_dsi_edpi_video(struct dsi_context *ctx)
> +{
> +	struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
> +	const u32 fifo_depth = 1096;
> +	const u32 word_length = 4;
> +	u32 hactive = ctx->vm.hactive;
> +	u32 Bpp_x100;
> +	u32 max_fifo_len;
> +	u8 coding;
> +
> +	coding = fmt_to_coding(dsi->slave->format);
> +	Bpp_x100 = calc_bytes_per_pixel_x100(coding);
> +	max_fifo_len = word_length * fifo_depth * 100 / Bpp_x100;
> +
> +	writel(0, ctx->base + SOFT_RESET);
> +	dsi_reg_wr(ctx, DPI_VIDEO_FORMAT, DPI_VIDEO_MODE_FORMAT, 0, coding);
> +	dsi_reg_wr(ctx, CMD_MODE_CFG, TEAR_FX_EN, 0, ctx->te_ack_en);
> +
> +	if (max_fifo_len > hactive)
> +		writel(hactive, ctx->base + DCS_WM_PKT_SIZE);
> +	else
> +		writel(max_fifo_len, ctx->base + DCS_WM_PKT_SIZE);
> +
> +	writel(ctx->int0_mask, ctx->base + MASK_PROTOCOL_INT);
> +	writel(ctx->int1_mask, ctx->base + MASK_INTERNAL_INT);
> +	writel(1, ctx->base + SOFT_RESET);
> +}
> +
> +/*
> + * Send a packet on the generic interface,
> + * this function has an active delay to wait for the buffer to clear.
> + * The delay is limited to:
> + * (param_length / 4) x DSIH_FIFO_ACTIVE_WAIT x register access time
> + * the controller restricts the sending of.
> + *
> + * This function will not be able to send Null and Blanking packets due to
> + * controller restriction
> + */
> +static int sprd_dsi_wr_pkt(struct dsi_context *ctx, u8 vc, u8 type,
> +			const u8 *param, u16 len)
> +{
> +	struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
> +	u8 wc_lsbyte, wc_msbyte;
> +	u32 payload;
> +	int i, j, ret;
> +
> +	if (vc > 3)
> +		return -EINVAL;
> +
> +
> +	/* 1st: for long packet, must config payload first */
> +	ret = dsi_wait_tx_payload_fifo_empty(ctx);
> +	if (ret) {
> +		drm_err(dsi->drm, "tx payload fifo is not empty\n");
> +		return ret;
> +	}
> +
> +	if (len > 2) {
> +		for (i = 0, j = 0; i < len; i += j) {
> +			payload = 0;
> +			for (j = 0; (j < 4) && ((j + i) < (len)); j++)
> +				payload |= param[i + j] << (j * 8);
> +
> +			writel(payload, ctx->base + GEN_PLD_DATA);
> +		}
> +		wc_lsbyte = len & 0xff;
> +		wc_msbyte = len >> 8;
> +	} else {
> +		wc_lsbyte = (len > 0) ? param[0] : 0;
> +		wc_msbyte = (len > 1) ? param[1] : 0;
> +	}
> +
> +	/* 2nd: then set packet header */
> +	ret = dsi_wait_tx_cmd_fifo_empty(ctx);
> +	if (ret) {
> +		drm_err(dsi->drm, "tx cmd fifo is not empty\n");
> +		return ret;
> +	}
> +
> +	writel(type | (vc << 6) | (wc_lsbyte << 8) | (wc_msbyte << 16),
> +			ctx->base + GEN_HDR);
> +
> +	return 0;
> +}
> +
> +/*
> + * Send READ packet to peripheral using the generic interface,
> + * this will force command mode and stop video mode (because of BTA).
> + *
> + * This function has an active delay to wait for the buffer to clear,
> + * the delay is limited to 2 x DSIH_FIFO_ACTIVE_WAIT
> + * (waiting for command buffer, and waiting for receiving)
> + * @note this function will enable BTA
> + */
> +static int sprd_dsi_rd_pkt(struct dsi_context *ctx, u8 vc, u8 type,
> +			u8 msb_byte, u8 lsb_byte,
> +			u8 *buffer, u8 bytes_to_read)
> +{
> +	struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
> +	int i, ret;
> +	int count = 0;
> +	u32 temp;
> +
> +	if (vc > 3)
> +		return -EINVAL;
> +
> +	/* 1st: send read command to peripheral */
> +	ret = dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_CMD_FIFO_EMPTY, 5);
> +	if (!ret)
> +		return -EIO;
> +
> +	writel(type | (vc << 6) | (lsb_byte << 8) | (msb_byte << 16),
> +			ctx->base + GEN_HDR);
> +
> +	/* 2nd: wait peripheral response completed */
> +	ret = dsi_wait_rd_resp_completed(ctx);
> +	if (ret) {
> +		drm_err(dsi->drm, "wait read response time out\n");
> +		return ret;
> +	}
> +
> +	/* 3rd: get data from rx payload fifo */
> +	ret = dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_RDATA_FIFO_EMPTY, 1);
> +	if (ret) {
> +		drm_err(dsi->drm, "rx payload fifo empty\n");
> +		return -EIO;
> +	}
> +
> +	for (i = 0; i < 100; i++) {
> +		temp = readl(ctx->base + GEN_PLD_DATA);
> +
> +		if (count < bytes_to_read)
> +			buffer[count++] = temp & 0xff;
> +		if (count < bytes_to_read)
> +			buffer[count++] = (temp >> 8) & 0xff;
> +		if (count < bytes_to_read)
> +			buffer[count++] = (temp >> 16) & 0xff;
> +		if (count < bytes_to_read)
> +			buffer[count++] = (temp >> 24) & 0xff;
> +
> +		ret = dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_RDATA_FIFO_EMPTY, 1);
> +		if (ret)
> +			return count;
> +	}
> +
> +	return 0;
> +}
> +
> +static void sprd_dsi_set_work_mode(struct dsi_context *ctx, u8 mode)
> +{
> +	if (mode == DSI_MODE_CMD)
> +		writel(1, ctx->base + DSI_MODE_CFG);
> +	else
> +		writel(0, ctx->base + DSI_MODE_CFG);
> +}
> +
> +static void sprd_dsi_lp_cmd_enable(struct dsi_context *ctx)
> +{
> +	if (readl(ctx->base + DSI_MODE_CFG))
> +		dsi_reg_up(ctx, CMD_MODE_CFG, GEN_SW_0P_TX | GEN_SW_1P_TX |
> +			GEN_SW_2P_TX | GEN_SR_0P_TX | GEN_SR_1P_TX | GEN_SR_2P_TX |
> +			GEN_LW_TX | DCS_SW_0P_TX | DCS_SW_1P_TX | DCS_SR_0P_TX |
> +			DCS_LW_TX | MAX_RD_PKT_SIZE, GEN_SW_0P_TX | GEN_SW_1P_TX |
> +			GEN_SW_2P_TX | GEN_SR_0P_TX | GEN_SR_1P_TX | GEN_SR_2P_TX |
> +			GEN_LW_TX | DCS_SW_0P_TX | DCS_SW_1P_TX | DCS_SR_0P_TX |
> +			DCS_LW_TX | MAX_RD_PKT_SIZE);
> +	else
> +		dsi_reg_up(ctx, VID_MODE_CFG, LP_CMD_EN, LP_CMD_EN);
> +}
> +
> +static void sprd_dsi_state_reset(struct dsi_context *ctx)
> +{
> +	writel(0, ctx->base + SOFT_RESET);
> +	udelay(100);
> +	writel(1, ctx->base + SOFT_RESET);
> +}
> +
> +static int sprd_dphy_init(struct dsi_context *ctx)
> +{
> +	struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
> +	int ret;
> +
> +	dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_RESET_N, 0);
> +	dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_SHUTDOWN, 0);
> +	dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_CLK_EN, 0);
> +
> +	dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLR, 0);
> +	dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLR, PHY_TESTCLR);
> +	dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLR, 0);
> +
> +	dphy_pll_config(ctx);
> +	dphy_timing_config(ctx);
> +
> +	dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_SHUTDOWN, RF_PHY_SHUTDOWN);
> +	dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_RESET_N, RF_PHY_RESET_N);
> +	writel(0x1C, ctx->base + PHY_MIN_STOP_TIME);
> +	dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_CLK_EN, RF_PHY_CLK_EN);
> +	writel(dsi->slave->lanes - 1, ctx->base + PHY_LANE_NUM_CONFIG);
> +
> +	ret = dphy_wait_pll_locked(ctx);
> +	if (ret) {
> +		drm_err(dsi->drm, "dphy initial failed\n");
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static void sprd_dphy_fini(struct dsi_context *ctx)
> +{
> +	dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_RESET_N, 0);
> +	dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_SHUTDOWN, 0);
> +	dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_RESET_N, RF_PHY_RESET_N);
> +}
> +
> +static void sprd_dsi_encoder_enable(struct drm_encoder *encoder)
> +{
> +	struct sprd_dsi *dsi = encoder_to_dsi(encoder);
> +	struct sprd_dpu *dpu = to_sprd_crtc(encoder->crtc);
> +	struct dsi_context *ctx = &dsi->ctx;
> +
> +	if (ctx->enabled) {
> +		drm_warn(dsi->drm, "dsi is initialized\n");
> +		return;
> +	}
> +
> +	sprd_dsi_init(ctx);
> +	if (ctx->work_mode == DSI_MODE_VIDEO)
> +		sprd_dsi_dpi_video(ctx);
> +	else
> +		sprd_dsi_edpi_video(ctx);
> +
> +	sprd_dphy_init(ctx);
> +
> +	sprd_dsi_lp_cmd_enable(ctx);
> +
> +	if (dsi->panel) {
> +		drm_panel_prepare(dsi->panel);
> +		drm_panel_enable(dsi->panel);
> +	}

Please use the new devm_drm_of_get_bridge helper here, and use the
bridge API instead.

> +	sprd_dsi_set_work_mode(ctx, ctx->work_mode);
> +	sprd_dsi_state_reset(ctx);
> +
> +	if (dsi->slave->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
> +		dsi_reg_up(ctx, PHY_CLK_LANE_LP_CTRL, AUTO_CLKLANE_CTRL_EN,
> +				AUTO_CLKLANE_CTRL_EN);
> +	else {
> +		dsi_reg_up(ctx, PHY_CLK_LANE_LP_CTRL, RF_PHY_CLK_EN, RF_PHY_CLK_EN);
> +		dsi_reg_up(ctx, PHY_CLK_LANE_LP_CTRL, PHY_CLKLANE_TX_REQ_HS,
> +				PHY_CLKLANE_TX_REQ_HS);
> +		dphy_wait_pll_locked(ctx);
> +	}
> +
> +	sprd_dpu_run(dpu);
> +
> +	ctx->enabled = true;
> +}
> +
> +static void sprd_dsi_encoder_disable(struct drm_encoder *encoder)
> +{
> +	struct sprd_dsi *dsi = encoder_to_dsi(encoder);
> +	struct sprd_dpu *dpu = to_sprd_crtc(encoder->crtc);
> +	struct dsi_context *ctx = &dsi->ctx;
> +
> +	if (!ctx->enabled) {
> +		drm_warn(dsi->drm, "dsi isn't initialized\n");
> +		return;
> +	}
> +
> +	sprd_dpu_stop(dpu);
> +	sprd_dsi_set_work_mode(ctx, DSI_MODE_CMD);
> +	sprd_dsi_lp_cmd_enable(ctx);
> +
> +	if (dsi->panel) {
> +		drm_panel_disable(dsi->panel);
> +		drm_panel_unprepare(dsi->panel);
> +	}
> +
> +	sprd_dphy_fini(ctx);
> +	sprd_dsi_fini(ctx);
> +
> +	ctx->enabled = false;
> +}
> +
> +static void sprd_dsi_encoder_mode_set(struct drm_encoder *encoder,
> +				 struct drm_display_mode *mode,
> +				 struct drm_display_mode *adj_mode)
> +{
> +	struct sprd_dsi *dsi = encoder_to_dsi(encoder);
> +
> +	drm_dbg(dsi->drm, "%s() set mode: %s\n", __func__, dsi->mode->name);
> +}

You don't need that function?

> +static int sprd_dsi_encoder_atomic_check(struct drm_encoder *encoder,
> +				    struct drm_crtc_state *crtc_state,
> +				    struct drm_connector_state *conn_state)
> +{
> +	return 0;
> +}

Ditto

> +static const struct drm_encoder_helper_funcs sprd_encoder_helper_funcs = {
> +	.atomic_check	= sprd_dsi_encoder_atomic_check,
> +	.mode_set	= sprd_dsi_encoder_mode_set,
> +	.enable		= sprd_dsi_encoder_enable,
> +	.disable	= sprd_dsi_encoder_disable
> +};
> +
> +static const struct drm_encoder_funcs sprd_encoder_funcs = {
> +	.destroy = drm_encoder_cleanup,
> +};
> +
> +static struct sprd_dsi *sprd_dsi_encoder_init(struct drm_device *drm,
> +			       struct device *dev)
> +{
> +	struct sprd_dsi *dsi;
> +	u32 crtc_mask;
> +
> +	crtc_mask = drm_of_find_possible_crtcs(drm, dev->of_node);
> +	if (!crtc_mask) {
> +		drm_err(drm, "failed to find crtc mask\n");
> +		return ERR_PTR(-EINVAL);
> +	}
> +
> +	drm_dbg(drm, "find possible crtcs: 0x%08x\n", crtc_mask);
> +
> +	dsi = drmm_encoder_alloc(drm, struct sprd_dsi, encoder,
> +			       &sprd_encoder_funcs, DRM_MODE_ENCODER_DSI, NULL);
> +	if (IS_ERR(dsi)) {
> +		drm_err(drm, "failed to init dsi encoder.\n");
> +		return dsi;
> +	}
> +
> +	dsi->encoder.possible_crtcs = crtc_mask;
> +	drm_encoder_helper_add(&dsi->encoder, &sprd_encoder_helper_funcs);
> +
> +	return dsi;
> +}
> +
> +static int sprd_dsi_find_panel(struct sprd_dsi *dsi)
> +{
> +	struct device *dev = dsi->host.dev;
> +	struct device_node *child, *lcds_node;
> +	struct drm_panel *panel;
> +
> +	/* search /lcds child node first */
> +	lcds_node = of_find_node_by_path("/lcds");
> +	for_each_child_of_node(lcds_node, child) {
> +		panel = of_drm_find_panel(child);
> +		if (!IS_ERR(panel)) {
> +			dsi->panel = panel;
> +			return 0;
> +		}
> +	}
> +
> +	/*
> +	 * If /lcds child node search failed, we search
> +	 * the child of dsi host node.
> +	 */
> +	for_each_child_of_node(dev->of_node, child) {
> +		panel = of_drm_find_panel(child);
> +		if (!IS_ERR(panel)) {
> +			dsi->panel = panel;
> +			return 0;
> +		}
> +	}
> +
> +	drm_err(dsi->drm, "of_drm_find_panel() failed\n");
> +	return -ENODEV;
> +}

Just use devm_drm_of_get_bridge there

> +static int sprd_dsi_host_attach(struct mipi_dsi_host *host,
> +			   struct mipi_dsi_device *slave)
> +{
> +	struct sprd_dsi *dsi = host_to_dsi(host);
> +	struct dsi_context *ctx = &dsi->ctx;
> +	int ret;
> +
> +	dsi->slave = slave;
> +
> +	if (slave->mode_flags & MIPI_DSI_MODE_VIDEO)
> +		ctx->work_mode = DSI_MODE_VIDEO;
> +	else
> +		ctx->work_mode = DSI_MODE_CMD;
> +
> +	if (slave->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
> +		ctx->burst_mode = VIDEO_BURST_WITH_SYNC_PULSES;
> +	else if (slave->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
> +		ctx->burst_mode = VIDEO_NON_BURST_WITH_SYNC_PULSES;
> +	else
> +		ctx->burst_mode = VIDEO_NON_BURST_WITH_SYNC_EVENTS;
> +
> +	ret = sprd_dsi_find_panel(dsi);
> +	if (ret)
> +		return ret;
> +
> +	return 0;
> +}
> +
> +static int sprd_dsi_host_detach(struct mipi_dsi_host *host,
> +			   struct mipi_dsi_device *slave)
> +{
> +	/* do nothing */
> +	return 0;
> +}
> +
> +static ssize_t sprd_dsi_host_transfer(struct mipi_dsi_host *host,
> +				const struct mipi_dsi_msg *msg)
> +{
> +	struct sprd_dsi *dsi = host_to_dsi(host);
> +	const u8 *tx_buf = msg->tx_buf;
> +
> +	if (msg->rx_buf && msg->rx_len) {
> +		u8 lsb = (msg->tx_len > 0) ? tx_buf[0] : 0;
> +		u8 msb = (msg->tx_len > 1) ? tx_buf[1] : 0;
> +
> +		return sprd_dsi_rd_pkt(&dsi->ctx, msg->channel, msg->type,
> +				msb, lsb, msg->rx_buf, msg->rx_len);
> +	}
> +
> +	if (msg->tx_buf && msg->tx_len)
> +		return sprd_dsi_wr_pkt(&dsi->ctx, msg->channel, msg->type,
> +					tx_buf, msg->tx_len);
> +
> +	return 0;
> +}
> +
> +static const struct mipi_dsi_host_ops sprd_dsi_host_ops = {
> +	.attach = sprd_dsi_host_attach,
> +	.detach = sprd_dsi_host_detach,
> +	.transfer = sprd_dsi_host_transfer,
> +};
> +
> +static int sprd_dsi_host_init(struct sprd_dsi *dsi, struct device *dev)
> +{
> +	int ret;
> +
> +	dsi->host.dev = dev;
> +	dsi->host.ops = &sprd_dsi_host_ops;
> +
> +	ret = mipi_dsi_host_register(&dsi->host);
> +	if (ret)
> +		drm_err(dsi->drm, "failed to register dsi host\n");
> +
> +	return ret;
> +}
> +
> +static int sprd_dsi_connector_get_modes(struct drm_connector *connector)
> +{
> +	struct sprd_dsi *dsi = connector_to_dsi(connector);
> +
> +	return drm_panel_get_modes(dsi->panel, connector);
> +}
> +
> +static enum drm_mode_status
> +sprd_dsi_connector_mode_valid(struct drm_connector *connector,
> +			 struct drm_display_mode *mode)
> +{
> +	struct sprd_dsi *dsi = connector_to_dsi(connector);
> +
> +	drm_dbg(dsi->drm, "%s() mode: "DRM_MODE_FMT"\n", __func__, DRM_MODE_ARG(mode));
> +
> +	if (mode->type & DRM_MODE_TYPE_PREFERRED) {
> +		dsi->mode = mode;
> +		drm_display_mode_to_videomode(dsi->mode, &dsi->ctx.vm);
> +	}

I already told you this, but you shouldn't modify your state in
mode_valid, and certainly not based on whether it's the preferred mode
or not.

> +	return MODE_OK;
> +}
> +
> +static struct drm_encoder *
> +sprd_dsi_connector_best_encoder(struct drm_connector *connector)
> +{
> +	struct sprd_dsi *dsi = connector_to_dsi(connector);
> +
> +	return &dsi->encoder;
> +}
> +
> +static struct drm_connector_helper_funcs sprd_dsi_connector_helper_funcs = {
> +	.get_modes = sprd_dsi_connector_get_modes,
> +	.mode_valid = sprd_dsi_connector_mode_valid,
> +	.best_encoder = sprd_dsi_connector_best_encoder,
> +};
> +
> +static enum drm_connector_status
> +sprd_dsi_connector_detect(struct drm_connector *connector, bool force)
> +{
> +	struct sprd_dsi *dsi = connector_to_dsi(connector);
> +
> +	if (dsi->panel) {
> +		drm_panel_add(dsi->panel);
> +		return connector_status_connected;
> +	}
> +
> +	return connector_status_disconnected;
> +}
> +
> +static void sprd_dsi_connector_destroy(struct drm_connector *connector)
> +{
> +	drm_connector_unregister(connector);
> +	drm_connector_cleanup(connector);
> +}
> +
> +static const struct drm_connector_funcs sprd_dsi_atomic_connector_funcs = {
> +	.fill_modes = drm_helper_probe_single_connector_modes,
> +	.detect = sprd_dsi_connector_detect,
> +	.destroy = sprd_dsi_connector_destroy,
> +	.reset = drm_atomic_helper_connector_reset,
> +	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
> +	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> +};
> +
> +static int sprd_dsi_connector_init(struct drm_device *drm, struct sprd_dsi *dsi)
> +{
> +	struct drm_encoder *encoder = &dsi->encoder;
> +	struct drm_connector *connector = &dsi->connector;
> +	int ret;
> +
> +	connector->polled = DRM_CONNECTOR_POLL_HPD;
> +
> +	ret = drm_connector_init(drm, connector,
> +				 &sprd_dsi_atomic_connector_funcs,
> +				 DRM_MODE_CONNECTOR_DSI);
> +	if (ret) {
> +		drm_err(drm, "drm_connector_init() failed\n");
> +		return ret;
> +	}
> +
> +	drm_connector_helper_add(connector,
> +				 &sprd_dsi_connector_helper_funcs);
> +
> +	drm_connector_attach_encoder(connector, encoder);
> +
> +	return 0;
> +}
> +
> +static int sprd_dsi_context_init(struct sprd_dsi *dsi,
> +			struct device *dev)
> +{
> +	struct platform_device *pdev = to_platform_device(dev);
> +	struct dsi_context *ctx = &dsi->ctx;
> +	struct resource *res;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	ctx->base = devm_ioremap(dev, res->start, resource_size(res));
> +	if (!ctx->base) {
> +		drm_err(dsi->drm, "failed to map dsi host registers\n");
> +		return -ENXIO;
> +	}
> +
> +	ctx->pll = devm_kzalloc(dev, sizeof(*ctx->pll), GFP_KERNEL);
> +	if (!ctx->pll)
> +		return -ENOMEM;
> +
> +	ctx->regmap = devm_regmap_init(dev, &regmap_tst_io, dsi, &byte_config);
> +	if (IS_ERR(ctx->regmap)) {
> +		drm_err(dsi->drm, "dphy regmap init failed\n");
> +		return PTR_ERR(ctx->regmap);
> +	}
> +
> +	ctx->data_hs2lp = 120;
> +	ctx->data_lp2hs = 500;
> +	ctx->clk_hs2lp = 4;
> +	ctx->clk_lp2hs = 15;
> +	ctx->max_rd_time = 6000;
> +	ctx->int0_mask = 0xffffffff;
> +	ctx->int1_mask = 0xffffffff;
> +	ctx->enabled = true;
> +
> +	return 0;
> +}
> +
> +static int sprd_dsi_bind(struct device *dev, struct device *master, void *data)
> +{
> +	struct drm_device *drm = data;
> +	struct sprd_dsi *dsi;
> +	int ret;
> +
> +	dsi = sprd_dsi_encoder_init(drm, dev);
> +	if (IS_ERR(dsi))
> +		return PTR_ERR(dsi);
> +
> +	dsi->drm = drm;
> +	dev_set_drvdata(dev, dsi);
> +
> +	ret = sprd_dsi_connector_init(drm, dsi);
> +	if (ret)
> +		return ret;
> +
> +	ret = sprd_dsi_context_init(dsi, dev);
> +	if (ret)
> +		return ret;
> +
> +	ret = sprd_dsi_host_init(dsi, dev);
> +	if (ret)
> +		return ret;
> +
> +	return 0;
> +}
> +
> +static void sprd_dsi_unbind(struct device *dev,
> +			struct device *master, void *data)
> +{
> +	struct sprd_dsi *dsi = dev_get_drvdata(dev);
> +
> +	mipi_dsi_host_unregister(&dsi->host);
> +}
> +
> +static const struct component_ops dsi_component_ops = {
> +	.bind	= sprd_dsi_bind,
> +	.unbind	= sprd_dsi_unbind,
> +};
> +
> +static const struct of_device_id dsi_match_table[] = {
> +	{ .compatible = "sprd,sharkl3-dsi-host" },
> +	{ /* sentinel */ },
> +};
> +
> +static int sprd_dsi_probe(struct platform_device *pdev)
> +{
> +	return component_add(&pdev->dev, &dsi_component_ops);

In order to prevent probe issues, you need to register you mipi_dsi_host
here, see:
https://lore.kernel.org/dri-devel/20210910101218.1632297-3-maxime@cerno.tech/

Maxime

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH v6 4/6] drm/sprd: add Unisoc's drm display controller driver

[Kevin Tang]

Maxime Ripard <maxime@cerno.tech> 于2021年9月17日周五 下午10:58写道：
>
> Hi,
>
> On Fri, Aug 13, 2021 at 10:53:00PM +0800, Kevin Tang wrote:
> > Adds DPU(Display Processor Unit) support for the Unisoc's display
> > subsystem.
> > It's support multi planes, scaler, rotation, PQ(Picture Quality) and more.
> >
> > v2:
> >   - Use drm_xxx to replace all DRM_XXX.
> >   - Use kzalloc to replace devm_kzalloc for sprd_dpu structure init.
> >
> > v3:
> >   - Remove dpu_layer stuff layer and commit layers by aotmic_update
> >
> > v4:
> >   - Use drmm_helpers to allocate crtc and planes.
> >   - Move rotation enum definitions to crtc layer reg bitfields.
> >   - Move allocate crtc and planes to bind function.
> >
> > v5:
> >   - Fix the checkpatch warnings.
> >   - Use mode_set_nofb instead of mode_valid callback.
> >   - Follow the OF-Graph bindings, use of_graph_get_port_by_id
> >     instead of of_parse_phandle.
> >   - Use zpos to represent the layer position.
> >   - Rebase to last drm misc branch.
> >
> > v6:
> >   - Disable and clear interrupts before register dpu IRQ
> >   - Init dpi config used by crtc_state->adjusted_mode on mode_set_nofb
> >   - Remove enable_irq and disable_irq function call.
> >   - Remove drm_format_info function call.
> >
> > Cc: Orson Zhai <orsonzhai@gmail.com>
> > Cc: Chunyan Zhang <zhang.lyra@gmail.com>
> > Signed-off-by: Kevin Tang <kevin.tang@unisoc.com>
> > ---
> >  drivers/gpu/drm/sprd/Kconfig    |   1 +
> >  drivers/gpu/drm/sprd/Makefile   |   3 +-
> >  drivers/gpu/drm/sprd/sprd_dpu.c | 937 ++++++++++++++++++++++++++++++++
> >  drivers/gpu/drm/sprd/sprd_dpu.h | 109 ++++
> >  drivers/gpu/drm/sprd/sprd_drm.c |   1 +
> >  drivers/gpu/drm/sprd/sprd_drm.h |   2 +
> >  6 files changed, 1052 insertions(+), 1 deletion(-)
> >  create mode 100644 drivers/gpu/drm/sprd/sprd_dpu.c
> >  create mode 100644 drivers/gpu/drm/sprd/sprd_dpu.h
> >
> > diff --git a/drivers/gpu/drm/sprd/Kconfig b/drivers/gpu/drm/sprd/Kconfig
> > index 726c3e76d..37762c333 100644
> > --- a/drivers/gpu/drm/sprd/Kconfig
> > +++ b/drivers/gpu/drm/sprd/Kconfig
> > @@ -5,6 +5,7 @@ config DRM_SPRD
> >       select DRM_GEM_CMA_HELPER
> >       select DRM_KMS_CMA_HELPER
> >       select DRM_KMS_HELPER
> > +     select VIDEOMODE_HELPERS
> >       help
> >         Choose this option if you have a Unisoc chipset.
> >         If M is selected the module will be called sprd_drm.
> > diff --git a/drivers/gpu/drm/sprd/Makefile b/drivers/gpu/drm/sprd/Makefile
> > index 9850f00b8..ab12b95e6 100644
> > --- a/drivers/gpu/drm/sprd/Makefile
> > +++ b/drivers/gpu/drm/sprd/Makefile
> > @@ -1,3 +1,4 @@
> >  # SPDX-License-Identifier: GPL-2.0
> >
> > -obj-y := sprd_drm.o
> > +obj-y := sprd_drm.o \
> > +     sprd_dpu.o
> > diff --git a/drivers/gpu/drm/sprd/sprd_dpu.c b/drivers/gpu/drm/sprd/sprd_dpu.c
> > new file mode 100644
> > index 000000000..448dd4fb6
> > --- /dev/null
> > +++ b/drivers/gpu/drm/sprd/sprd_dpu.c
> > @@ -0,0 +1,937 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2020 Unisoc Inc.
> > + */
> > +
> > +#include <linux/component.h>
> > +#include <linux/delay.h>
> > +#include <linux/dma-buf.h>
> > +#include <linux/io.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_graph.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/wait.h>
> > +#include <linux/workqueue.h>
> > +
> > +#include <drm/drm_atomic_helper.h>
> > +#include <drm/drm_crtc_helper.h>
> > +#include <drm/drm_fb_cma_helper.h>
> > +#include <drm/drm_gem_cma_helper.h>
> > +#include <drm/drm_gem_framebuffer_helper.h>
> > +#include <drm/drm_plane_helper.h>
> > +
> > +#include "sprd_drm.h"
> > +#include "sprd_dpu.h"
> > +
> > +/* Global control registers */
> > +#define REG_DPU_CTRL 0x04
> > +#define REG_DPU_CFG0 0x08
> > +#define REG_PANEL_SIZE       0x20
> > +#define REG_BLEND_SIZE       0x24
> > +#define REG_BG_COLOR 0x2C
> > +
> > +/* Layer0 control registers */
> > +#define REG_LAY_BASE_ADDR0   0x30
> > +#define REG_LAY_BASE_ADDR1   0x34
> > +#define REG_LAY_BASE_ADDR2   0x38
> > +#define REG_LAY_CTRL         0x40
> > +#define REG_LAY_SIZE         0x44
> > +#define REG_LAY_PITCH                0x48
> > +#define REG_LAY_POS          0x4C
> > +#define REG_LAY_ALPHA                0x50
> > +#define REG_LAY_CROP_START   0x5C
> > +
> > +/* Interrupt control registers */
> > +#define REG_DPU_INT_EN               0x1E0
> > +#define REG_DPU_INT_CLR              0x1E4
> > +#define REG_DPU_INT_STS              0x1E8
> > +
> > +/* DPI control registers */
> > +#define REG_DPI_CTRL         0x1F0
> > +#define REG_DPI_H_TIMING     0x1F4
> > +#define REG_DPI_V_TIMING     0x1F8
> > +
> > +/* MMU control registers */
> > +#define REG_MMU_EN                   0x800
> > +#define REG_MMU_VPN_RANGE            0x80C
> > +#define REG_MMU_VAOR_ADDR_RD         0x818
> > +#define REG_MMU_VAOR_ADDR_WR         0x81C
> > +#define REG_MMU_INV_ADDR_RD          0x820
> > +#define REG_MMU_INV_ADDR_WR          0x824
> > +#define REG_MMU_PPN1                 0x83C
> > +#define REG_MMU_RANGE1                       0x840
> > +#define REG_MMU_PPN2                 0x844
> > +#define REG_MMU_RANGE2                       0x848
> > +
> > +/* Global control bits */
> > +#define BIT_DPU_RUN                  BIT(0)
> > +#define BIT_DPU_STOP                 BIT(1)
> > +#define BIT_DPU_REG_UPDATE           BIT(2)
> > +#define BIT_DPU_IF_EDPI                      BIT(0)
> > +
> > +/* Layer control bits */
> > +#define BIT_DPU_LAY_EN                               BIT(0)
> > +#define BIT_DPU_LAY_LAYER_ALPHA                      (0x01 << 2)
> > +#define BIT_DPU_LAY_COMBO_ALPHA                      (0x02 << 2)
> > +#define BIT_DPU_LAY_FORMAT_YUV422_2PLANE             (0x00 << 4)
> > +#define BIT_DPU_LAY_FORMAT_YUV420_2PLANE             (0x01 << 4)
> > +#define BIT_DPU_LAY_FORMAT_YUV420_3PLANE             (0x02 << 4)
> > +#define BIT_DPU_LAY_FORMAT_ARGB8888                  (0x03 << 4)
> > +#define BIT_DPU_LAY_FORMAT_RGB565                    (0x04 << 4)
> > +#define BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3             (0x00 << 8)
> > +#define BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0             (0x01 << 8)
> > +#define BIT_DPU_LAY_NO_SWITCH                        (0x00 << 10)
> > +#define BIT_DPU_LAY_RB_OR_UV_SWITCH          (0x01 << 10)
> > +#define BIT_DPU_LAY_MODE_BLEND_NORMAL                (0x00 << 16)
> > +#define BIT_DPU_LAY_MODE_BLEND_PREMULT               (0x01 << 16)
> > +#define BIT_DPU_LAY_ROTATION_0               (0x00 << 20)
> > +#define BIT_DPU_LAY_ROTATION_90              (0x01 << 20)
> > +#define BIT_DPU_LAY_ROTATION_180     (0x02 << 20)
> > +#define BIT_DPU_LAY_ROTATION_270     (0x03 << 20)
> > +#define BIT_DPU_LAY_ROTATION_0_M     (0x04 << 20)
> > +#define BIT_DPU_LAY_ROTATION_90_M    (0x05 << 20)
> > +#define BIT_DPU_LAY_ROTATION_180_M   (0x06 << 20)
> > +#define BIT_DPU_LAY_ROTATION_270_M   (0x07 << 20)
> > +
> > +/* Interrupt control & status bits */
> > +#define BIT_DPU_INT_DONE             BIT(0)
> > +#define BIT_DPU_INT_TE                       BIT(1)
> > +#define BIT_DPU_INT_ERR                      BIT(2)
> > +#define BIT_DPU_INT_UPDATE_DONE              BIT(4)
> > +#define BIT_DPU_INT_VSYNC            BIT(5)
> > +#define BIT_DPU_INT_MMU_VAOR_RD              BIT(16)
> > +#define BIT_DPU_INT_MMU_VAOR_WR              BIT(17)
> > +#define BIT_DPU_INT_MMU_INV_RD               BIT(18)
> > +#define BIT_DPU_INT_MMU_INV_WR               BIT(19)
> > +
> > +/* DPI control bits */
> > +#define BIT_DPU_EDPI_TE_EN           BIT(8)
> > +#define BIT_DPU_EDPI_FROM_EXTERNAL_PAD       BIT(10)
> > +#define BIT_DPU_DPI_HALT_EN          BIT(16)
> > +
> > +static const u32 layer_fmts[] = {
> > +     DRM_FORMAT_XRGB8888,
> > +     DRM_FORMAT_XBGR8888,
> > +     DRM_FORMAT_ARGB8888,
> > +     DRM_FORMAT_ABGR8888,
> > +     DRM_FORMAT_RGBA8888,
> > +     DRM_FORMAT_BGRA8888,
> > +     DRM_FORMAT_RGBX8888,
> > +     DRM_FORMAT_RGB565,
> > +     DRM_FORMAT_BGR565,
> > +     DRM_FORMAT_NV12,
> > +     DRM_FORMAT_NV21,
> > +     DRM_FORMAT_NV16,
> > +     DRM_FORMAT_NV61,
> > +     DRM_FORMAT_YUV420,
> > +     DRM_FORMAT_YVU420,
> > +};
> > +
> > +struct sprd_plane {
> > +     struct drm_plane base;
> > +};
> > +
> > +static u32 check_mmu_isr(struct sprd_dpu *dpu, u32 reg_val)
> > +{
> > +     struct dpu_context *ctx = &dpu->ctx;
> > +     u32 mmu_mask = BIT_DPU_INT_MMU_VAOR_RD |
> > +                     BIT_DPU_INT_MMU_VAOR_WR |
> > +                     BIT_DPU_INT_MMU_INV_RD |
> > +                     BIT_DPU_INT_MMU_INV_WR;
> > +     u32 val = reg_val & mmu_mask;
> > +     int i;
> > +
> > +     if (val) {
> > +             drm_err(dpu->drm, "--- iommu interrupt err: 0x%04x ---\n", val);
> > +
> > +             if (val & BIT_DPU_INT_MMU_INV_RD)
> > +                     drm_err(dpu->drm, "iommu invalid read error, addr: 0x%08x\n",
> > +                             readl(ctx->base + REG_MMU_INV_ADDR_RD));
> > +             if (val & BIT_DPU_INT_MMU_INV_WR)
> > +                     drm_err(dpu->drm, "iommu invalid write error, addr: 0x%08x\n",
> > +                             readl(ctx->base + REG_MMU_INV_ADDR_WR));
> > +             if (val & BIT_DPU_INT_MMU_VAOR_RD)
> > +                     drm_err(dpu->drm, "iommu va out of range read error, addr: 0x%08x\n",
> > +                             readl(ctx->base + REG_MMU_VAOR_ADDR_RD));
> > +             if (val & BIT_DPU_INT_MMU_VAOR_WR)
> > +                     drm_err(dpu->drm, "iommu va out of range write error, addr: 0x%08x\n",
> > +                             readl(ctx->base + REG_MMU_VAOR_ADDR_WR));
> > +
> > +             for (i = 0; i < 8; i++) {
> > +                     reg_val = layer_reg_rd(ctx, REG_LAY_CTRL, i);
> > +                     if (reg_val & 0x1)
> > +                             drm_info(dpu->drm, "layer%d: 0x%x 0x%x 0x%x ctrl: 0x%x\n", i,
> > +                                     layer_reg_rd(ctx, REG_LAY_BASE_ADDR0, i),
> > +                                     layer_reg_rd(ctx, REG_LAY_BASE_ADDR1, i),
> > +                                     layer_reg_rd(ctx, REG_LAY_BASE_ADDR2, i),
> > +                                     layer_reg_rd(ctx, REG_LAY_CTRL, i));
> > +             }
> > +     }
> > +
> > +     return val;
> > +}
>
> We'll still want an Acked-by from one of the IOMMU maintainers. Last
> time they commented they were against that.
>
> > +static int dpu_wait_stop_done(struct sprd_dpu *dpu)
> > +{
> > +     struct dpu_context *ctx = &dpu->ctx;
> > +     int rc;
> > +
> > +     if (ctx->stopped)
> > +             return 0;
> > +
> > +     rc = wait_event_interruptible_timeout(ctx->wait_queue, ctx->evt_stop,
> > +                                            msecs_to_jiffies(500));
> > +     ctx->evt_stop = false;
> > +
> > +     ctx->stopped = true;
> > +
> > +     if (!rc) {
> > +             drm_err(dpu->drm, "dpu wait for stop done time out!\n");
> > +             return -ETIMEDOUT;
> > +     }
> > +
> > +     return 0;
> > +}
> > +
> > +static int dpu_wait_update_done(struct sprd_dpu *dpu)
> > +{
> > +     struct dpu_context *ctx = &dpu->ctx;
> > +     int rc;
> > +
> > +     ctx->evt_update = false;
> > +
> > +     rc = wait_event_interruptible_timeout(ctx->wait_queue, ctx->evt_update,
> > +                                            msecs_to_jiffies(500));
> > +
> > +     if (!rc) {
> > +             drm_err(dpu->drm, "dpu wait for reg update done time out!\n");
> > +             return -ETIMEDOUT;
> > +     }
> > +
> > +     return 0;
> > +}
> > +
> > +static u32 drm_format_to_dpu(struct drm_framebuffer *fb)
> > +{
> > +     u32 format = 0;
> > +
> > +     switch (fb->format->format) {
> > +     case DRM_FORMAT_BGRA8888:
> > +             /* BGRA8888 -> ARGB8888 */
> > +             format |= BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0;
> > +             format |= BIT_DPU_LAY_FORMAT_ARGB8888;
> > +             break;
> > +     case DRM_FORMAT_RGBX8888:
> > +     case DRM_FORMAT_RGBA8888:
> > +             /* RGBA8888 -> ABGR8888 */
> > +             format |= BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0;
> > +             fallthrough;
> > +     case DRM_FORMAT_ABGR8888:
> > +             /* RB switch */
> > +             format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
> > +             fallthrough;
> > +     case DRM_FORMAT_ARGB8888:
> > +             format |= BIT_DPU_LAY_FORMAT_ARGB8888;
> > +             break;
> > +     case DRM_FORMAT_XBGR8888:
> > +             /* RB switch */
> > +             format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
> > +             fallthrough;
> > +     case DRM_FORMAT_XRGB8888:
> > +             format |= BIT_DPU_LAY_FORMAT_ARGB8888;
> > +             break;
> > +     case DRM_FORMAT_BGR565:
> > +             /* RB switch */
> > +             format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
> > +             fallthrough;
> > +     case DRM_FORMAT_RGB565:
> > +             format |= BIT_DPU_LAY_FORMAT_RGB565;
> > +             break;
> > +     case DRM_FORMAT_NV12:
> > +             /* 2-Lane: Yuv420 */
> > +             format |= BIT_DPU_LAY_FORMAT_YUV420_2PLANE;
> > +             /* Y endian */
> > +             format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
> > +             /* UV endian */
> > +             format |= BIT_DPU_LAY_NO_SWITCH;
> > +             break;
> > +     case DRM_FORMAT_NV21:
> > +             /* 2-Lane: Yuv420 */
> > +             format |= BIT_DPU_LAY_FORMAT_YUV420_2PLANE;
> > +             /* Y endian */
> > +             format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
> > +             /* UV endian */
> > +             format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
> > +             break;
> > +     case DRM_FORMAT_NV16:
> > +             /* 2-Lane: Yuv422 */
> > +             format |= BIT_DPU_LAY_FORMAT_YUV422_2PLANE;
> > +             /* Y endian */
> > +             format |= BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0;
> > +             /* UV endian */
> > +             format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
> > +             break;
> > +     case DRM_FORMAT_NV61:
> > +             /* 2-Lane: Yuv422 */
> > +             format |= BIT_DPU_LAY_FORMAT_YUV422_2PLANE;
> > +             /* Y endian */
> > +             format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
> > +             /* UV endian */
> > +             format |= BIT_DPU_LAY_NO_SWITCH;
> > +             break;
> > +     case DRM_FORMAT_YUV420:
> > +             format |= BIT_DPU_LAY_FORMAT_YUV420_3PLANE;
> > +             /* Y endian */
> > +             format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
> > +             /* UV endian */
> > +             format |= BIT_DPU_LAY_NO_SWITCH;
> > +             break;
> > +     case DRM_FORMAT_YVU420:
> > +             format |= BIT_DPU_LAY_FORMAT_YUV420_3PLANE;
> > +             /* Y endian */
> > +             format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
> > +             /* UV endian */
> > +             format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
> > +             break;
> > +     default:
> > +             break;
> > +     }
> > +
> > +     return format;
> > +}
> > +
> > +static u32 drm_rotation_to_dpu(struct drm_plane_state *state)
> > +{
> > +     u32 rotation = 0;
> > +
> > +     switch (state->rotation) {
> > +     default:
> > +     case DRM_MODE_ROTATE_0:
> > +             rotation = BIT_DPU_LAY_ROTATION_0;
> > +             break;
> > +     case DRM_MODE_ROTATE_90:
> > +             rotation = BIT_DPU_LAY_ROTATION_90;
> > +             break;
> > +     case DRM_MODE_ROTATE_180:
> > +             rotation = BIT_DPU_LAY_ROTATION_180;
> > +             break;
> > +     case DRM_MODE_ROTATE_270:
> > +             rotation = BIT_DPU_LAY_ROTATION_270;
> > +             break;
> > +     case DRM_MODE_REFLECT_Y:
> > +             rotation = BIT_DPU_LAY_ROTATION_180_M;
> > +             break;
> > +     case (DRM_MODE_REFLECT_Y | DRM_MODE_ROTATE_90):
> > +             rotation = BIT_DPU_LAY_ROTATION_90_M;
> > +             break;
> > +     case DRM_MODE_REFLECT_X:
> > +             rotation = BIT_DPU_LAY_ROTATION_0_M;
> > +             break;
> > +     case (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90):
> > +             rotation = BIT_DPU_LAY_ROTATION_270_M;
> > +             break;
> > +     }
> > +
> > +     return rotation;
> > +}
> > +
> > +static u32 drm_blend_to_dpu(struct drm_plane_state *state)
> > +{
> > +     u32 blend = 0;
> > +
> > +     switch (state->pixel_blend_mode) {
> > +     case DRM_MODE_BLEND_COVERAGE:
> > +             /* alpha mode select - combo alpha */
> > +             blend |= BIT_DPU_LAY_COMBO_ALPHA;
> > +             /* Normal mode */
> > +             blend |= BIT_DPU_LAY_MODE_BLEND_NORMAL;
> > +             break;
> > +     case DRM_MODE_BLEND_PREMULTI:
> > +             /* alpha mode select - combo alpha */
> > +             blend |= BIT_DPU_LAY_COMBO_ALPHA;
> > +             /* Pre-mult mode */
> > +             blend |= BIT_DPU_LAY_MODE_BLEND_PREMULT;
> > +             break;
> > +     case DRM_MODE_BLEND_PIXEL_NONE:
> > +     default:
> > +             /* don't do blending, maybe RGBX */
> > +             /* alpha mode select - layer alpha */
> > +             blend |= BIT_DPU_LAY_LAYER_ALPHA;
> > +             break;
> > +     }
> > +
> > +     return blend;
> > +}
> > +
> > +static void sprd_dpu_layer(struct sprd_dpu *dpu, struct drm_plane_state *state)
> > +{
> > +     struct dpu_context *ctx = &dpu->ctx;
> > +     struct drm_gem_cma_object *cma_obj;
> > +     struct drm_framebuffer *fb = state->fb;
> > +     u32 addr, size, offset, pitch, blend, format, rotation;
> > +     u32 src_x = state->src_x >> 16;
> > +     u32 src_y = state->src_y >> 16;
> > +     u32 src_w = state->src_w >> 16;
> > +     u32 src_h = state->src_h >> 16;
> > +     u32 dst_x = state->crtc_x;
> > +     u32 dst_y = state->crtc_y;
> > +     u32 alpha = state->alpha;
> > +     u32 index = state->zpos;
> > +     int i;
> > +
> > +     offset = (dst_x & 0xffff) | (dst_y << 16);
> > +     size = (src_w & 0xffff) | (src_h << 16);
> > +
> > +     for (i = 0; i < fb->format->num_planes; i++) {
> > +             cma_obj = drm_fb_cma_get_gem_obj(fb, i);
> > +             addr = cma_obj->paddr + fb->offsets[i];
> > +
> > +             if (i == 0)
> > +                     layer_reg_wr(ctx, REG_LAY_BASE_ADDR0, addr, index);
> > +             else if (i == 1)
> > +                     layer_reg_wr(ctx, REG_LAY_BASE_ADDR1, addr, index);
> > +             else
> > +                     layer_reg_wr(ctx, REG_LAY_BASE_ADDR2, addr, index);
> > +     }
> > +
> > +     if (fb->format->num_planes == 3) {
> > +             /* UV pitch is 1/2 of Y pitch */
> > +             pitch = (fb->pitches[0] / fb->format->cpp[0]) |
> > +                             (fb->pitches[0] / fb->format->cpp[0] << 15);
> > +     } else {
> > +             pitch = fb->pitches[0] / fb->format->cpp[0];
> > +     }
> > +
> > +     layer_reg_wr(ctx, REG_LAY_POS, offset, index);
> > +     layer_reg_wr(ctx, REG_LAY_SIZE, size, index);
> > +     layer_reg_wr(ctx, REG_LAY_CROP_START,
> > +                     src_y << 16 | src_x, index);
> > +     layer_reg_wr(ctx, REG_LAY_ALPHA, alpha, index);
> > +     layer_reg_wr(ctx, REG_LAY_PITCH, pitch, index);
> > +
> > +     format = drm_format_to_dpu(fb);
> > +     blend = drm_blend_to_dpu(state);
> > +     rotation = drm_rotation_to_dpu(state);
> > +
> > +     layer_reg_wr(ctx, REG_LAY_CTRL, BIT_DPU_LAY_EN |
> > +                             format |
> > +                             blend |
> > +                             rotation,
> > +                             index);
> > +}
> > +
> > +static void sprd_dpu_flip(struct sprd_dpu *dpu)
> > +{
> > +     struct dpu_context *ctx = &dpu->ctx;
> > +     u32 reg_val;
> > +
> > +     /*
> > +      * Make sure the dpu is in stop status. DPU has no shadow
> > +      * registers in EDPI mode. So the config registers can only be
> > +      * updated in the rising edge of DPU_RUN bit.
> > +      */
> > +     if (ctx->if_type == SPRD_DPU_IF_EDPI)
> > +             dpu_wait_stop_done(dpu);
> > +
> > +     /* update trigger and wait */
> > +     if (ctx->if_type == SPRD_DPU_IF_DPI) {
> > +             if (!ctx->stopped) {
> > +                     dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_REG_UPDATE);
> > +                     dpu_wait_update_done(dpu);
> > +             }
> > +
> > +             dpu_reg_set(ctx, REG_DPU_INT_EN, BIT_DPU_INT_ERR);
> > +     } else if (ctx->if_type == SPRD_DPU_IF_EDPI) {
> > +             dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_RUN);
> > +
> > +             ctx->stopped = false;
> > +     }
> > +
> > +     /*
> > +      * If the following interrupt was disabled in isr,
> > +      * re-enable it.
> > +      */
> > +     reg_val = BIT_DPU_INT_MMU_VAOR_RD |
> > +               BIT_DPU_INT_MMU_VAOR_WR |
> > +               BIT_DPU_INT_MMU_INV_RD |
> > +               BIT_DPU_INT_MMU_INV_WR;
> > +     dpu_reg_set(ctx, REG_DPU_INT_EN, reg_val);
> > +}
> > +
> > +static void sprd_dpu_init(struct sprd_dpu *dpu)
> > +{
> > +     struct dpu_context *ctx = &dpu->ctx;
> > +     u32 int_mask = 0;
> > +
> > +     writel(0x00, ctx->base + REG_BG_COLOR);
> > +     writel(0x00, ctx->base + REG_MMU_EN);
> > +     writel(0x00, ctx->base + REG_MMU_PPN1);
> > +     writel(0xffff, ctx->base + REG_MMU_RANGE1);
> > +     writel(0x00, ctx->base + REG_MMU_PPN2);
> > +     writel(0xffff, ctx->base + REG_MMU_RANGE2);
> > +     writel(0x1ffff, ctx->base + REG_MMU_VPN_RANGE);
> > +
> > +     if (ctx->if_type == SPRD_DPU_IF_DPI) {
> > +             /* use dpi as interface */
> > +             dpu_reg_clr(ctx, REG_DPU_CFG0, BIT_DPU_IF_EDPI);
> > +             /* disable Halt function for SPRD DSI */
> > +             dpu_reg_clr(ctx, REG_DPI_CTRL, BIT_DPU_DPI_HALT_EN);
> > +             /* select te from external pad */
> > +             dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_EDPI_FROM_EXTERNAL_PAD);
> > +
> > +             /* enable dpu update done INT */
> > +             int_mask |= BIT_DPU_INT_UPDATE_DONE;
> > +             /* enable dpu done INT */
> > +             int_mask |= BIT_DPU_INT_DONE;
> > +             /* enable dpu dpi vsync */
> > +             int_mask |= BIT_DPU_INT_VSYNC;
> > +             /* enable dpu TE INT */
> > +             int_mask |= BIT_DPU_INT_TE;
> > +             /* enable underflow err INT */
> > +             int_mask |= BIT_DPU_INT_ERR;
> > +     } else if (ctx->if_type == SPRD_DPU_IF_EDPI) {
> > +             /* use edpi as interface */
> > +             dpu_reg_set(ctx, REG_DPU_CFG0, BIT_DPU_IF_EDPI);
> > +             /* use external te */
> > +             dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_EDPI_FROM_EXTERNAL_PAD);
> > +             /* enable te */
> > +             dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_EDPI_TE_EN);
> > +
> > +             /* enable stop done INT */
> > +             int_mask |= BIT_DPU_INT_DONE;
> > +             /* enable TE INT */
> > +             int_mask |= BIT_DPU_INT_TE;
> > +     }
> > +
> > +     /* enable iommu va out of range read error INT */
> > +     int_mask |= BIT_DPU_INT_MMU_VAOR_RD;
> > +     /* enable iommu va out of range write error INT */
> > +     int_mask |= BIT_DPU_INT_MMU_VAOR_WR;
> > +     /* enable iommu invalid read error INT */
> > +     int_mask |= BIT_DPU_INT_MMU_INV_RD;
> > +     /* enable iommu invalid write error INT */
> > +     int_mask |= BIT_DPU_INT_MMU_INV_WR;
> > +
> > +     writel(int_mask, ctx->base + REG_DPU_INT_EN);
> > +}
> > +
> > +static void sprd_dpu_fini(struct sprd_dpu *dpu)
> > +{
> > +     struct dpu_context *ctx = &dpu->ctx;
> > +
> > +     writel(0x00, ctx->base + REG_DPU_INT_EN);
> > +     writel(0xff, ctx->base + REG_DPU_INT_CLR);
> > +}
> > +
> > +static void sprd_dpi_init(struct sprd_dpu *dpu)
> > +{
> > +     struct dpu_context *ctx = &dpu->ctx;
> > +     u32 reg_val;
> > +     u32 size;
> > +
> > +     size = (ctx->vm.vactive << 16) | ctx->vm.hactive;
> > +     writel(size, ctx->base + REG_PANEL_SIZE);
> > +     writel(size, ctx->base + REG_BLEND_SIZE);
> > +
> > +     if (ctx->if_type == SPRD_DPU_IF_DPI) {
> > +             /* set dpi timing */
> > +             reg_val = ctx->vm.hsync_len << 0 |
> > +                       ctx->vm.hback_porch << 8 |
> > +                       ctx->vm.hfront_porch << 20;
> > +             writel(reg_val, ctx->base + REG_DPI_H_TIMING);
> > +
> > +             reg_val = ctx->vm.vsync_len << 0 |
> > +                       ctx->vm.vback_porch << 8 |
> > +                       ctx->vm.vfront_porch << 20;
> > +             writel(reg_val, ctx->base + REG_DPI_V_TIMING);
> > +     }
> > +}
> > +
> > +void sprd_dpu_run(struct sprd_dpu *dpu)
> > +{
> > +     struct dpu_context *ctx = &dpu->ctx;
> > +
> > +     dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_RUN);
> > +
> > +     ctx->stopped = false;
> > +}
> > +
> > +void sprd_dpu_stop(struct sprd_dpu *dpu)
> > +{
> > +     struct dpu_context *ctx = &dpu->ctx;
> > +
> > +     if (ctx->if_type == SPRD_DPU_IF_DPI)
> > +             dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_STOP);
> > +
> > +     dpu_wait_stop_done(dpu);
> > +}
> > +
> > +static int sprd_plane_atomic_check(struct drm_plane *plane,
> > +                               struct drm_atomic_state *state)
> > +{
> > +     struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state,
> > +                                                                          plane);
> > +     struct drm_crtc_state *crtc_state;
> > +     u32 fmt;
> > +
> > +     if (!plane_state->fb || !plane_state->crtc)
> > +             return 0;
> > +
> > +     fmt = drm_format_to_dpu(plane_state->fb);
> > +     if (!fmt)
> > +             return -EINVAL;
> > +
> > +     crtc_state = drm_atomic_get_crtc_state(plane_state->state, plane_state->crtc);
> > +     if (IS_ERR(crtc_state))
> > +             return PTR_ERR(crtc_state);
> > +
> > +     return drm_atomic_helper_check_plane_state(plane_state, crtc_state,
> > +                                               DRM_PLANE_HELPER_NO_SCALING,
> > +                                               DRM_PLANE_HELPER_NO_SCALING,
> > +                                               true, true);
> > +}
> > +
> > +static void sprd_plane_atomic_update(struct drm_plane *drm_plane,
> > +                                 struct drm_atomic_state *state)
> > +{
> > +     struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
> > +                                                                        drm_plane);
> > +     struct sprd_dpu *dpu = to_sprd_crtc(new_state->crtc);
> > +
> > +     /* start configure dpu layers */
> > +     sprd_dpu_layer(dpu, new_state);
> > +}
> > +
> > +static void sprd_plane_atomic_disable(struct drm_plane *drm_plane,
> > +                                  struct drm_atomic_state *state)
> > +{
> > +     struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
> > +                                                                        drm_plane);
> > +     struct sprd_dpu *dpu = to_sprd_crtc(old_state->crtc);
> > +
> > +     layer_reg_wr(&dpu->ctx, REG_LAY_CTRL, 0x00, old_state->zpos);
> > +}
> > +
> > +static void sprd_plane_create_properties(struct sprd_plane *plane, int index)
> > +{
> > +     unsigned int supported_modes = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
> > +                                    BIT(DRM_MODE_BLEND_PREMULTI) |
> > +                                    BIT(DRM_MODE_BLEND_COVERAGE);
> > +
> > +     /* create rotation property */
> > +     drm_plane_create_rotation_property(&plane->base,
> > +                                        DRM_MODE_ROTATE_0,
> > +                                        DRM_MODE_ROTATE_MASK |
> > +                                        DRM_MODE_REFLECT_MASK);
> > +
> > +     /* create alpha property */
> > +     drm_plane_create_alpha_property(&plane->base);
> > +
> > +     /* create blend mode property */
> > +     drm_plane_create_blend_mode_property(&plane->base, supported_modes);
> > +
> > +     /* create zpos property */
> > +     drm_plane_create_zpos_immutable_property(&plane->base, index);
> > +}
> > +
> > +static const struct drm_plane_helper_funcs sprd_plane_helper_funcs = {
> > +     .atomic_check = sprd_plane_atomic_check,
> > +     .atomic_update = sprd_plane_atomic_update,
> > +     .atomic_disable = sprd_plane_atomic_disable,
> > +};
> > +
> > +static const struct drm_plane_funcs sprd_plane_funcs = {
> > +     .update_plane = drm_atomic_helper_update_plane,
> > +     .disable_plane  = drm_atomic_helper_disable_plane,
> > +     .destroy = drm_plane_cleanup,
> > +     .reset = drm_atomic_helper_plane_reset,
> > +     .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
> > +     .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
> > +};
> > +
> > +static struct sprd_plane *sprd_planes_init(struct drm_device *drm)
> > +{
> > +     struct sprd_plane *plane, *primary;
> > +     enum drm_plane_type plane_type;
> > +     int i;
> > +
> > +     for (i = 0; i < 6; i++) {
> > +             plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY :
> > +                                     DRM_PLANE_TYPE_OVERLAY;
> > +
> > +             plane = drmm_universal_plane_alloc(drm, struct sprd_plane, base,
> > +                                            1, &sprd_plane_funcs,
> > +                                            layer_fmts, ARRAY_SIZE(layer_fmts),
> > +                                            NULL, plane_type, NULL);
> > +             if (IS_ERR(plane)) {
> > +                     drm_err(drm, "failed to init drm plane: %d\n", i);
> > +                     return plane;
> > +             }
> > +
> > +             drm_plane_helper_add(&plane->base, &sprd_plane_helper_funcs);
> > +
> > +             sprd_plane_create_properties(plane, i);
> > +
> > +             if (i == 0)
> > +                     primary = plane;
> > +     }
> > +
> > +     return primary;
> > +}
> > +
> > +static void sprd_crtc_mode_set_nofb(struct drm_crtc *crtc)
> > +{
> > +     struct sprd_dpu *dpu = to_sprd_crtc(crtc);
> > +     struct drm_display_mode *mode = &crtc->state->adjusted_mode;
> > +
> > +     drm_display_mode_to_videomode(mode, &dpu->ctx.vm);
>
> You don't need to store the videomode into you dpu structure, just pass
> adjusted_mode to sprd_dpi_init.
I get it, thks.
>
> > +     sprd_dpi_init(dpu);
> > +}
> > +
> > +static void sprd_crtc_atomic_enable(struct drm_crtc *crtc,
> > +                                struct drm_atomic_state *state)
> > +{
> > +     struct sprd_dpu *dpu = to_sprd_crtc(crtc);
> > +
> > +     sprd_dpu_init(dpu);
>
> Do you need to do it on both mode_set_nofb and atomic_enable?
mode_set_nofb is sprd_dpi_init, but atomic_enable is sprd_dpu_init,
not the same interface.
>
> Maxime

Re: [PATCH v6 4/6] drm/sprd: add Unisoc's drm display controller driver

[Kevin Tang]

Maxime Ripard <maxime@cerno.tech> 于2021年9月17日周五 下午10:58写道：
>
> Hi,
>
> On Fri, Aug 13, 2021 at 10:53:00PM +0800, Kevin Tang wrote:
> > Adds DPU(Display Processor Unit) support for the Unisoc's display
> > subsystem.
> > It's support multi planes, scaler, rotation, PQ(Picture Quality) and more.
> >
> > v2:
> >   - Use drm_xxx to replace all DRM_XXX.
> >   - Use kzalloc to replace devm_kzalloc for sprd_dpu structure init.
> >
> > v3:
> >   - Remove dpu_layer stuff layer and commit layers by aotmic_update
> >
> > v4:
> >   - Use drmm_helpers to allocate crtc and planes.
> >   - Move rotation enum definitions to crtc layer reg bitfields.
> >   - Move allocate crtc and planes to bind function.
> >
> > v5:
> >   - Fix the checkpatch warnings.
> >   - Use mode_set_nofb instead of mode_valid callback.
> >   - Follow the OF-Graph bindings, use of_graph_get_port_by_id
> >     instead of of_parse_phandle.
> >   - Use zpos to represent the layer position.
> >   - Rebase to last drm misc branch.
> >
> > v6:
> >   - Disable and clear interrupts before register dpu IRQ
> >   - Init dpi config used by crtc_state->adjusted_mode on mode_set_nofb
> >   - Remove enable_irq and disable_irq function call.
> >   - Remove drm_format_info function call.
> >
> > Cc: Orson Zhai <orsonzhai@gmail.com>
> > Cc: Chunyan Zhang <zhang.lyra@gmail.com>
> > Signed-off-by: Kevin Tang <kevin.tang@unisoc.com>
> > ---
> >  drivers/gpu/drm/sprd/Kconfig    |   1 +
> >  drivers/gpu/drm/sprd/Makefile   |   3 +-
> >  drivers/gpu/drm/sprd/sprd_dpu.c | 937 ++++++++++++++++++++++++++++++++
> >  drivers/gpu/drm/sprd/sprd_dpu.h | 109 ++++
> >  drivers/gpu/drm/sprd/sprd_drm.c |   1 +
> >  drivers/gpu/drm/sprd/sprd_drm.h |   2 +
> >  6 files changed, 1052 insertions(+), 1 deletion(-)
> >  create mode 100644 drivers/gpu/drm/sprd/sprd_dpu.c
> >  create mode 100644 drivers/gpu/drm/sprd/sprd_dpu.h
> >
> > diff --git a/drivers/gpu/drm/sprd/Kconfig b/drivers/gpu/drm/sprd/Kconfig
> > index 726c3e76d..37762c333 100644
> > --- a/drivers/gpu/drm/sprd/Kconfig
> > +++ b/drivers/gpu/drm/sprd/Kconfig
> > @@ -5,6 +5,7 @@ config DRM_SPRD
> >       select DRM_GEM_CMA_HELPER
> >       select DRM_KMS_CMA_HELPER
> >       select DRM_KMS_HELPER
> > +     select VIDEOMODE_HELPERS
> >       help
> >         Choose this option if you have a Unisoc chipset.
> >         If M is selected the module will be called sprd_drm.
> > diff --git a/drivers/gpu/drm/sprd/Makefile b/drivers/gpu/drm/sprd/Makefile
> > index 9850f00b8..ab12b95e6 100644
> > --- a/drivers/gpu/drm/sprd/Makefile
> > +++ b/drivers/gpu/drm/sprd/Makefile
> > @@ -1,3 +1,4 @@
> >  # SPDX-License-Identifier: GPL-2.0
> >
> > -obj-y := sprd_drm.o
> > +obj-y := sprd_drm.o \
> > +     sprd_dpu.o
> > diff --git a/drivers/gpu/drm/sprd/sprd_dpu.c b/drivers/gpu/drm/sprd/sprd_dpu.c
> > new file mode 100644
> > index 000000000..448dd4fb6
> > --- /dev/null
> > +++ b/drivers/gpu/drm/sprd/sprd_dpu.c
> > @@ -0,0 +1,937 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2020 Unisoc Inc.
> > + */
> > +
> > +#include <linux/component.h>
> > +#include <linux/delay.h>
> > +#include <linux/dma-buf.h>
> > +#include <linux/io.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_graph.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/wait.h>
> > +#include <linux/workqueue.h>
> > +
> > +#include <drm/drm_atomic_helper.h>
> > +#include <drm/drm_crtc_helper.h>
> > +#include <drm/drm_fb_cma_helper.h>
> > +#include <drm/drm_gem_cma_helper.h>
> > +#include <drm/drm_gem_framebuffer_helper.h>
> > +#include <drm/drm_plane_helper.h>
> > +
> > +#include "sprd_drm.h"
> > +#include "sprd_dpu.h"
> > +
> > +/* Global control registers */
> > +#define REG_DPU_CTRL 0x04
> > +#define REG_DPU_CFG0 0x08
> > +#define REG_PANEL_SIZE       0x20
> > +#define REG_BLEND_SIZE       0x24
> > +#define REG_BG_COLOR 0x2C
> > +
> > +/* Layer0 control registers */
> > +#define REG_LAY_BASE_ADDR0   0x30
> > +#define REG_LAY_BASE_ADDR1   0x34
> > +#define REG_LAY_BASE_ADDR2   0x38
> > +#define REG_LAY_CTRL         0x40
> > +#define REG_LAY_SIZE         0x44
> > +#define REG_LAY_PITCH                0x48
> > +#define REG_LAY_POS          0x4C
> > +#define REG_LAY_ALPHA                0x50
> > +#define REG_LAY_CROP_START   0x5C
> > +
> > +/* Interrupt control registers */
> > +#define REG_DPU_INT_EN               0x1E0
> > +#define REG_DPU_INT_CLR              0x1E4
> > +#define REG_DPU_INT_STS              0x1E8
> > +
> > +/* DPI control registers */
> > +#define REG_DPI_CTRL         0x1F0
> > +#define REG_DPI_H_TIMING     0x1F4
> > +#define REG_DPI_V_TIMING     0x1F8
> > +
> > +/* MMU control registers */
> > +#define REG_MMU_EN                   0x800
> > +#define REG_MMU_VPN_RANGE            0x80C
> > +#define REG_MMU_VAOR_ADDR_RD         0x818
> > +#define REG_MMU_VAOR_ADDR_WR         0x81C
> > +#define REG_MMU_INV_ADDR_RD          0x820
> > +#define REG_MMU_INV_ADDR_WR          0x824
> > +#define REG_MMU_PPN1                 0x83C
> > +#define REG_MMU_RANGE1                       0x840
> > +#define REG_MMU_PPN2                 0x844
> > +#define REG_MMU_RANGE2                       0x848
> > +
> > +/* Global control bits */
> > +#define BIT_DPU_RUN                  BIT(0)
> > +#define BIT_DPU_STOP                 BIT(1)
> > +#define BIT_DPU_REG_UPDATE           BIT(2)
> > +#define BIT_DPU_IF_EDPI                      BIT(0)
> > +
> > +/* Layer control bits */
> > +#define BIT_DPU_LAY_EN                               BIT(0)
> > +#define BIT_DPU_LAY_LAYER_ALPHA                      (0x01 << 2)
> > +#define BIT_DPU_LAY_COMBO_ALPHA                      (0x02 << 2)
> > +#define BIT_DPU_LAY_FORMAT_YUV422_2PLANE             (0x00 << 4)
> > +#define BIT_DPU_LAY_FORMAT_YUV420_2PLANE             (0x01 << 4)
> > +#define BIT_DPU_LAY_FORMAT_YUV420_3PLANE             (0x02 << 4)
> > +#define BIT_DPU_LAY_FORMAT_ARGB8888                  (0x03 << 4)
> > +#define BIT_DPU_LAY_FORMAT_RGB565                    (0x04 << 4)
> > +#define BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3             (0x00 << 8)
> > +#define BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0             (0x01 << 8)
> > +#define BIT_DPU_LAY_NO_SWITCH                        (0x00 << 10)
> > +#define BIT_DPU_LAY_RB_OR_UV_SWITCH          (0x01 << 10)
> > +#define BIT_DPU_LAY_MODE_BLEND_NORMAL                (0x00 << 16)
> > +#define BIT_DPU_LAY_MODE_BLEND_PREMULT               (0x01 << 16)
> > +#define BIT_DPU_LAY_ROTATION_0               (0x00 << 20)
> > +#define BIT_DPU_LAY_ROTATION_90              (0x01 << 20)
> > +#define BIT_DPU_LAY_ROTATION_180     (0x02 << 20)
> > +#define BIT_DPU_LAY_ROTATION_270     (0x03 << 20)
> > +#define BIT_DPU_LAY_ROTATION_0_M     (0x04 << 20)
> > +#define BIT_DPU_LAY_ROTATION_90_M    (0x05 << 20)
> > +#define BIT_DPU_LAY_ROTATION_180_M   (0x06 << 20)
> > +#define BIT_DPU_LAY_ROTATION_270_M   (0x07 << 20)
> > +
> > +/* Interrupt control & status bits */
> > +#define BIT_DPU_INT_DONE             BIT(0)
> > +#define BIT_DPU_INT_TE                       BIT(1)
> > +#define BIT_DPU_INT_ERR                      BIT(2)
> > +#define BIT_DPU_INT_UPDATE_DONE              BIT(4)
> > +#define BIT_DPU_INT_VSYNC            BIT(5)
> > +#define BIT_DPU_INT_MMU_VAOR_RD              BIT(16)
> > +#define BIT_DPU_INT_MMU_VAOR_WR              BIT(17)
> > +#define BIT_DPU_INT_MMU_INV_RD               BIT(18)
> > +#define BIT_DPU_INT_MMU_INV_WR               BIT(19)
> > +
> > +/* DPI control bits */
> > +#define BIT_DPU_EDPI_TE_EN           BIT(8)
> > +#define BIT_DPU_EDPI_FROM_EXTERNAL_PAD       BIT(10)
> > +#define BIT_DPU_DPI_HALT_EN          BIT(16)
> > +
> > +static const u32 layer_fmts[] = {
> > +     DRM_FORMAT_XRGB8888,
> > +     DRM_FORMAT_XBGR8888,
> > +     DRM_FORMAT_ARGB8888,
> > +     DRM_FORMAT_ABGR8888,
> > +     DRM_FORMAT_RGBA8888,
> > +     DRM_FORMAT_BGRA8888,
> > +     DRM_FORMAT_RGBX8888,
> > +     DRM_FORMAT_RGB565,
> > +     DRM_FORMAT_BGR565,
> > +     DRM_FORMAT_NV12,
> > +     DRM_FORMAT_NV21,
> > +     DRM_FORMAT_NV16,
> > +     DRM_FORMAT_NV61,
> > +     DRM_FORMAT_YUV420,
> > +     DRM_FORMAT_YVU420,
> > +};
> > +
> > +struct sprd_plane {
> > +     struct drm_plane base;
> > +};
> > +
> > +static u32 check_mmu_isr(struct sprd_dpu *dpu, u32 reg_val)
> > +{
> > +     struct dpu_context *ctx = &dpu->ctx;
> > +     u32 mmu_mask = BIT_DPU_INT_MMU_VAOR_RD |
> > +                     BIT_DPU_INT_MMU_VAOR_WR |
> > +                     BIT_DPU_INT_MMU_INV_RD |
> > +                     BIT_DPU_INT_MMU_INV_WR;
> > +     u32 val = reg_val & mmu_mask;
> > +     int i;
> > +
> > +     if (val) {
> > +             drm_err(dpu->drm, "--- iommu interrupt err: 0x%04x ---\n", val);
> > +
> > +             if (val & BIT_DPU_INT_MMU_INV_RD)
> > +                     drm_err(dpu->drm, "iommu invalid read error, addr: 0x%08x\n",
> > +                             readl(ctx->base + REG_MMU_INV_ADDR_RD));
> > +             if (val & BIT_DPU_INT_MMU_INV_WR)
> > +                     drm_err(dpu->drm, "iommu invalid write error, addr: 0x%08x\n",
> > +                             readl(ctx->base + REG_MMU_INV_ADDR_WR));
> > +             if (val & BIT_DPU_INT_MMU_VAOR_RD)
> > +                     drm_err(dpu->drm, "iommu va out of range read error, addr: 0x%08x\n",
> > +                             readl(ctx->base + REG_MMU_VAOR_ADDR_RD));
> > +             if (val & BIT_DPU_INT_MMU_VAOR_WR)
> > +                     drm_err(dpu->drm, "iommu va out of range write error, addr: 0x%08x\n",
> > +                             readl(ctx->base + REG_MMU_VAOR_ADDR_WR));
> > +
> > +             for (i = 0; i < 8; i++) {
> > +                     reg_val = layer_reg_rd(ctx, REG_LAY_CTRL, i);
> > +                     if (reg_val & 0x1)
> > +                             drm_info(dpu->drm, "layer%d: 0x%x 0x%x 0x%x ctrl: 0x%x\n", i,
> > +                                     layer_reg_rd(ctx, REG_LAY_BASE_ADDR0, i),
> > +                                     layer_reg_rd(ctx, REG_LAY_BASE_ADDR1, i),
> > +                                     layer_reg_rd(ctx, REG_LAY_BASE_ADDR2, i),
> > +                                     layer_reg_rd(ctx, REG_LAY_CTRL, i));
> > +             }
> > +     }
> > +
> > +     return val;
> > +}
>
> We'll still want an Acked-by from one of the IOMMU maintainers. Last
> time they commented they were against that.
>
> > +static int dpu_wait_stop_done(struct sprd_dpu *dpu)
> > +{
> > +     struct dpu_context *ctx = &dpu->ctx;
> > +     int rc;
> > +
> > +     if (ctx->stopped)
> > +             return 0;
> > +
> > +     rc = wait_event_interruptible_timeout(ctx->wait_queue, ctx->evt_stop,
> > +                                            msecs_to_jiffies(500));
> > +     ctx->evt_stop = false;
> > +
> > +     ctx->stopped = true;
> > +
> > +     if (!rc) {
> > +             drm_err(dpu->drm, "dpu wait for stop done time out!\n");
> > +             return -ETIMEDOUT;
> > +     }
> > +
> > +     return 0;
> > +}
> > +
> > +static int dpu_wait_update_done(struct sprd_dpu *dpu)
> > +{
> > +     struct dpu_context *ctx = &dpu->ctx;
> > +     int rc;
> > +
> > +     ctx->evt_update = false;
> > +
> > +     rc = wait_event_interruptible_timeout(ctx->wait_queue, ctx->evt_update,
> > +                                            msecs_to_jiffies(500));
> > +
> > +     if (!rc) {
> > +             drm_err(dpu->drm, "dpu wait for reg update done time out!\n");
> > +             return -ETIMEDOUT;
> > +     }
> > +
> > +     return 0;
> > +}
> > +
> > +static u32 drm_format_to_dpu(struct drm_framebuffer *fb)
> > +{
> > +     u32 format = 0;
> > +
> > +     switch (fb->format->format) {
> > +     case DRM_FORMAT_BGRA8888:
> > +             /* BGRA8888 -> ARGB8888 */
> > +             format |= BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0;
> > +             format |= BIT_DPU_LAY_FORMAT_ARGB8888;
> > +             break;
> > +     case DRM_FORMAT_RGBX8888:
> > +     case DRM_FORMAT_RGBA8888:
> > +             /* RGBA8888 -> ABGR8888 */
> > +             format |= BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0;
> > +             fallthrough;
> > +     case DRM_FORMAT_ABGR8888:
> > +             /* RB switch */
> > +             format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
> > +             fallthrough;
> > +     case DRM_FORMAT_ARGB8888:
> > +             format |= BIT_DPU_LAY_FORMAT_ARGB8888;
> > +             break;
> > +     case DRM_FORMAT_XBGR8888:
> > +             /* RB switch */
> > +             format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
> > +             fallthrough;
> > +     case DRM_FORMAT_XRGB8888:
> > +             format |= BIT_DPU_LAY_FORMAT_ARGB8888;
> > +             break;
> > +     case DRM_FORMAT_BGR565:
> > +             /* RB switch */
> > +             format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
> > +             fallthrough;
> > +     case DRM_FORMAT_RGB565:
> > +             format |= BIT_DPU_LAY_FORMAT_RGB565;
> > +             break;
> > +     case DRM_FORMAT_NV12:
> > +             /* 2-Lane: Yuv420 */
> > +             format |= BIT_DPU_LAY_FORMAT_YUV420_2PLANE;
> > +             /* Y endian */
> > +             format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
> > +             /* UV endian */
> > +             format |= BIT_DPU_LAY_NO_SWITCH;
> > +             break;
> > +     case DRM_FORMAT_NV21:
> > +             /* 2-Lane: Yuv420 */
> > +             format |= BIT_DPU_LAY_FORMAT_YUV420_2PLANE;
> > +             /* Y endian */
> > +             format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
> > +             /* UV endian */
> > +             format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
> > +             break;
> > +     case DRM_FORMAT_NV16:
> > +             /* 2-Lane: Yuv422 */
> > +             format |= BIT_DPU_LAY_FORMAT_YUV422_2PLANE;
> > +             /* Y endian */
> > +             format |= BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0;
> > +             /* UV endian */
> > +             format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
> > +             break;
> > +     case DRM_FORMAT_NV61:
> > +             /* 2-Lane: Yuv422 */
> > +             format |= BIT_DPU_LAY_FORMAT_YUV422_2PLANE;
> > +             /* Y endian */
> > +             format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
> > +             /* UV endian */
> > +             format |= BIT_DPU_LAY_NO_SWITCH;
> > +             break;
> > +     case DRM_FORMAT_YUV420:
> > +             format |= BIT_DPU_LAY_FORMAT_YUV420_3PLANE;
> > +             /* Y endian */
> > +             format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
> > +             /* UV endian */
> > +             format |= BIT_DPU_LAY_NO_SWITCH;
> > +             break;
> > +     case DRM_FORMAT_YVU420:
> > +             format |= BIT_DPU_LAY_FORMAT_YUV420_3PLANE;
> > +             /* Y endian */
> > +             format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
> > +             /* UV endian */
> > +             format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
> > +             break;
> > +     default:
> > +             break;
> > +     }
> > +
> > +     return format;
> > +}
> > +
> > +static u32 drm_rotation_to_dpu(struct drm_plane_state *state)
> > +{
> > +     u32 rotation = 0;
> > +
> > +     switch (state->rotation) {
> > +     default:
> > +     case DRM_MODE_ROTATE_0:
> > +             rotation = BIT_DPU_LAY_ROTATION_0;
> > +             break;
> > +     case DRM_MODE_ROTATE_90:
> > +             rotation = BIT_DPU_LAY_ROTATION_90;
> > +             break;
> > +     case DRM_MODE_ROTATE_180:
> > +             rotation = BIT_DPU_LAY_ROTATION_180;
> > +             break;
> > +     case DRM_MODE_ROTATE_270:
> > +             rotation = BIT_DPU_LAY_ROTATION_270;
> > +             break;
> > +     case DRM_MODE_REFLECT_Y:
> > +             rotation = BIT_DPU_LAY_ROTATION_180_M;
> > +             break;
> > +     case (DRM_MODE_REFLECT_Y | DRM_MODE_ROTATE_90):
> > +             rotation = BIT_DPU_LAY_ROTATION_90_M;
> > +             break;
> > +     case DRM_MODE_REFLECT_X:
> > +             rotation = BIT_DPU_LAY_ROTATION_0_M;
> > +             break;
> > +     case (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90):
> > +             rotation = BIT_DPU_LAY_ROTATION_270_M;
> > +             break;
> > +     }
> > +
> > +     return rotation;
> > +}
> > +
> > +static u32 drm_blend_to_dpu(struct drm_plane_state *state)
> > +{
> > +     u32 blend = 0;
> > +
> > +     switch (state->pixel_blend_mode) {
> > +     case DRM_MODE_BLEND_COVERAGE:
> > +             /* alpha mode select - combo alpha */
> > +             blend |= BIT_DPU_LAY_COMBO_ALPHA;
> > +             /* Normal mode */
> > +             blend |= BIT_DPU_LAY_MODE_BLEND_NORMAL;
> > +             break;
> > +     case DRM_MODE_BLEND_PREMULTI:
> > +             /* alpha mode select - combo alpha */
> > +             blend |= BIT_DPU_LAY_COMBO_ALPHA;
> > +             /* Pre-mult mode */
> > +             blend |= BIT_DPU_LAY_MODE_BLEND_PREMULT;
> > +             break;
> > +     case DRM_MODE_BLEND_PIXEL_NONE:
> > +     default:
> > +             /* don't do blending, maybe RGBX */
> > +             /* alpha mode select - layer alpha */
> > +             blend |= BIT_DPU_LAY_LAYER_ALPHA;
> > +             break;
> > +     }
> > +
> > +     return blend;
> > +}
> > +
> > +static void sprd_dpu_layer(struct sprd_dpu *dpu, struct drm_plane_state *state)
> > +{
> > +     struct dpu_context *ctx = &dpu->ctx;
> > +     struct drm_gem_cma_object *cma_obj;
> > +     struct drm_framebuffer *fb = state->fb;
> > +     u32 addr, size, offset, pitch, blend, format, rotation;
> > +     u32 src_x = state->src_x >> 16;
> > +     u32 src_y = state->src_y >> 16;
> > +     u32 src_w = state->src_w >> 16;
> > +     u32 src_h = state->src_h >> 16;
> > +     u32 dst_x = state->crtc_x;
> > +     u32 dst_y = state->crtc_y;
> > +     u32 alpha = state->alpha;
> > +     u32 index = state->zpos;
> > +     int i;
> > +
> > +     offset = (dst_x & 0xffff) | (dst_y << 16);
> > +     size = (src_w & 0xffff) | (src_h << 16);
> > +
> > +     for (i = 0; i < fb->format->num_planes; i++) {
> > +             cma_obj = drm_fb_cma_get_gem_obj(fb, i);
> > +             addr = cma_obj->paddr + fb->offsets[i];
> > +
> > +             if (i == 0)
> > +                     layer_reg_wr(ctx, REG_LAY_BASE_ADDR0, addr, index);
> > +             else if (i == 1)
> > +                     layer_reg_wr(ctx, REG_LAY_BASE_ADDR1, addr, index);
> > +             else
> > +                     layer_reg_wr(ctx, REG_LAY_BASE_ADDR2, addr, index);
> > +     }
> > +
> > +     if (fb->format->num_planes == 3) {
> > +             /* UV pitch is 1/2 of Y pitch */
> > +             pitch = (fb->pitches[0] / fb->format->cpp[0]) |
> > +                             (fb->pitches[0] / fb->format->cpp[0] << 15);
> > +     } else {
> > +             pitch = fb->pitches[0] / fb->format->cpp[0];
> > +     }
> > +
> > +     layer_reg_wr(ctx, REG_LAY_POS, offset, index);
> > +     layer_reg_wr(ctx, REG_LAY_SIZE, size, index);
> > +     layer_reg_wr(ctx, REG_LAY_CROP_START,
> > +                     src_y << 16 | src_x, index);
> > +     layer_reg_wr(ctx, REG_LAY_ALPHA, alpha, index);
> > +     layer_reg_wr(ctx, REG_LAY_PITCH, pitch, index);
> > +
> > +     format = drm_format_to_dpu(fb);
> > +     blend = drm_blend_to_dpu(state);
> > +     rotation = drm_rotation_to_dpu(state);
> > +
> > +     layer_reg_wr(ctx, REG_LAY_CTRL, BIT_DPU_LAY_EN |
> > +                             format |
> > +                             blend |
> > +                             rotation,
> > +                             index);
> > +}
> > +
> > +static void sprd_dpu_flip(struct sprd_dpu *dpu)
> > +{
> > +     struct dpu_context *ctx = &dpu->ctx;
> > +     u32 reg_val;
> > +
> > +     /*
> > +      * Make sure the dpu is in stop status. DPU has no shadow
> > +      * registers in EDPI mode. So the config registers can only be
> > +      * updated in the rising edge of DPU_RUN bit.
> > +      */
> > +     if (ctx->if_type == SPRD_DPU_IF_EDPI)
> > +             dpu_wait_stop_done(dpu);
> > +
> > +     /* update trigger and wait */
> > +     if (ctx->if_type == SPRD_DPU_IF_DPI) {
> > +             if (!ctx->stopped) {
> > +                     dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_REG_UPDATE);
> > +                     dpu_wait_update_done(dpu);
> > +             }
> > +
> > +             dpu_reg_set(ctx, REG_DPU_INT_EN, BIT_DPU_INT_ERR);
> > +     } else if (ctx->if_type == SPRD_DPU_IF_EDPI) {
> > +             dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_RUN);
> > +
> > +             ctx->stopped = false;
> > +     }
> > +
> > +     /*
> > +      * If the following interrupt was disabled in isr,
> > +      * re-enable it.
> > +      */
> > +     reg_val = BIT_DPU_INT_MMU_VAOR_RD |
> > +               BIT_DPU_INT_MMU_VAOR_WR |
> > +               BIT_DPU_INT_MMU_INV_RD |
> > +               BIT_DPU_INT_MMU_INV_WR;
> > +     dpu_reg_set(ctx, REG_DPU_INT_EN, reg_val);
> > +}
> > +
> > +static void sprd_dpu_init(struct sprd_dpu *dpu)
> > +{
> > +     struct dpu_context *ctx = &dpu->ctx;
> > +     u32 int_mask = 0;
> > +
> > +     writel(0x00, ctx->base + REG_BG_COLOR);
> > +     writel(0x00, ctx->base + REG_MMU_EN);
> > +     writel(0x00, ctx->base + REG_MMU_PPN1);
> > +     writel(0xffff, ctx->base + REG_MMU_RANGE1);
> > +     writel(0x00, ctx->base + REG_MMU_PPN2);
> > +     writel(0xffff, ctx->base + REG_MMU_RANGE2);
> > +     writel(0x1ffff, ctx->base + REG_MMU_VPN_RANGE);
> > +
> > +     if (ctx->if_type == SPRD_DPU_IF_DPI) {
> > +             /* use dpi as interface */
> > +             dpu_reg_clr(ctx, REG_DPU_CFG0, BIT_DPU_IF_EDPI);
> > +             /* disable Halt function for SPRD DSI */
> > +             dpu_reg_clr(ctx, REG_DPI_CTRL, BIT_DPU_DPI_HALT_EN);
> > +             /* select te from external pad */
> > +             dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_EDPI_FROM_EXTERNAL_PAD);
> > +
> > +             /* enable dpu update done INT */
> > +             int_mask |= BIT_DPU_INT_UPDATE_DONE;
> > +             /* enable dpu done INT */
> > +             int_mask |= BIT_DPU_INT_DONE;
> > +             /* enable dpu dpi vsync */
> > +             int_mask |= BIT_DPU_INT_VSYNC;
> > +             /* enable dpu TE INT */
> > +             int_mask |= BIT_DPU_INT_TE;
> > +             /* enable underflow err INT */
> > +             int_mask |= BIT_DPU_INT_ERR;
> > +     } else if (ctx->if_type == SPRD_DPU_IF_EDPI) {
> > +             /* use edpi as interface */
> > +             dpu_reg_set(ctx, REG_DPU_CFG0, BIT_DPU_IF_EDPI);
> > +             /* use external te */
> > +             dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_EDPI_FROM_EXTERNAL_PAD);
> > +             /* enable te */
> > +             dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_EDPI_TE_EN);
> > +
> > +             /* enable stop done INT */
> > +             int_mask |= BIT_DPU_INT_DONE;
> > +             /* enable TE INT */
> > +             int_mask |= BIT_DPU_INT_TE;
> > +     }
> > +
> > +     /* enable iommu va out of range read error INT */
> > +     int_mask |= BIT_DPU_INT_MMU_VAOR_RD;
> > +     /* enable iommu va out of range write error INT */
> > +     int_mask |= BIT_DPU_INT_MMU_VAOR_WR;
> > +     /* enable iommu invalid read error INT */
> > +     int_mask |= BIT_DPU_INT_MMU_INV_RD;
> > +     /* enable iommu invalid write error INT */
> > +     int_mask |= BIT_DPU_INT_MMU_INV_WR;
> > +
> > +     writel(int_mask, ctx->base + REG_DPU_INT_EN);
> > +}
> > +
> > +static void sprd_dpu_fini(struct sprd_dpu *dpu)
> > +{
> > +     struct dpu_context *ctx = &dpu->ctx;
> > +
> > +     writel(0x00, ctx->base + REG_DPU_INT_EN);
> > +     writel(0xff, ctx->base + REG_DPU_INT_CLR);
> > +}
> > +
> > +static void sprd_dpi_init(struct sprd_dpu *dpu)
> > +{
> > +     struct dpu_context *ctx = &dpu->ctx;
> > +     u32 reg_val;
> > +     u32 size;
> > +
> > +     size = (ctx->vm.vactive << 16) | ctx->vm.hactive;
> > +     writel(size, ctx->base + REG_PANEL_SIZE);
> > +     writel(size, ctx->base + REG_BLEND_SIZE);
> > +
> > +     if (ctx->if_type == SPRD_DPU_IF_DPI) {
> > +             /* set dpi timing */
> > +             reg_val = ctx->vm.hsync_len << 0 |
> > +                       ctx->vm.hback_porch << 8 |
> > +                       ctx->vm.hfront_porch << 20;
> > +             writel(reg_val, ctx->base + REG_DPI_H_TIMING);
> > +
> > +             reg_val = ctx->vm.vsync_len << 0 |
> > +                       ctx->vm.vback_porch << 8 |
> > +                       ctx->vm.vfront_porch << 20;
> > +             writel(reg_val, ctx->base + REG_DPI_V_TIMING);
> > +     }
> > +}
> > +
> > +void sprd_dpu_run(struct sprd_dpu *dpu)
> > +{
> > +     struct dpu_context *ctx = &dpu->ctx;
> > +
> > +     dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_RUN);
> > +
> > +     ctx->stopped = false;
> > +}
> > +
> > +void sprd_dpu_stop(struct sprd_dpu *dpu)
> > +{
> > +     struct dpu_context *ctx = &dpu->ctx;
> > +
> > +     if (ctx->if_type == SPRD_DPU_IF_DPI)
> > +             dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_STOP);
> > +
> > +     dpu_wait_stop_done(dpu);
> > +}
> > +
> > +static int sprd_plane_atomic_check(struct drm_plane *plane,
> > +                               struct drm_atomic_state *state)
> > +{
> > +     struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state,
> > +                                                                          plane);
> > +     struct drm_crtc_state *crtc_state;
> > +     u32 fmt;
> > +
> > +     if (!plane_state->fb || !plane_state->crtc)
> > +             return 0;
> > +
> > +     fmt = drm_format_to_dpu(plane_state->fb);
> > +     if (!fmt)
> > +             return -EINVAL;
> > +
> > +     crtc_state = drm_atomic_get_crtc_state(plane_state->state, plane_state->crtc);
> > +     if (IS_ERR(crtc_state))
> > +             return PTR_ERR(crtc_state);
> > +
> > +     return drm_atomic_helper_check_plane_state(plane_state, crtc_state,
> > +                                               DRM_PLANE_HELPER_NO_SCALING,
> > +                                               DRM_PLANE_HELPER_NO_SCALING,
> > +                                               true, true);
> > +}
> > +
> > +static void sprd_plane_atomic_update(struct drm_plane *drm_plane,
> > +                                 struct drm_atomic_state *state)
> > +{
> > +     struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
> > +                                                                        drm_plane);
> > +     struct sprd_dpu *dpu = to_sprd_crtc(new_state->crtc);
> > +
> > +     /* start configure dpu layers */
> > +     sprd_dpu_layer(dpu, new_state);
> > +}
> > +
> > +static void sprd_plane_atomic_disable(struct drm_plane *drm_plane,
> > +                                  struct drm_atomic_state *state)
> > +{
> > +     struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
> > +                                                                        drm_plane);
> > +     struct sprd_dpu *dpu = to_sprd_crtc(old_state->crtc);
> > +
> > +     layer_reg_wr(&dpu->ctx, REG_LAY_CTRL, 0x00, old_state->zpos);
> > +}
> > +
> > +static void sprd_plane_create_properties(struct sprd_plane *plane, int index)
> > +{
> > +     unsigned int supported_modes = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
> > +                                    BIT(DRM_MODE_BLEND_PREMULTI) |
> > +                                    BIT(DRM_MODE_BLEND_COVERAGE);
> > +
> > +     /* create rotation property */
> > +     drm_plane_create_rotation_property(&plane->base,
> > +                                        DRM_MODE_ROTATE_0,
> > +                                        DRM_MODE_ROTATE_MASK |
> > +                                        DRM_MODE_REFLECT_MASK);
> > +
> > +     /* create alpha property */
> > +     drm_plane_create_alpha_property(&plane->base);
> > +
> > +     /* create blend mode property */
> > +     drm_plane_create_blend_mode_property(&plane->base, supported_modes);
> > +
> > +     /* create zpos property */
> > +     drm_plane_create_zpos_immutable_property(&plane->base, index);
> > +}
> > +
> > +static const struct drm_plane_helper_funcs sprd_plane_helper_funcs = {
> > +     .atomic_check = sprd_plane_atomic_check,
> > +     .atomic_update = sprd_plane_atomic_update,
> > +     .atomic_disable = sprd_plane_atomic_disable,
> > +};
> > +
> > +static const struct drm_plane_funcs sprd_plane_funcs = {
> > +     .update_plane = drm_atomic_helper_update_plane,
> > +     .disable_plane  = drm_atomic_helper_disable_plane,
> > +     .destroy = drm_plane_cleanup,
> > +     .reset = drm_atomic_helper_plane_reset,
> > +     .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
> > +     .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
> > +};
> > +
> > +static struct sprd_plane *sprd_planes_init(struct drm_device *drm)
> > +{
> > +     struct sprd_plane *plane, *primary;
> > +     enum drm_plane_type plane_type;
> > +     int i;
> > +
> > +     for (i = 0; i < 6; i++) {
> > +             plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY :
> > +                                     DRM_PLANE_TYPE_OVERLAY;
> > +
> > +             plane = drmm_universal_plane_alloc(drm, struct sprd_plane, base,
> > +                                            1, &sprd_plane_funcs,
> > +                                            layer_fmts, ARRAY_SIZE(layer_fmts),
> > +                                            NULL, plane_type, NULL);
> > +             if (IS_ERR(plane)) {
> > +                     drm_err(drm, "failed to init drm plane: %d\n", i);
> > +                     return plane;
> > +             }
> > +
> > +             drm_plane_helper_add(&plane->base, &sprd_plane_helper_funcs);
> > +
> > +             sprd_plane_create_properties(plane, i);
> > +
> > +             if (i == 0)
> > +                     primary = plane;
> > +     }
> > +
> > +     return primary;
> > +}
> > +
> > +static void sprd_crtc_mode_set_nofb(struct drm_crtc *crtc)
> > +{
> > +     struct sprd_dpu *dpu = to_sprd_crtc(crtc);
> > +     struct drm_display_mode *mode = &crtc->state->adjusted_mode;
> > +
> > +     drm_display_mode_to_videomode(mode, &dpu->ctx.vm);
>
> You don't need to store the videomode into you dpu structure, just pass
> adjusted_mode to sprd_dpi_init.
I get it, thks.
>
> > +     sprd_dpi_init(dpu);
> > +}
> > +
> > +static void sprd_crtc_atomic_enable(struct drm_crtc *crtc,
> > +                                struct drm_atomic_state *state)
> > +{
> > +     struct sprd_dpu *dpu = to_sprd_crtc(crtc);
> > +
> > +     sprd_dpu_init(dpu);
>
> Do you need to do it on both mode_set_nofb and atomic_enable?
mode_set_nofb is sprd_dpi_init, but atomic_enable is sprd_dpu_init,
not the same interface.
>
> Maxime

Re: [PATCH v6 6/6] drm/sprd: add Unisoc's drm mipi dsi&dphy driver

[Kevin Tang]

Maxime Ripard <maxime@cerno.tech> 于2021年9月17日周五 下午11:40写道：
>
> On Fri, Aug 13, 2021 at 10:53:02PM +0800, Kevin Tang wrote:
> > Adds dsi host controller support for the Unisoc's display subsystem.
> > Adds dsi phy support for the Unisoc's display subsystem.
> > Only MIPI DSI Displays supported, DP/TV/HMDI will be support
> > in the feature.
> >
> > v1:
> >   - Remove dphy and dsi graph binding, merge the dphy driver into the dsi.
> >
> > v2:
> >   - Use drm_xxx to replace all DRM_XXX.
> >   - Use kzalloc to replace devm_kzalloc for sprd_dsi structure init.
> >
> > v4:
> >   - Use drmm_helpers to allocate encoder.
> >   - Move allocate encoder and connector to bind function.
> >
> > v5:
> >   - Drop the dsi ip file prefix.
> >   - Fix the checkpatch warnings.
> >   - Add Signed-off-by for dsi&dphy patch.
> >   - Use the mode_flags of mipi_dsi_device to setup crtc DPI and EDPI mode.
> >
> > v6:
> >   - Redesign the way to access the dsi register.
> >   - Reduce the dsi_context member variables.
> > ---
> >  drivers/gpu/drm/sprd/Kconfig         |    1 +
> >  drivers/gpu/drm/sprd/Makefile        |    4 +-
> >  drivers/gpu/drm/sprd/megacores_pll.c |  317 +++++++
> >  drivers/gpu/drm/sprd/megacores_pll.h |  146 +++
> >  drivers/gpu/drm/sprd/sprd_dpu.c      |   17 +
> >  drivers/gpu/drm/sprd/sprd_drm.c      |    1 +
> >  drivers/gpu/drm/sprd/sprd_drm.h      |    1 +
> >  drivers/gpu/drm/sprd/sprd_dsi.c      | 1260 ++++++++++++++++++++++++++
> >  drivers/gpu/drm/sprd/sprd_dsi.h      |   94 ++
> >  9 files changed, 1840 insertions(+), 1 deletion(-)
> >  create mode 100644 drivers/gpu/drm/sprd/megacores_pll.c
> >  create mode 100644 drivers/gpu/drm/sprd/megacores_pll.h
> >  create mode 100644 drivers/gpu/drm/sprd/sprd_dsi.c
> >  create mode 100644 drivers/gpu/drm/sprd/sprd_dsi.h
> >
> > diff --git a/drivers/gpu/drm/sprd/Kconfig b/drivers/gpu/drm/sprd/Kconfig
> > index 37762c333..3edeaeca0 100644
> > --- a/drivers/gpu/drm/sprd/Kconfig
> > +++ b/drivers/gpu/drm/sprd/Kconfig
> > @@ -5,6 +5,7 @@ config DRM_SPRD
> >       select DRM_GEM_CMA_HELPER
> >       select DRM_KMS_CMA_HELPER
> >       select DRM_KMS_HELPER
> > +     select DRM_MIPI_DSI
> >       select VIDEOMODE_HELPERS
> >       help
> >         Choose this option if you have a Unisoc chipset.
> > diff --git a/drivers/gpu/drm/sprd/Makefile b/drivers/gpu/drm/sprd/Makefile
> > index ab12b95e6..73f96c459 100644
> > --- a/drivers/gpu/drm/sprd/Makefile
> > +++ b/drivers/gpu/drm/sprd/Makefile
> > @@ -1,4 +1,6 @@
> >  # SPDX-License-Identifier: GPL-2.0
> >
> >  obj-y := sprd_drm.o \
> > -     sprd_dpu.o
> > +     sprd_dpu.o \
> > +     sprd_dsi.o \
> > +     megacores_pll.o
> > diff --git a/drivers/gpu/drm/sprd/megacores_pll.c b/drivers/gpu/drm/sprd/megacores_pll.c
> > new file mode 100644
> > index 000000000..0dfd3c372
> > --- /dev/null
> > +++ b/drivers/gpu/drm/sprd/megacores_pll.c
> > @@ -0,0 +1,317 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2020 Unisoc Inc.
> > + */
> > +
> > +#include <asm/div64.h>
> > +#include <linux/delay.h>
> > +#include <linux/init.h>
> > +#include <linux/kernel.h>
> > +#include <linux/regmap.h>
> > +#include <linux/string.h>
> > +
> > +#include "megacores_pll.h"
> > +
> > +#define L                                            0
> > +#define H                                            1
> > +#define CLK                                          0
> > +#define DATA                                 1
> > +#define INFINITY                             0xffffffff
> > +#define MIN_OUTPUT_FREQ                      (100)
> > +
> > +#define AVERAGE(a, b) (min(a, b) + abs((b) - (a)) / 2)
> > +
> > +/* sharkle */
> > +#define VCO_BAND_LOW 750
> > +#define VCO_BAND_MID 1100
> > +#define VCO_BAND_HIGH        1500
> > +#define PHY_REF_CLK  26000
> > +
> > +static int dphy_calc_pll_param(struct dphy_pll *pll)
> > +{
> > +     const u32 khz = 1000;
> > +     const u32 mhz = 1000000;
> > +     const unsigned long long factor = 100;
> > +     unsigned long long tmp;
> > +     int i;
> > +
> > +     pll->potential_fvco = pll->freq / khz;
> > +     pll->ref_clk = PHY_REF_CLK / khz;
> > +
> > +     for (i = 0; i < 4; ++i) {
> > +             if (pll->potential_fvco >= VCO_BAND_LOW &&
> > +                     pll->potential_fvco <= VCO_BAND_HIGH) {
> > +                     pll->fvco = pll->potential_fvco;
> > +                     pll->out_sel = BIT(i);
> > +                     break;
> > +             }
> > +             pll->potential_fvco <<= 1;
> > +     }
> > +     if (pll->fvco == 0)
> > +             return -EINVAL;
> > +
> > +     if (pll->fvco >= VCO_BAND_LOW && pll->fvco <= VCO_BAND_MID) {
> > +             /* vco band control */
> > +             pll->vco_band = 0x0;
> > +             /* low pass filter control */
> > +             pll->lpf_sel = 1;
> > +     } else if (pll->fvco > VCO_BAND_MID && pll->fvco <= VCO_BAND_HIGH) {
> > +             pll->vco_band = 0x1;
> > +             pll->lpf_sel = 0;
> > +     } else
> > +             return -EINVAL;
>
> This doesn't follow the kernel coding style, make sure all the issues
> with checkpatch.pl --strict are fixed.
Here I should have used checkpatch to check, maybe the --strict
parameter was not added, i will check it again.
>
> > +
> > +     pll->nint = pll->fvco / pll->ref_clk;
> > +     tmp = pll->fvco * factor * mhz;
> > +     do_div(tmp, pll->ref_clk);
> > +     tmp = tmp - pll->nint * factor * mhz;
> > +     tmp *= BIT(20);
> > +     do_div(tmp, 100000000);
> > +     pll->kint = (u32)tmp;
> > +     pll->refin = 3; /* pre-divider bypass */
> > +     pll->sdm_en = true; /* use fraction N PLL */
> > +     pll->fdk_s = 0x1; /* fraction */
> > +     pll->cp_s = 0x0;
> > +     pll->det_delay = 0x1;
> > +
> > +     return 0;
> > +}
> > +
> > +static void dphy_set_pll_reg(struct dphy_pll *pll, struct regmap *regmap)
> > +{
> > +     struct pll_reg *reg = &pll->reg;
> > +     u8 *val;
> > +     int i;
> > +
> > +     u8 reg_addr[] = {
> > +             0x03, 0x04, 0x06, 0x08, 0x09,
> > +             0x0a, 0x0b, 0x0e, 0x0f
> > +     };
> > +
> > +     reg->_03.bits.prbs_bist = 1;
> > +     reg->_03.bits.en_lp_treot = true;
> > +     reg->_03.bits.lpf_sel = pll->lpf_sel;
> > +     reg->_03.bits.txfifo_bypass = 0;
> > +     reg->_04.bits.div = pll->div;
> > +     reg->_04.bits.masterof8lane = 1;
> > +     reg->_04.bits.cp_s = pll->cp_s;
> > +     reg->_04.bits.fdk_s = pll->fdk_s;
> > +     reg->_06.bits.nint = pll->nint;
> > +     reg->_08.bits.vco_band = pll->vco_band;
> > +     reg->_08.bits.sdm_en = pll->sdm_en;
> > +     reg->_08.bits.refin = pll->refin;
> > +     reg->_09.bits.kint_h = pll->kint >> 12;
> > +     reg->_0a.bits.kint_m = (pll->kint >> 4) & 0xff;
> > +     reg->_0b.bits.out_sel = pll->out_sel;
> > +     reg->_0b.bits.kint_l = pll->kint & 0xf;
> > +     reg->_0e.bits.pll_pu_byp = 0;
> > +     reg->_0e.bits.pll_pu = 0;
> > +     reg->_0e.bits.stopstate_sel = 1;
> > +     reg->_0f.bits.det_delay = pll->det_delay;
> > +
> > +     val = (u8 *)&reg;
> > +
> > +     for (i = 0; i < sizeof(reg_addr); ++i) {
> > +             regmap_write(regmap, reg_addr[i], val[i]);
> > +             DRM_DEBUG("%02x: %02x\n", reg_addr[i], val[i]);
> > +     }
> > +}
>
> It would be great to also convert this part to a pattern without
> structures.
I will try it, but our pll registers, all not have official name from
aisc design owner.
If need to convert it, our pll regiters macro define, it can only be
named as reg_01, reg_02...
>
> > +
> > +int dphy_pll_config(struct dsi_context *ctx)
> > +{
> > +     struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
> > +     struct regmap *regmap = ctx->regmap;
> > +     struct dphy_pll *pll = ctx->pll;
> > +     int ret;
> > +
> > +     pll->freq = dsi->slave->hs_rate;
> > +
> > +     /* FREQ = 26M * (NINT + KINT / 2^20) / out_sel */
> > +     ret = dphy_calc_pll_param(pll);
> > +     if (ret) {
> > +             drm_err(dsi->drm, "failed to calculate dphy pll parameters\n");
> > +             return ret;
> > +     }
> > +     dphy_set_pll_reg(pll, regmap);
> > +
> > +     return 0;
> > +}
> > +
> > +static void dphy_set_timing_reg(struct regmap *regmap, int type, u8 val[])
> > +{
> > +     switch (type) {
> > +     case REQUEST_TIME:
> > +             regmap_write(regmap, 0x31, val[CLK]);
> > +             regmap_write(regmap, 0x41, val[DATA]);
> > +             regmap_write(regmap, 0x51, val[DATA]);
> > +             regmap_write(regmap, 0x61, val[DATA]);
> > +             regmap_write(regmap, 0x71, val[DATA]);
> > +
> > +             regmap_write(regmap, 0x90, val[CLK]);
> > +             regmap_write(regmap, 0xa0, val[DATA]);
> > +             regmap_write(regmap, 0xb0, val[DATA]);
> > +             regmap_write(regmap, 0xc0, val[DATA]);
> > +             regmap_write(regmap, 0xd0, val[DATA]);
> > +             break;
>
> defines and macros would help the readability here
I will try it, but our pll registers, all not have official name from
aisc design owner.
If need to convert it, our pll regiters macro define, it can only be
named as reg_01, reg_02...
>
> > +     case PREPARE_TIME:
> > +             regmap_write(regmap, 0x32, val[CLK]);
> > +             regmap_write(regmap, 0x42, val[DATA]);
> > +             regmap_write(regmap, 0x52, val[DATA]);
> > +             regmap_write(regmap, 0x62, val[DATA]);
> > +             regmap_write(regmap, 0x72, val[DATA]);
> > +
> > +             regmap_write(regmap, 0x91, val[CLK]);
> > +             regmap_write(regmap, 0xa1, val[DATA]);
> > +             regmap_write(regmap, 0xb1, val[DATA]);
> > +             regmap_write(regmap, 0xc1, val[DATA]);
> > +             regmap_write(regmap, 0xd1, val[DATA]);
> > +             break;
> > +     case ZERO_TIME:
> > +             regmap_write(regmap, 0x33, val[CLK]);
> > +             regmap_write(regmap, 0x43, val[DATA]);
> > +             regmap_write(regmap, 0x53, val[DATA]);
> > +             regmap_write(regmap, 0x63, val[DATA]);
> > +             regmap_write(regmap, 0x73, val[DATA]);
> > +
> > +             regmap_write(regmap, 0x92, val[CLK]);
> > +             regmap_write(regmap, 0xa2, val[DATA]);
> > +             regmap_write(regmap, 0xb2, val[DATA]);
> > +             regmap_write(regmap, 0xc2, val[DATA]);
> > +             regmap_write(regmap, 0xd2, val[DATA]);
> > +             break;
> > +     case TRAIL_TIME:
> > +             regmap_write(regmap, 0x34, val[CLK]);
> > +             regmap_write(regmap, 0x44, val[DATA]);
> > +             regmap_write(regmap, 0x54, val[DATA]);
> > +             regmap_write(regmap, 0x64, val[DATA]);
> > +             regmap_write(regmap, 0x74, val[DATA]);
> > +
> > +             regmap_write(regmap, 0x93, val[CLK]);
> > +             regmap_write(regmap, 0xa3, val[DATA]);
> > +             regmap_write(regmap, 0xb3, val[DATA]);
> > +             regmap_write(regmap, 0xc3, val[DATA]);
> > +             regmap_write(regmap, 0xd3, val[DATA]);
> > +             break;
> > +     case EXIT_TIME:
> > +             regmap_write(regmap, 0x36, val[CLK]);
> > +             regmap_write(regmap, 0x46, val[DATA]);
> > +             regmap_write(regmap, 0x56, val[DATA]);
> > +             regmap_write(regmap, 0x66, val[DATA]);
> > +             regmap_write(regmap, 0x76, val[DATA]);
> > +
> > +             regmap_write(regmap, 0x95, val[CLK]);
> > +             regmap_write(regmap, 0xA5, val[DATA]);
> > +             regmap_write(regmap, 0xB5, val[DATA]);
> > +             regmap_write(regmap, 0xc5, val[DATA]);
> > +             regmap_write(regmap, 0xd5, val[DATA]);
> > +             break;
> > +     case CLKPOST_TIME:
> > +             regmap_write(regmap, 0x35, val[CLK]);
> > +             regmap_write(regmap, 0x94, val[CLK]);
> > +             break;
> > +
> > +     /* the following just use default value */
> > +     case SETTLE_TIME:
> > +     case TA_GET:
> > +     case TA_GO:
> > +     case TA_SURE:
> > +             break;
>
> you need to use fallthrough; for all those cases
I get it, thks.

>
> > +     default:
> > +             break;
> > +     }
> > +}
> > +
> > +void dphy_timing_config(struct dsi_context *ctx)
> > +{
> > +     struct regmap *regmap = ctx->regmap;
> > +     struct dphy_pll *pll = ctx->pll;
> > +     const u32 factor = 2;
> > +     const u32 scale = 100;
> > +     u32 t_ui, t_byteck, t_half_byteck;
> > +     u32 range[2], constant;
> > +     u8 val[2];
> > +     u32 tmp = 0;
> > +
> > +     /* t_ui: 1 ui, byteck: 8 ui, half byteck: 4 ui */
> > +     t_ui = 1000 * scale / (pll->freq / 1000);
> > +     t_byteck = t_ui << 3;
> > +     t_half_byteck = t_ui << 2;
> > +     constant = t_ui << 1;
> > +
> > +     /* REQUEST_TIME: HS T-LPX: LP-01
> > +      * For T-LPX, mipi spec defined min value is 50ns,
> > +      * but maybe it shouldn't be too small, because BTA,
> > +      * LP-10, LP-00, LP-01, all of this is related to T-LPX.
> > +      */
> > +     range[L] = 50 * scale;
> > +     range[H] = INFINITY;
> > +     val[CLK] = DIV_ROUND_UP(range[L] * (factor << 1), t_byteck) - 2;
> > +     val[DATA] = val[CLK];
> > +     dphy_set_timing_reg(regmap, REQUEST_TIME, val);
> > +
> > +     /* PREPARE_TIME: HS sequence: LP-00 */
> > +     range[L] = 38 * scale;
> > +     range[H] = 95 * scale;
> > +     tmp = AVERAGE(range[L], range[H]);
> > +     val[CLK] = DIV_ROUND_UP(AVERAGE(range[L], range[H]),
> > +                     t_half_byteck) - 1;
> > +     range[L] = 40 * scale + 4 * t_ui;
> > +     range[H] = 85 * scale + 6 * t_ui;
> > +     tmp |= AVERAGE(range[L], range[H]) << 16;
> > +     val[DATA] = DIV_ROUND_UP(AVERAGE(range[L], range[H]),
> > +                     t_half_byteck) - 1;
> > +     dphy_set_timing_reg(regmap, PREPARE_TIME, val);
> > +
> > +     /* ZERO_TIME: HS-ZERO */
> > +     range[L] = 300 * scale;
> > +     range[H] = INFINITY;
> > +     val[CLK] = DIV_ROUND_UP(range[L] * factor + (tmp & 0xffff)
> > +                     - 525 * t_byteck / 100, t_byteck) - 2;
> > +     range[L] = 145 * scale + 10 * t_ui;
> > +     val[DATA] = DIV_ROUND_UP(range[L] * factor
> > +                     + ((tmp >> 16) & 0xffff) - 525 * t_byteck / 100,
> > +                     t_byteck) - 2;
> > +     dphy_set_timing_reg(regmap, ZERO_TIME, val);
> > +
> > +     /* TRAIL_TIME: HS-TRAIL */
> > +     range[L] = 60 * scale;
> > +     range[H] = INFINITY;
> > +     val[CLK] = DIV_ROUND_UP(range[L] * factor - constant, t_half_byteck);
> > +     range[L] = max(8 * t_ui, 60 * scale + 4 * t_ui);
> > +     val[DATA] = DIV_ROUND_UP(range[L] * 3 / 2 - constant, t_half_byteck) - 2;
> > +     dphy_set_timing_reg(regmap, TRAIL_TIME, val);
> > +
> > +     /* EXIT_TIME: */
> > +     range[L] = 100 * scale;
> > +     range[H] = INFINITY;
> > +     val[CLK] = DIV_ROUND_UP(range[L] * factor, t_byteck) - 2;
> > +     val[DATA] = val[CLK];
> > +     dphy_set_timing_reg(regmap, EXIT_TIME, val);
> > +
> > +     /* CLKPOST_TIME: */
> > +     range[L] = 60 * scale + 52 * t_ui;
> > +     range[H] = INFINITY;
> > +     val[CLK] = DIV_ROUND_UP(range[L] * factor, t_byteck) - 2;
> > +     val[DATA] = val[CLK];
> > +     dphy_set_timing_reg(regmap, CLKPOST_TIME, val);
> > +
> > +     /* SETTLE_TIME:
> > +      * This time is used for receiver. So for transmitter,
> > +      * it can be ignored.
> > +      */
> > +
> > +     /* TA_GO:
> > +      * transmitter drives bridge state(LP-00) before releasing control,
> > +      * reg 0x1f default value: 0x04, which is good.
> > +      */
> > +
> > +     /* TA_SURE:
> > +      * After LP-10 state and before bridge state(LP-00),
> > +      * reg 0x20 default value: 0x01, which is good.
> > +      */
> > +
> > +     /* TA_GET:
> > +      * receiver drives Bridge state(LP-00) before releasing control
> > +      * reg 0x21 default value: 0x03, which is good.
> > +      */
> > +}
> > diff --git a/drivers/gpu/drm/sprd/megacores_pll.h b/drivers/gpu/drm/sprd/megacores_pll.h
> > new file mode 100644
> > index 000000000..bf20aae65
> > --- /dev/null
> > +++ b/drivers/gpu/drm/sprd/megacores_pll.h
> > @@ -0,0 +1,146 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (C) 2020 Unisoc Inc.
> > + */
> > +
> > +#ifndef _MEGACORES_PLL_H_
> > +#define _MEGACORES_PLL_H_
> > +
> > +#include "sprd_dsi.h"
> > +
> > +enum PLL_TIMING {
> > +     NONE,
> > +     REQUEST_TIME,
> > +     PREPARE_TIME,
> > +     SETTLE_TIME,
> > +     ZERO_TIME,
> > +     TRAIL_TIME,
> > +     EXIT_TIME,
> > +     CLKPOST_TIME,
> > +     TA_GET,
> > +     TA_GO,
> > +     TA_SURE,
> > +     TA_WAIT,
> > +};
> > +
> > +struct pll_reg {
> > +     union __reg_03__ {
> > +             struct __03 {
> > +                     u8 prbs_bist: 1;
> > +                     u8 en_lp_treot: 1;
> > +                     u8 lpf_sel: 4;
> > +                     u8 txfifo_bypass: 1;
> > +                     u8 freq_hopping: 1;
> > +             } bits;
> > +             u8 val;
> > +     } _03;
> > +     union __reg_04__ {
> > +             struct __04 {
> > +                     u8 div: 3;
> > +                     u8 masterof8lane: 1;
> > +                     u8 hop_trig: 1;
> > +                     u8 cp_s: 2;
> > +                     u8 fdk_s: 1;
> > +             } bits;
> > +             u8 val;
> > +     } _04;
> > +     union __reg_06__ {
> > +             struct __06 {
> > +                     u8 nint: 7;
> > +                     u8 mod_en: 1;
> > +             } bits;
> > +             u8 val;
> > +     } _06;
> > +     union __reg_07__ {
> > +             struct __07 {
> > +                     u8 kdelta_h: 8;
> > +             } bits;
> > +             u8 val;
> > +     } _07;
> > +     union __reg_08__ {
> > +             struct __08 {
> > +                     u8 vco_band: 1;
> > +                     u8 sdm_en: 1;
> > +                     u8 refin: 2;
> > +                     u8 kdelta_l: 4;
> > +             } bits;
> > +             u8 val;
> > +     } _08;
> > +     union __reg_09__ {
> > +             struct __09 {
> > +                     u8 kint_h: 8;
> > +             } bits;
> > +             u8 val;
> > +     } _09;
> > +     union __reg_0a__ {
> > +             struct __0a {
> > +                     u8 kint_m: 8;
> > +             } bits;
> > +             u8 val;
> > +     } _0a;
> > +     union __reg_0b__ {
> > +             struct __0b {
> > +                     u8 out_sel: 4;
> > +                     u8 kint_l: 4;
> > +             } bits;
> > +             u8 val;
> > +     } _0b;
> > +     union __reg_0c__ {
> > +             struct __0c {
> > +                     u8 kstep_h: 8;
> > +             } bits;
> > +             u8 val;
> > +     } _0c;
> > +     union __reg_0d__ {
> > +             struct __0d {
> > +                     u8 kstep_m: 8;
> > +             } bits;
> > +             u8 val;
> > +     } _0d;
> > +     union __reg_0e__ {
> > +             struct __0e {
> > +                     u8 pll_pu_byp: 1;
> > +                     u8 pll_pu: 1;
> > +                     u8 hsbist_len: 2;
> > +                     u8 stopstate_sel: 1;
> > +                     u8 kstep_l: 3;
> > +             } bits;
> > +             u8 val;
> > +     } _0e;
> > +     union __reg_0f__ {
> > +             struct __0f {
> > +                     u8 det_delay:2;
> > +                     u8 kdelta: 4;
> > +                     u8 ldo0p4:2;
> > +             } bits;
> > +             u8 val;
> > +     } _0f;
> > +};
> > +
> > +struct dphy_pll {
> > +     u8 refin; /* Pre-divider control signal */
> > +     u8 cp_s; /* 00: SDM_EN=1, 10: SDM_EN=0 */
> > +     u8 fdk_s; /* PLL mode control: integer or fraction */
> > +     u8 sdm_en;
> > +     u8 div;
> > +     u8 int_n; /* integer N PLL */
> > +     u32 ref_clk; /* dphy reference clock, unit: MHz */
> > +     u32 freq; /* panel config, unit: KHz */
> > +     u32 fvco;
> > +     u32 potential_fvco;
> > +     u32 nint; /* sigma delta modulator NINT control */
> > +     u32 kint; /* sigma delta modulator KINT control */
> > +     u8 lpf_sel; /* low pass filter control */
> > +     u8 out_sel; /* post divider control */
> > +     u8 vco_band; /* vco range */
> > +     u8 det_delay;
> > +
> > +     struct pll_reg reg;
> > +};
> > +
> > +struct dsi_context;
> > +
> > +int dphy_pll_config(struct dsi_context *ctx);
> > +void dphy_timing_config(struct dsi_context *ctx);
> > +
> > +#endif /* _MEGACORES_PLL_H_ */
> > diff --git a/drivers/gpu/drm/sprd/sprd_dpu.c b/drivers/gpu/drm/sprd/sprd_dpu.c
> > index 448dd4fb6..4e3b30abe 100644
> > --- a/drivers/gpu/drm/sprd/sprd_dpu.c
> > +++ b/drivers/gpu/drm/sprd/sprd_dpu.c
> > @@ -25,6 +25,7 @@
> >
> >  #include "sprd_drm.h"
> >  #include "sprd_dpu.h"
> > +#include "sprd_dsi.h"
> >
> >  /* Global control registers */
> >  #define REG_DPU_CTRL 0x04
> > @@ -686,9 +687,25 @@ static void sprd_crtc_mode_set_nofb(struct drm_crtc *crtc)
> >  {
> >       struct sprd_dpu *dpu = to_sprd_crtc(crtc);
> >       struct drm_display_mode *mode = &crtc->state->adjusted_mode;
> > +     struct drm_encoder *encoder;
> > +     struct mipi_dsi_device *slave;
> > +     struct sprd_dsi *dsi;
> >
> >       drm_display_mode_to_videomode(mode, &dpu->ctx.vm);
> >
> > +     drm_for_each_encoder(encoder, crtc->dev) {
> > +             if (encoder->crtc != crtc)
> > +                     continue;
> > +
> > +             dsi = encoder_to_dsi(encoder);
> > +             slave = dsi->slave;
> > +
> > +             if (slave->mode_flags & MIPI_DSI_MODE_VIDEO)
> > +                     dpu->ctx.if_type = SPRD_DPU_IF_DPI;
> > +             else
> > +                     dpu->ctx.if_type = SPRD_DPU_IF_EDPI;
> > +     }
> > +
>
> You're not using if_type anywhere
Used in sprd_dpu.c as for crtc output type dpi or edpi.
>
> >       sprd_dpi_init(dpu);
> >  }
> >
> > diff --git a/drivers/gpu/drm/sprd/sprd_drm.c b/drivers/gpu/drm/sprd/sprd_drm.c
> > index 549b71278..68cf0933c 100644
> > --- a/drivers/gpu/drm/sprd/sprd_drm.c
> > +++ b/drivers/gpu/drm/sprd/sprd_drm.c
> > @@ -183,6 +183,7 @@ static struct platform_driver sprd_drm_driver = {
> >  static struct platform_driver *sprd_drm_drivers[]  = {
> >       &sprd_drm_driver,
> >       &sprd_dpu_driver,
> > +     &sprd_dsi_driver,
> >  };
> >
> >  static int __init sprd_drm_init(void)
> > diff --git a/drivers/gpu/drm/sprd/sprd_drm.h b/drivers/gpu/drm/sprd/sprd_drm.h
> > index 85d4a8b9f..95d1b972f 100644
> > --- a/drivers/gpu/drm/sprd/sprd_drm.h
> > +++ b/drivers/gpu/drm/sprd/sprd_drm.h
> > @@ -14,5 +14,6 @@ struct sprd_drm {
> >  };
> >
> >  extern struct platform_driver sprd_dpu_driver;
> > +extern struct platform_driver sprd_dsi_driver;
> >
> >  #endif /* _SPRD_DRM_H_ */
> > diff --git a/drivers/gpu/drm/sprd/sprd_dsi.c b/drivers/gpu/drm/sprd/sprd_dsi.c
> > new file mode 100644
> > index 000000000..5ce98fe90
> > --- /dev/null
> > +++ b/drivers/gpu/drm/sprd/sprd_dsi.c
> > @@ -0,0 +1,1260 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2020 Unisoc Inc.
> > + */
> > +
> > +#include <linux/component.h>
> > +#include <linux/module.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/of_graph.h>
> > +#include <video/mipi_display.h>
> > +
> > +#include <drm/drm_atomic_helper.h>
> > +#include <drm/drm_crtc_helper.h>
> > +#include <drm/drm_of.h>
> > +#include <drm/drm_probe_helper.h>
> > +
> > +#include "sprd_drm.h"
> > +#include "sprd_dpu.h"
> > +#include "sprd_dsi.h"
> > +
> > +#define SOFT_RESET 0x04
> > +#define MASK_PROTOCOL_INT 0x0C
> > +#define MASK_INTERNAL_INT 0x14
> > +#define DSI_MODE_CFG 0x18
> > +
> > +#define VIRTUAL_CHANNEL_ID 0x1C
> > +#define GEN_RX_VCID GENMASK(1, 0)
> > +#define VIDEO_PKT_VCID GENMASK(3, 2)
> > +
> > +#define DPI_VIDEO_FORMAT 0x20
> > +#define DPI_VIDEO_MODE_FORMAT GENMASK(5, 0)
> > +#define LOOSELY18_EN BIT(6)
> > +
> > +#define VIDEO_PKT_CONFIG 0x24
> > +#define VIDEO_PKT_SIZE GENMASK(15, 0)
> > +#define VIDEO_LINE_CHUNK_NUM GENMASK(31, 16)
> > +
> > +#define VIDEO_LINE_HBLK_TIME 0x28
> > +#define VIDEO_LINE_HBP_TIME GENMASK(15, 0)
> > +#define VIDEO_LINE_HSA_TIME GENMASK(31, 16)
> > +
> > +#define VIDEO_LINE_TIME 0x2C
> > +
> > +#define VIDEO_VBLK_LINES 0x30
> > +#define VFP_LINES GENMASK(9, 0)
> > +#define VBP_LINES GENMASK(19, 10)
> > +#define VSA_LINES GENMASK(29, 20)
> > +
> > +#define VIDEO_VACTIVE_LINES 0x34
> > +
> > +#define VID_MODE_CFG 0x38
> > +#define VID_MODE_TYPE GENMASK(1, 0)
> > +#define LP_VSA_EN BIT(8)
> > +#define LP_VBP_EN BIT(9)
> > +#define LP_VFP_EN BIT(10)
> > +#define LP_VACT_EN BIT(11)
> > +#define LP_HBP_EN BIT(12)
> > +#define LP_HFP_EN BIT(13)
> > +#define FRAME_BTA_ACK_EN BIT(14)
> > +#define LP_CMD_EN BIT(15)
> > +
> > +#define TIMEOUT_CNT_CLK_CONFIG 0x40
> > +#define HTX_TO_CONFIG 0x44
> > +#define LRX_H_TO_CONFIG 0x48
> > +
> > +#define TX_ESC_CLK_CONFIG 0x5C
> > +
> > +#define CMD_MODE_CFG 0x68
> > +#define TEAR_FX_EN BIT(0)
> > +#define ACK_RQST_EN BIT(1)
> > +#define PPS_TX BIT(5)
> > +#define EXQ_TX BIT(6)
> > +#define CMC_TX BIT(7)
> > +#define GEN_SW_0P_TX BIT(8)
> > +#define GEN_SW_1P_TX BIT(9)
> > +#define GEN_SW_2P_TX BIT(10)
> > +#define GEN_SR_0P_TX BIT(11)
> > +#define GEN_SR_1P_TX BIT(12)
> > +#define GEN_SR_2P_TX BIT(13)
> > +#define GEN_LW_TX BIT(14)
> > +#define DCS_SW_0P_TX BIT(16)
> > +#define DCS_SW_1P_TX BIT(17)
> > +#define DCS_SR_0P_TX BIT(18)
> > +#define DCS_LW_TX BIT(19)
> > +#define MAX_RD_PKT_SIZE BIT(24)
> > +
> > +#define GEN_HDR 0x6C
> > +#define GEN_DT GENMASK(5, 0)
> > +#define GEN_VC GENMASK(7, 6)
> > +#define GEN_WC_LSBYTE GENMASK(15, 8)
> > +#define GEN_WC_MSBYTE GENMASK(23, 16)
> > +
> > +#define GEN_PLD_DATA 0x70
> > +#define GEN_PLD_B1 GENMASK(7, 0)
> > +#define GEN_PLD_B2 GENMASK(15, 8)
> > +#define GEN_PLD_B3 GENMASK(23, 16)
> > +#define GEN_PLD_B4 GENMASK(31, 24)
> > +
> > +#define PHY_CLK_LANE_LP_CTRL 0x74
> > +#define PHY_CLKLANE_TX_REQ_HS BIT(0)
> > +#define AUTO_CLKLANE_CTRL_EN BIT(1)
> > +
> > +#define PHY_INTERFACE_CTRL 0x78
> > +#define RF_PHY_SHUTDOWN BIT(0)
> > +#define RF_PHY_RESET_N BIT(1)
> > +#define RF_PHY_CLK_EN BIT(2)
> > +
> > +#define CMD_MODE_STATUS 0x98
> > +#define GEN_CMD_RDCMD_ONGOING BIT(0)
> > +#define GEN_CMD_RDATA_FIFO_EMPTY BIT(1)
> > +#define GEN_CMD_RDATA_FIFO_FULL BIT(2)
> > +#define GEN_CMD_WDATA_FIFO_EMPTY BIT(3)
> > +#define GEN_CMD_WDATA_FIFO_FULL BIT(4)
> > +#define GEN_CMD_CMD_FIFO_EMPTY BIT(5)
> > +#define GEN_CMD_CMD_FIFO_FULL BIT(6)
> > +#define GEN_CMD_RDCMD_DONE BIT(7)
> > +
> > +#define PHY_STATUS 0x9C
> > +#define PHY_LOCK BIT(1)
> > +
> > +#define PHY_MIN_STOP_TIME 0xA0
> > +#define PHY_LANE_NUM_CONFIG 0xA4
> > +
> > +#define PHY_CLKLANE_TIME_CONFIG 0xA8
> > +#define PHY_CLKLANE_LP_TO_HS_TIME GENMASK(15, 0)
> > +#define PHY_CLKLANE_HS_TO_LP_TIME GENMASK(31, 16)
> > +
> > +#define PHY_DATALANE_TIME_CONFIG 0xAC
> > +#define PHY_DATALANE_LP_TO_HS_TIME GENMASK(15, 0)
> > +#define PHY_DATALANE_HS_TO_LP_TIME GENMASK(31, 16)
> > +
> > +#define MAX_READ_TIME 0xB0
> > +
> > +#define RX_PKT_CHECK_CONFIG 0xB4
> > +#define RX_PKT_ECC_EN BIT(0)
> > +#define RX_PKT_CRC_EN BIT(1)
> > +
> > +#define TA_EN 0xB8
> > +
> > +#define EOTP_EN 0xBC
> > +#define TX_EOTP_EN BIT(0)
> > +#define RX_EOTP_EN BIT(1)
> > +
> > +#define VIDEO_NULLPKT_SIZE 0xC0
> > +#define DCS_WM_PKT_SIZE 0xC4
> > +#define PROTOCOL_INT_CLR 0xC8
> > +#define INTERNAL_INT_CLR 0xCC
> > +
> > +#define VIDEO_SIG_DELAY_CONFIG 0xD0
> > +#define VIDEO_SIG_DELAY GENMASK(23, 0)
> > +#define VIDEO_SIG_DELAY_MODE BIT(24)
> > +
> > +#define PHY_TST_CTRL0 0xF0
> > +#define PHY_TESTCLR BIT(0)
> > +#define PHY_TESTCLK BIT(1)
> > +
> > +#define PHY_TST_CTRL1 0xF4
> > +#define PHY_TESTDIN GENMASK(7, 0)
> > +#define PHY_TESTDOUT GENMASK(15, 8)
> > +#define PHY_TESTEN BIT(16)
> > +
> > +#define host_to_dsi(host) \
> > +     container_of(host, struct sprd_dsi, host)
> > +#define connector_to_dsi(connector) \
> > +     container_of(connector, struct sprd_dsi, connector)
> > +
> > +static inline u32
> > +dsi_reg_rd(struct dsi_context *ctx, u32 offset, u32 mask,
> > +                     u32 shift)
> > +{
> > +     return (readl(ctx->base + offset) & mask) >> shift;
> > +}
> > +
> > +static inline void
> > +dsi_reg_wr(struct dsi_context *ctx, u32 offset, u32 mask,
> > +                     u32 shift, u32 val)
> > +{
> > +     u32 ret;
> > +
> > +     ret = readl(ctx->base + offset);
> > +     ret &= ~mask;
> > +     ret |= (val << shift) & mask;
> > +     writel(ret, ctx->base + offset);
> > +}
> > +
> > +static inline void
> > +dsi_reg_up(struct dsi_context *ctx, u32 offset, u32 mask,
> > +                     u32 val)
> > +{
> > +     u32 ret = readl(ctx->base + offset);
> > +
> > +     writel((ret & ~mask) | (val & mask), ctx->base + offset);
> > +}
> > +
> > +static int regmap_tst_io_write(void *context, u32 reg, u32 val)
> > +{
> > +     struct sprd_dsi *dsi = context;
> > +     struct dsi_context *ctx = &dsi->ctx;
> > +
> > +     if (val > 0xff || reg > 0xff)
> > +             return -EINVAL;
> > +
> > +     drm_dbg(dsi->drm, "reg = 0x%02x, val = 0x%02x\n", reg, val);
> > +
> > +     dsi_reg_up(ctx, PHY_TST_CTRL1, PHY_TESTEN, PHY_TESTEN);
> > +     dsi_reg_wr(ctx, PHY_TST_CTRL1, PHY_TESTDIN, 0, reg);
> > +     dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, PHY_TESTCLK);
> > +     dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, 0);
> > +     dsi_reg_up(ctx, PHY_TST_CTRL1, PHY_TESTEN, 0);
> > +     dsi_reg_wr(ctx, PHY_TST_CTRL1, PHY_TESTDIN, 0, val);
> > +     dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, PHY_TESTCLK);
> > +     dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, 0);
> > +
> > +     return 0;
> > +}
> > +
> > +static int regmap_tst_io_read(void *context, u32 reg, u32 *val)
> > +{
> > +     struct sprd_dsi *dsi = context;
> > +     struct dsi_context *ctx = &dsi->ctx;
> > +     int ret;
> > +
> > +     if (reg > 0xff)
> > +             return -EINVAL;
> > +
> > +     dsi_reg_up(ctx, PHY_TST_CTRL1, PHY_TESTEN, PHY_TESTEN);
> > +     dsi_reg_wr(ctx, PHY_TST_CTRL1, PHY_TESTDIN, 0, reg);
> > +     dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, PHY_TESTCLK);
> > +     dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, 0);
> > +     dsi_reg_up(ctx, PHY_TST_CTRL1, PHY_TESTEN, 0);
> > +
> > +     udelay(1);
> > +
> > +     ret = dsi_reg_rd(ctx, PHY_TST_CTRL1, PHY_TESTDOUT, 8);
> > +     if (ret < 0)
> > +             return ret;
> > +
> > +     *val = ret;
> > +
> > +     drm_dbg(dsi->drm, "reg = 0x%02x, val = 0x%02x\n", reg, *val);
> > +     return 0;
> > +}
> > +
> > +static struct regmap_bus regmap_tst_io = {
> > +     .reg_write = regmap_tst_io_write,
> > +     .reg_read = regmap_tst_io_read,
> > +};
> > +
> > +static const struct regmap_config byte_config = {
> > +     .reg_bits = 8,
> > +     .val_bits = 8,
> > +};
> > +
> > +static int dphy_wait_pll_locked(struct dsi_context *ctx)
> > +{
> > +     struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
> > +     int i;
> > +
> > +     for (i = 0; i < 50000; i++) {
> > +             if (dsi_reg_rd(ctx, PHY_STATUS, PHY_LOCK, 1))
> > +                     return 0;
> > +             udelay(3);
> > +     }
> > +
> > +     drm_err(dsi->drm, "dphy pll can not be locked\n");
> > +     return -ETIMEDOUT;
> > +}
> > +
> > +static int dsi_wait_tx_payload_fifo_empty(struct dsi_context *ctx)
> > +{
> > +     int i;
> > +
> > +     for (i = 0; i < 5000; i++) {
> > +             if (dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_WDATA_FIFO_EMPTY, 3))
> > +                     return 0;
> > +             udelay(1);
> > +     }
> > +
> > +     return -ETIMEDOUT;
> > +}
> > +
> > +static int dsi_wait_tx_cmd_fifo_empty(struct dsi_context *ctx)
> > +{
> > +     int i;
> > +
> > +     for (i = 0; i < 5000; i++) {
> > +             if (dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_CMD_FIFO_EMPTY, 5))
> > +                     return 0;
> > +             udelay(1);
> > +     }
> > +
> > +     return -ETIMEDOUT;
> > +}
> > +
> > +static int dsi_wait_rd_resp_completed(struct dsi_context *ctx)
> > +{
> > +     int i;
> > +
> > +     for (i = 0; i < 10000; i++) {
> > +             if (dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_RDCMD_DONE, 7))
> > +                     return 0;
> > +             udelay(10);
> > +     }
> > +
> > +     return -ETIMEDOUT;
> > +}
> > +
> > +static u16 calc_bytes_per_pixel_x100(int coding)
> > +{
> > +     u16 Bpp_x100;
> > +
> > +     switch (coding) {
> > +     case COLOR_CODE_16BIT_CONFIG1:
> > +     case COLOR_CODE_16BIT_CONFIG2:
> > +     case COLOR_CODE_16BIT_CONFIG3:
> > +             Bpp_x100 = 200;
> > +             break;
> > +     case COLOR_CODE_18BIT_CONFIG1:
> > +     case COLOR_CODE_18BIT_CONFIG2:
> > +             Bpp_x100 = 225;
> > +             break;
> > +     case COLOR_CODE_24BIT:
> > +             Bpp_x100 = 300;
> > +             break;
> > +     case COLOR_CODE_COMPRESSTION:
> > +             Bpp_x100 = 100;
> > +             break;
> > +     case COLOR_CODE_20BIT_YCC422_LOOSELY:
> > +             Bpp_x100 = 250;
> > +             break;
> > +     case COLOR_CODE_24BIT_YCC422:
> > +             Bpp_x100 = 300;
> > +             break;
> > +     case COLOR_CODE_16BIT_YCC422:
> > +             Bpp_x100 = 200;
> > +             break;
> > +     case COLOR_CODE_30BIT:
> > +             Bpp_x100 = 375;
> > +             break;
> > +     case COLOR_CODE_36BIT:
> > +             Bpp_x100 = 450;
> > +             break;
> > +     case COLOR_CODE_12BIT_YCC420:
> > +             Bpp_x100 = 150;
> > +             break;
> > +     default:
> > +             DRM_ERROR("invalid color coding");
> > +             Bpp_x100 = 0;
> > +             break;
> > +     }
> > +
> > +     return Bpp_x100;
> > +}
> > +
> > +static u8 calc_video_size_step(int coding)
> > +{
> > +     u8 video_size_step;
> > +
> > +     switch (coding) {
> > +     case COLOR_CODE_16BIT_CONFIG1:
> > +     case COLOR_CODE_16BIT_CONFIG2:
> > +     case COLOR_CODE_16BIT_CONFIG3:
> > +     case COLOR_CODE_18BIT_CONFIG1:
> > +     case COLOR_CODE_18BIT_CONFIG2:
> > +     case COLOR_CODE_24BIT:
> > +     case COLOR_CODE_COMPRESSTION:
> > +             return video_size_step = 1;
> > +     case COLOR_CODE_20BIT_YCC422_LOOSELY:
> > +     case COLOR_CODE_24BIT_YCC422:
> > +     case COLOR_CODE_16BIT_YCC422:
> > +     case COLOR_CODE_30BIT:
> > +     case COLOR_CODE_36BIT:
> > +     case COLOR_CODE_12BIT_YCC420:
> > +             return video_size_step = 2;
> > +     default:
> > +             DRM_ERROR("invalid color coding");
> > +             return 0;
> > +     }
> > +}
> > +
> > +static u16 round_video_size(int coding, u16 video_size)
> > +{
> > +     switch (coding) {
> > +     case COLOR_CODE_16BIT_YCC422:
> > +     case COLOR_CODE_24BIT_YCC422:
> > +     case COLOR_CODE_20BIT_YCC422_LOOSELY:
> > +     case COLOR_CODE_12BIT_YCC420:
> > +             /* round up active H pixels to a multiple of 2 */
> > +             if ((video_size % 2) != 0)
> > +                     video_size += 1;
> > +             break;
> > +     default:
> > +             break;
> > +     }
> > +
> > +     return video_size;
> > +}
> > +
> > +#define SPRD_MIPI_DSI_FMT_DSC 0xff
> > +static u32 fmt_to_coding(u32 fmt)
> > +{
> > +     switch (fmt) {
> > +     case MIPI_DSI_FMT_RGB565:
> > +             return COLOR_CODE_16BIT_CONFIG1;
> > +     case MIPI_DSI_FMT_RGB666:
> > +     case MIPI_DSI_FMT_RGB666_PACKED:
> > +             return COLOR_CODE_18BIT_CONFIG1;
> > +     case MIPI_DSI_FMT_RGB888:
> > +             return COLOR_CODE_24BIT;
> > +     case SPRD_MIPI_DSI_FMT_DSC:
> > +             return COLOR_CODE_COMPRESSTION;
> > +     default:
> > +             DRM_ERROR("Unsupported format (%d)\n", fmt);
> > +             return COLOR_CODE_24BIT;
> > +     }
> > +}
> > +
> > +#define ns_to_cycle(ns, byte_clk) \
> > +     DIV_ROUND_UP((ns) * (byte_clk), 1000000)
> > +
> > +static void sprd_dsi_init(struct dsi_context *ctx)
> > +{
> > +     struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
> > +     u32 byte_clk = dsi->slave->hs_rate / 8;
> > +     u16 data_hs2lp, data_lp2hs, clk_hs2lp, clk_lp2hs;
> > +     u16 max_rd_time;
> > +     int div;
> > +
> > +     writel(0, ctx->base + SOFT_RESET);
> > +     writel(0xffffffff, ctx->base + MASK_PROTOCOL_INT);
> > +     writel(0xffffffff, ctx->base + MASK_INTERNAL_INT);
> > +     writel(1, ctx->base + DSI_MODE_CFG);
> > +     dsi_reg_up(ctx, EOTP_EN, RX_EOTP_EN, 0);
> > +     dsi_reg_up(ctx, EOTP_EN, TX_EOTP_EN, 0);
> > +     dsi_reg_up(ctx, RX_PKT_CHECK_CONFIG, RX_PKT_ECC_EN, RX_PKT_ECC_EN);
> > +     dsi_reg_up(ctx, RX_PKT_CHECK_CONFIG, RX_PKT_CRC_EN, RX_PKT_CRC_EN);
> > +     writel(1, ctx->base + TA_EN);
> > +     dsi_reg_up(ctx, VIRTUAL_CHANNEL_ID, VIDEO_PKT_VCID, 0);
> > +     dsi_reg_up(ctx, VIRTUAL_CHANNEL_ID, GEN_RX_VCID, 0);
> > +
> > +     div = DIV_ROUND_UP(byte_clk, dsi->slave->lp_rate);
> > +     writel(div, ctx->base + TX_ESC_CLK_CONFIG);
> > +
> > +     max_rd_time = ns_to_cycle(ctx->max_rd_time, byte_clk);
> > +     writel(max_rd_time, ctx->base + MAX_READ_TIME);
> > +
> > +     data_hs2lp = ns_to_cycle(ctx->data_hs2lp, byte_clk);
> > +     data_lp2hs = ns_to_cycle(ctx->data_lp2hs, byte_clk);
> > +     clk_hs2lp = ns_to_cycle(ctx->clk_hs2lp, byte_clk);
> > +     clk_lp2hs = ns_to_cycle(ctx->clk_lp2hs, byte_clk);
> > +     dsi_reg_wr(ctx, PHY_DATALANE_TIME_CONFIG,
> > +             PHY_DATALANE_HS_TO_LP_TIME, 16, data_hs2lp);
> > +     dsi_reg_wr(ctx, PHY_DATALANE_TIME_CONFIG,
> > +             PHY_DATALANE_LP_TO_HS_TIME, 0, data_lp2hs);
> > +     dsi_reg_wr(ctx, PHY_CLKLANE_TIME_CONFIG,
> > +             PHY_CLKLANE_HS_TO_LP_TIME, 16, clk_hs2lp);
> > +     dsi_reg_wr(ctx, PHY_CLKLANE_TIME_CONFIG,
> > +             PHY_CLKLANE_LP_TO_HS_TIME, 0, clk_lp2hs);
> > +
> > +     writel(1, ctx->base + SOFT_RESET);
> > +}
> > +
> > +/*
> > + * Free up resources and shutdown host controller and PHY
> > + */
> > +static void sprd_dsi_fini(struct dsi_context *ctx)
> > +{
> > +     writel(0xffffffff, ctx->base + MASK_PROTOCOL_INT);
> > +     writel(0xffffffff, ctx->base + MASK_INTERNAL_INT);
> > +     writel(0, ctx->base + SOFT_RESET);
> > +}
> > +
> > +/*
> > + * If not in burst mode, it will compute the video and null packet sizes
> > + * according to necessity.
> > + * Configure timers for data lanes and/or clock lane to return to LP when
> > + * bandwidth is not filled by data.
> > + */
> > +static int sprd_dsi_dpi_video(struct dsi_context *ctx)
> > +{
> > +     struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
> > +     struct videomode *vm = &ctx->vm;
> > +     u32 byte_clk = dsi->slave->hs_rate / 8;
> > +     u16 Bpp_x100;
> > +     u16 video_size;
> > +     u32 ratio_x1000;
> > +     u16 null_pkt_size = 0;
> > +     u8 video_size_step;
> > +     u32 hs_to;
> > +     u32 total_bytes;
> > +     u32 bytes_per_chunk;
> > +     u32 chunks = 0;
> > +     u32 bytes_left = 0;
> > +     u32 chunk_overhead;
> > +     const u8 pkt_header = 6;
> > +     u8 coding;
> > +     int div;
> > +     u16 hline;
> > +     u16 byte_cycle;
> > +
> > +     coding = fmt_to_coding(dsi->slave->format);
> > +     video_size = round_video_size(coding, vm->hactive);
> > +     Bpp_x100 = calc_bytes_per_pixel_x100(coding);
> > +     video_size_step = calc_video_size_step(coding);
> > +     ratio_x1000 = byte_clk * 1000 / (vm->pixelclock / 1000);
> > +     hline = vm->hactive + vm->hsync_len + vm->hfront_porch +
> > +             vm->hback_porch;
> > +
> > +     writel(0, ctx->base + SOFT_RESET);
> > +     dsi_reg_wr(ctx, VID_MODE_CFG, FRAME_BTA_ACK_EN, 15, ctx->frame_ack_en);
> > +     dsi_reg_wr(ctx, DPI_VIDEO_FORMAT, DPI_VIDEO_MODE_FORMAT, 0, coding);
> > +     dsi_reg_wr(ctx, VID_MODE_CFG, VID_MODE_TYPE, 0, ctx->burst_mode);
> > +     byte_cycle = 95 * hline * ratio_x1000 / 100000;
> > +     dsi_reg_wr(ctx, VIDEO_SIG_DELAY_CONFIG, VIDEO_SIG_DELAY, 0, byte_cycle);
> > +     byte_cycle = hline * ratio_x1000 / 1000;
> > +     writel(byte_cycle, ctx->base + VIDEO_LINE_TIME);
> > +     byte_cycle = vm->hsync_len * ratio_x1000 / 1000;
> > +     dsi_reg_wr(ctx, VIDEO_LINE_HBLK_TIME, VIDEO_LINE_HSA_TIME, 16, byte_cycle);
> > +     byte_cycle = vm->hback_porch * ratio_x1000 / 1000;
> > +     dsi_reg_wr(ctx, VIDEO_LINE_HBLK_TIME, VIDEO_LINE_HBP_TIME, 0, byte_cycle);
> > +     writel(vm->vactive, ctx->base + VIDEO_VACTIVE_LINES);
> > +     dsi_reg_wr(ctx, VIDEO_VBLK_LINES, VFP_LINES, 0, vm->vfront_porch);
> > +     dsi_reg_wr(ctx, VIDEO_VBLK_LINES, VBP_LINES, 10, vm->vback_porch);
> > +     dsi_reg_wr(ctx, VIDEO_VBLK_LINES, VSA_LINES, 20, vm->vsync_len);
> > +     dsi_reg_up(ctx, VID_MODE_CFG, LP_HBP_EN | LP_HFP_EN | LP_VACT_EN |
> > +                     LP_VFP_EN | LP_VBP_EN | LP_VSA_EN, LP_HBP_EN | LP_HFP_EN |
> > +                     LP_VACT_EN | LP_VFP_EN | LP_VBP_EN | LP_VSA_EN);
> > +
> > +     hs_to = (hline * vm->vactive) + (2 * Bpp_x100) / 100;
> > +     for (div = 0x80; (div < hs_to) && (div > 2); div--) {
> > +             if ((hs_to % div) == 0) {
> > +                     writel(div, ctx->base + TIMEOUT_CNT_CLK_CONFIG);
> > +                     writel(hs_to / div, ctx->base + LRX_H_TO_CONFIG);
> > +                     writel(hs_to / div, ctx->base + HTX_TO_CONFIG);
> > +                     break;
> > +             }
> > +     }
> > +
> > +     if (ctx->burst_mode == VIDEO_BURST_WITH_SYNC_PULSES) {
> > +             dsi_reg_wr(ctx, VIDEO_PKT_CONFIG, VIDEO_PKT_SIZE, 0, video_size);
> > +             writel(0, ctx->base + VIDEO_NULLPKT_SIZE);
> > +             dsi_reg_up(ctx, VIDEO_PKT_CONFIG, VIDEO_LINE_CHUNK_NUM, 0);
> > +     } else {
> > +             /* non burst transmission */
> > +             null_pkt_size = 0;
> > +
> > +             /* bytes to be sent - first as one chunk */
> > +             bytes_per_chunk = vm->hactive * Bpp_x100 / 100 + pkt_header;
> > +
> > +             /* hline total bytes from the DPI interface */
> > +             total_bytes = (vm->hactive + vm->hfront_porch) *
> > +                             ratio_x1000 / dsi->slave->lanes / 1000;
> > +
> > +             /* check if the pixels actually fit on the DSI link */
> > +             if (total_bytes < bytes_per_chunk) {
> > +                     drm_err(dsi->drm, "current resolution can not be set\n");
> > +                     return -EINVAL;
> > +             }
> > +
> > +             chunk_overhead = total_bytes - bytes_per_chunk;
> > +
> > +             /* overhead higher than 1 -> enable multi packets */
> > +             if (chunk_overhead > 1) {
> > +
> > +                     /* multi packets */
> > +                     for (video_size = video_size_step;
> > +                          video_size < vm->hactive;
> > +                          video_size += video_size_step) {
> > +
> > +                             if (vm->hactive * 1000 / video_size % 1000)
> > +                                     continue;
> > +
> > +                             chunks = vm->hactive / video_size;
> > +                             bytes_per_chunk = Bpp_x100 * video_size / 100
> > +                                               + pkt_header;
> > +                             if (total_bytes >= (bytes_per_chunk * chunks)) {
> > +                                     bytes_left = total_bytes -
> > +                                                  bytes_per_chunk * chunks;
> > +                                     break;
> > +                             }
> > +                     }
> > +
> > +                     /* prevent overflow (unsigned - unsigned) */
> > +                     if (bytes_left > (pkt_header * chunks)) {
> > +                             null_pkt_size = (bytes_left -
> > +                                             pkt_header * chunks) / chunks;
> > +                             /* avoid register overflow */
> > +                             if (null_pkt_size > 1023)
> > +                                     null_pkt_size = 1023;
> > +                     }
> > +
> > +             } else {
> > +
> > +                     /* single packet */
> > +                     chunks = 1;
> > +
> > +                     /* must be a multiple of 4 except 18 loosely */
> > +                     for (video_size = vm->hactive;
> > +                         (video_size % video_size_step) != 0;
> > +                          video_size++)
> > +                             ;
> > +             }
> > +
> > +             dsi_reg_wr(ctx, VIDEO_PKT_CONFIG, VIDEO_PKT_SIZE, 0, video_size);
> > +             writel(null_pkt_size, ctx->base + VIDEO_NULLPKT_SIZE);
> > +             dsi_reg_wr(ctx, VIDEO_PKT_CONFIG, VIDEO_LINE_CHUNK_NUM, 16, chunks);
> > +     }
> > +
> > +     writel(ctx->int0_mask, ctx->base + MASK_PROTOCOL_INT);
> > +     writel(ctx->int1_mask, ctx->base + MASK_INTERNAL_INT);
> > +     writel(1, ctx->base + SOFT_RESET);
> > +
> > +     return 0;
> > +}
> > +
> > +static void sprd_dsi_edpi_video(struct dsi_context *ctx)
> > +{
> > +     struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
> > +     const u32 fifo_depth = 1096;
> > +     const u32 word_length = 4;
> > +     u32 hactive = ctx->vm.hactive;
> > +     u32 Bpp_x100;
> > +     u32 max_fifo_len;
> > +     u8 coding;
> > +
> > +     coding = fmt_to_coding(dsi->slave->format);
> > +     Bpp_x100 = calc_bytes_per_pixel_x100(coding);
> > +     max_fifo_len = word_length * fifo_depth * 100 / Bpp_x100;
> > +
> > +     writel(0, ctx->base + SOFT_RESET);
> > +     dsi_reg_wr(ctx, DPI_VIDEO_FORMAT, DPI_VIDEO_MODE_FORMAT, 0, coding);
> > +     dsi_reg_wr(ctx, CMD_MODE_CFG, TEAR_FX_EN, 0, ctx->te_ack_en);
> > +
> > +     if (max_fifo_len > hactive)
> > +             writel(hactive, ctx->base + DCS_WM_PKT_SIZE);
> > +     else
> > +             writel(max_fifo_len, ctx->base + DCS_WM_PKT_SIZE);
> > +
> > +     writel(ctx->int0_mask, ctx->base + MASK_PROTOCOL_INT);
> > +     writel(ctx->int1_mask, ctx->base + MASK_INTERNAL_INT);
> > +     writel(1, ctx->base + SOFT_RESET);
> > +}
> > +
> > +/*
> > + * Send a packet on the generic interface,
> > + * this function has an active delay to wait for the buffer to clear.
> > + * The delay is limited to:
> > + * (param_length / 4) x DSIH_FIFO_ACTIVE_WAIT x register access time
> > + * the controller restricts the sending of.
> > + *
> > + * This function will not be able to send Null and Blanking packets due to
> > + * controller restriction
> > + */
> > +static int sprd_dsi_wr_pkt(struct dsi_context *ctx, u8 vc, u8 type,
> > +                     const u8 *param, u16 len)
> > +{
> > +     struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
> > +     u8 wc_lsbyte, wc_msbyte;
> > +     u32 payload;
> > +     int i, j, ret;
> > +
> > +     if (vc > 3)
> > +             return -EINVAL;
> > +
> > +
> > +     /* 1st: for long packet, must config payload first */
> > +     ret = dsi_wait_tx_payload_fifo_empty(ctx);
> > +     if (ret) {
> > +             drm_err(dsi->drm, "tx payload fifo is not empty\n");
> > +             return ret;
> > +     }
> > +
> > +     if (len > 2) {
> > +             for (i = 0, j = 0; i < len; i += j) {
> > +                     payload = 0;
> > +                     for (j = 0; (j < 4) && ((j + i) < (len)); j++)
> > +                             payload |= param[i + j] << (j * 8);
> > +
> > +                     writel(payload, ctx->base + GEN_PLD_DATA);
> > +             }
> > +             wc_lsbyte = len & 0xff;
> > +             wc_msbyte = len >> 8;
> > +     } else {
> > +             wc_lsbyte = (len > 0) ? param[0] : 0;
> > +             wc_msbyte = (len > 1) ? param[1] : 0;
> > +     }
> > +
> > +     /* 2nd: then set packet header */
> > +     ret = dsi_wait_tx_cmd_fifo_empty(ctx);
> > +     if (ret) {
> > +             drm_err(dsi->drm, "tx cmd fifo is not empty\n");
> > +             return ret;
> > +     }
> > +
> > +     writel(type | (vc << 6) | (wc_lsbyte << 8) | (wc_msbyte << 16),
> > +                     ctx->base + GEN_HDR);
> > +
> > +     return 0;
> > +}
> > +
> > +/*
> > + * Send READ packet to peripheral using the generic interface,
> > + * this will force command mode and stop video mode (because of BTA).
> > + *
> > + * This function has an active delay to wait for the buffer to clear,
> > + * the delay is limited to 2 x DSIH_FIFO_ACTIVE_WAIT
> > + * (waiting for command buffer, and waiting for receiving)
> > + * @note this function will enable BTA
> > + */
> > +static int sprd_dsi_rd_pkt(struct dsi_context *ctx, u8 vc, u8 type,
> > +                     u8 msb_byte, u8 lsb_byte,
> > +                     u8 *buffer, u8 bytes_to_read)
> > +{
> > +     struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
> > +     int i, ret;
> > +     int count = 0;
> > +     u32 temp;
> > +
> > +     if (vc > 3)
> > +             return -EINVAL;
> > +
> > +     /* 1st: send read command to peripheral */
> > +     ret = dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_CMD_FIFO_EMPTY, 5);
> > +     if (!ret)
> > +             return -EIO;
> > +
> > +     writel(type | (vc << 6) | (lsb_byte << 8) | (msb_byte << 16),
> > +                     ctx->base + GEN_HDR);
> > +
> > +     /* 2nd: wait peripheral response completed */
> > +     ret = dsi_wait_rd_resp_completed(ctx);
> > +     if (ret) {
> > +             drm_err(dsi->drm, "wait read response time out\n");
> > +             return ret;
> > +     }
> > +
> > +     /* 3rd: get data from rx payload fifo */
> > +     ret = dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_RDATA_FIFO_EMPTY, 1);
> > +     if (ret) {
> > +             drm_err(dsi->drm, "rx payload fifo empty\n");
> > +             return -EIO;
> > +     }
> > +
> > +     for (i = 0; i < 100; i++) {
> > +             temp = readl(ctx->base + GEN_PLD_DATA);
> > +
> > +             if (count < bytes_to_read)
> > +                     buffer[count++] = temp & 0xff;
> > +             if (count < bytes_to_read)
> > +                     buffer[count++] = (temp >> 8) & 0xff;
> > +             if (count < bytes_to_read)
> > +                     buffer[count++] = (temp >> 16) & 0xff;
> > +             if (count < bytes_to_read)
> > +                     buffer[count++] = (temp >> 24) & 0xff;
> > +
> > +             ret = dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_RDATA_FIFO_EMPTY, 1);
> > +             if (ret)
> > +                     return count;
> > +     }
> > +
> > +     return 0;
> > +}
> > +
> > +static void sprd_dsi_set_work_mode(struct dsi_context *ctx, u8 mode)
> > +{
> > +     if (mode == DSI_MODE_CMD)
> > +             writel(1, ctx->base + DSI_MODE_CFG);
> > +     else
> > +             writel(0, ctx->base + DSI_MODE_CFG);
> > +}
> > +
> > +static void sprd_dsi_lp_cmd_enable(struct dsi_context *ctx)
> > +{
> > +     if (readl(ctx->base + DSI_MODE_CFG))
> > +             dsi_reg_up(ctx, CMD_MODE_CFG, GEN_SW_0P_TX | GEN_SW_1P_TX |
> > +                     GEN_SW_2P_TX | GEN_SR_0P_TX | GEN_SR_1P_TX | GEN_SR_2P_TX |
> > +                     GEN_LW_TX | DCS_SW_0P_TX | DCS_SW_1P_TX | DCS_SR_0P_TX |
> > +                     DCS_LW_TX | MAX_RD_PKT_SIZE, GEN_SW_0P_TX | GEN_SW_1P_TX |
> > +                     GEN_SW_2P_TX | GEN_SR_0P_TX | GEN_SR_1P_TX | GEN_SR_2P_TX |
> > +                     GEN_LW_TX | DCS_SW_0P_TX | DCS_SW_1P_TX | DCS_SR_0P_TX |
> > +                     DCS_LW_TX | MAX_RD_PKT_SIZE);
> > +     else
> > +             dsi_reg_up(ctx, VID_MODE_CFG, LP_CMD_EN, LP_CMD_EN);
> > +}
> > +
> > +static void sprd_dsi_state_reset(struct dsi_context *ctx)
> > +{
> > +     writel(0, ctx->base + SOFT_RESET);
> > +     udelay(100);
> > +     writel(1, ctx->base + SOFT_RESET);
> > +}
> > +
> > +static int sprd_dphy_init(struct dsi_context *ctx)
> > +{
> > +     struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
> > +     int ret;
> > +
> > +     dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_RESET_N, 0);
> > +     dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_SHUTDOWN, 0);
> > +     dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_CLK_EN, 0);
> > +
> > +     dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLR, 0);
> > +     dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLR, PHY_TESTCLR);
> > +     dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLR, 0);
> > +
> > +     dphy_pll_config(ctx);
> > +     dphy_timing_config(ctx);
> > +
> > +     dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_SHUTDOWN, RF_PHY_SHUTDOWN);
> > +     dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_RESET_N, RF_PHY_RESET_N);
> > +     writel(0x1C, ctx->base + PHY_MIN_STOP_TIME);
> > +     dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_CLK_EN, RF_PHY_CLK_EN);
> > +     writel(dsi->slave->lanes - 1, ctx->base + PHY_LANE_NUM_CONFIG);
> > +
> > +     ret = dphy_wait_pll_locked(ctx);
> > +     if (ret) {
> > +             drm_err(dsi->drm, "dphy initial failed\n");
> > +             return ret;
> > +     }
> > +
> > +     return 0;
> > +}
> > +
> > +static void sprd_dphy_fini(struct dsi_context *ctx)
> > +{
> > +     dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_RESET_N, 0);
> > +     dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_SHUTDOWN, 0);
> > +     dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_RESET_N, RF_PHY_RESET_N);
> > +}
> > +
> > +static void sprd_dsi_encoder_enable(struct drm_encoder *encoder)
> > +{
> > +     struct sprd_dsi *dsi = encoder_to_dsi(encoder);
> > +     struct sprd_dpu *dpu = to_sprd_crtc(encoder->crtc);
> > +     struct dsi_context *ctx = &dsi->ctx;
> > +
> > +     if (ctx->enabled) {
> > +             drm_warn(dsi->drm, "dsi is initialized\n");
> > +             return;
> > +     }
> > +
> > +     sprd_dsi_init(ctx);
> > +     if (ctx->work_mode == DSI_MODE_VIDEO)
> > +             sprd_dsi_dpi_video(ctx);
> > +     else
> > +             sprd_dsi_edpi_video(ctx);
> > +
> > +     sprd_dphy_init(ctx);
> > +
> > +     sprd_dsi_lp_cmd_enable(ctx);
> > +
> > +     if (dsi->panel) {
> > +             drm_panel_prepare(dsi->panel);
> > +             drm_panel_enable(dsi->panel);
> > +     }
>
> Please use the new devm_drm_of_get_bridge helper here, and use the
> bridge API instead.
We use drm_panel_init and drm_panel_add API to add panel, so here is a
panel device, not a bridge.
>
> > +     sprd_dsi_set_work_mode(ctx, ctx->work_mode);
> > +     sprd_dsi_state_reset(ctx);
> > +
> > +     if (dsi->slave->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
> > +             dsi_reg_up(ctx, PHY_CLK_LANE_LP_CTRL, AUTO_CLKLANE_CTRL_EN,
> > +                             AUTO_CLKLANE_CTRL_EN);
> > +     else {
> > +             dsi_reg_up(ctx, PHY_CLK_LANE_LP_CTRL, RF_PHY_CLK_EN, RF_PHY_CLK_EN);
> > +             dsi_reg_up(ctx, PHY_CLK_LANE_LP_CTRL, PHY_CLKLANE_TX_REQ_HS,
> > +                             PHY_CLKLANE_TX_REQ_HS);
> > +             dphy_wait_pll_locked(ctx);
> > +     }
> > +
> > +     sprd_dpu_run(dpu);
> > +
> > +     ctx->enabled = true;
> > +}
> > +
> > +static void sprd_dsi_encoder_disable(struct drm_encoder *encoder)
> > +{
> > +     struct sprd_dsi *dsi = encoder_to_dsi(encoder);
> > +     struct sprd_dpu *dpu = to_sprd_crtc(encoder->crtc);
> > +     struct dsi_context *ctx = &dsi->ctx;
> > +
> > +     if (!ctx->enabled) {
> > +             drm_warn(dsi->drm, "dsi isn't initialized\n");
> > +             return;
> > +     }
> > +
> > +     sprd_dpu_stop(dpu);
> > +     sprd_dsi_set_work_mode(ctx, DSI_MODE_CMD);
> > +     sprd_dsi_lp_cmd_enable(ctx);
> > +
> > +     if (dsi->panel) {
> > +             drm_panel_disable(dsi->panel);
> > +             drm_panel_unprepare(dsi->panel);
> > +     }
> > +
> > +     sprd_dphy_fini(ctx);
> > +     sprd_dsi_fini(ctx);
> > +
> > +     ctx->enabled = false;
> > +}
> > +
> > +static void sprd_dsi_encoder_mode_set(struct drm_encoder *encoder,
> > +                              struct drm_display_mode *mode,
> > +                              struct drm_display_mode *adj_mode)
> > +{
> > +     struct sprd_dsi *dsi = encoder_to_dsi(encoder);
> > +
> > +     drm_dbg(dsi->drm, "%s() set mode: %s\n", __func__, dsi->mode->name);
> > +}
>
> You don't need that function?
No need for now. need to delete it?
>
> > +static int sprd_dsi_encoder_atomic_check(struct drm_encoder *encoder,
> > +                                 struct drm_crtc_state *crtc_state,
> > +                                 struct drm_connector_state *conn_state)
> > +{
> > +     return 0;
> > +}
>
> Ditto
No need for now. need to delete it?
>
> > +static const struct drm_encoder_helper_funcs sprd_encoder_helper_funcs = {
> > +     .atomic_check   = sprd_dsi_encoder_atomic_check,
> > +     .mode_set       = sprd_dsi_encoder_mode_set,
> > +     .enable         = sprd_dsi_encoder_enable,
> > +     .disable        = sprd_dsi_encoder_disable
> > +};
> > +
> > +static const struct drm_encoder_funcs sprd_encoder_funcs = {
> > +     .destroy = drm_encoder_cleanup,
> > +};
> > +
> > +static struct sprd_dsi *sprd_dsi_encoder_init(struct drm_device *drm,
> > +                            struct device *dev)
> > +{
> > +     struct sprd_dsi *dsi;
> > +     u32 crtc_mask;
> > +
> > +     crtc_mask = drm_of_find_possible_crtcs(drm, dev->of_node);
> > +     if (!crtc_mask) {
> > +             drm_err(drm, "failed to find crtc mask\n");
> > +             return ERR_PTR(-EINVAL);
> > +     }
> > +
> > +     drm_dbg(drm, "find possible crtcs: 0x%08x\n", crtc_mask);
> > +
> > +     dsi = drmm_encoder_alloc(drm, struct sprd_dsi, encoder,
> > +                            &sprd_encoder_funcs, DRM_MODE_ENCODER_DSI, NULL);
> > +     if (IS_ERR(dsi)) {
> > +             drm_err(drm, "failed to init dsi encoder.\n");
> > +             return dsi;
> > +     }
> > +
> > +     dsi->encoder.possible_crtcs = crtc_mask;
> > +     drm_encoder_helper_add(&dsi->encoder, &sprd_encoder_helper_funcs);
> > +
> > +     return dsi;
> > +}
> > +
> > +static int sprd_dsi_find_panel(struct sprd_dsi *dsi)
> > +{
> > +     struct device *dev = dsi->host.dev;
> > +     struct device_node *child, *lcds_node;
> > +     struct drm_panel *panel;
> > +
> > +     /* search /lcds child node first */
> > +     lcds_node = of_find_node_by_path("/lcds");
> > +     for_each_child_of_node(lcds_node, child) {
> > +             panel = of_drm_find_panel(child);
> > +             if (!IS_ERR(panel)) {
> > +                     dsi->panel = panel;
> > +                     return 0;
> > +             }
> > +     }
> > +
> > +     /*
> > +      * If /lcds child node search failed, we search
> > +      * the child of dsi host node.
> > +      */
> > +     for_each_child_of_node(dev->of_node, child) {
> > +             panel = of_drm_find_panel(child);
> > +             if (!IS_ERR(panel)) {
> > +                     dsi->panel = panel;
> > +                     return 0;
> > +             }
> > +     }
> > +
> > +     drm_err(dsi->drm, "of_drm_find_panel() failed\n");
> > +     return -ENODEV;
> > +}
>
> Just use devm_drm_of_get_bridge there
We use drm_panel_init and drm_panel_add API to add panel, so here is a
panel device, not a bridge.
>
> > +static int sprd_dsi_host_attach(struct mipi_dsi_host *host,
> > +                        struct mipi_dsi_device *slave)
> > +{
> > +     struct sprd_dsi *dsi = host_to_dsi(host);
> > +     struct dsi_context *ctx = &dsi->ctx;
> > +     int ret;
> > +
> > +     dsi->slave = slave;
> > +
> > +     if (slave->mode_flags & MIPI_DSI_MODE_VIDEO)
> > +             ctx->work_mode = DSI_MODE_VIDEO;
> > +     else
> > +             ctx->work_mode = DSI_MODE_CMD;
> > +
> > +     if (slave->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
> > +             ctx->burst_mode = VIDEO_BURST_WITH_SYNC_PULSES;
> > +     else if (slave->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
> > +             ctx->burst_mode = VIDEO_NON_BURST_WITH_SYNC_PULSES;
> > +     else
> > +             ctx->burst_mode = VIDEO_NON_BURST_WITH_SYNC_EVENTS;
> > +
> > +     ret = sprd_dsi_find_panel(dsi);
> > +     if (ret)
> > +             return ret;
> > +
> > +     return 0;
> > +}
> > +
> > +static int sprd_dsi_host_detach(struct mipi_dsi_host *host,
> > +                        struct mipi_dsi_device *slave)
> > +{
> > +     /* do nothing */
> > +     return 0;
> > +}
> > +
> > +static ssize_t sprd_dsi_host_transfer(struct mipi_dsi_host *host,
> > +                             const struct mipi_dsi_msg *msg)
> > +{
> > +     struct sprd_dsi *dsi = host_to_dsi(host);
> > +     const u8 *tx_buf = msg->tx_buf;
> > +
> > +     if (msg->rx_buf && msg->rx_len) {
> > +             u8 lsb = (msg->tx_len > 0) ? tx_buf[0] : 0;
> > +             u8 msb = (msg->tx_len > 1) ? tx_buf[1] : 0;
> > +
> > +             return sprd_dsi_rd_pkt(&dsi->ctx, msg->channel, msg->type,
> > +                             msb, lsb, msg->rx_buf, msg->rx_len);
> > +     }
> > +
> > +     if (msg->tx_buf && msg->tx_len)
> > +             return sprd_dsi_wr_pkt(&dsi->ctx, msg->channel, msg->type,
> > +                                     tx_buf, msg->tx_len);
> > +
> > +     return 0;
> > +}
> > +
> > +static const struct mipi_dsi_host_ops sprd_dsi_host_ops = {
> > +     .attach = sprd_dsi_host_attach,
> > +     .detach = sprd_dsi_host_detach,
> > +     .transfer = sprd_dsi_host_transfer,
> > +};
> > +
> > +static int sprd_dsi_host_init(struct sprd_dsi *dsi, struct device *dev)
> > +{
> > +     int ret;
> > +
> > +     dsi->host.dev = dev;
> > +     dsi->host.ops = &sprd_dsi_host_ops;
> > +
> > +     ret = mipi_dsi_host_register(&dsi->host);
> > +     if (ret)
> > +             drm_err(dsi->drm, "failed to register dsi host\n");
> > +
> > +     return ret;
> > +}
> > +
> > +static int sprd_dsi_connector_get_modes(struct drm_connector *connector)
> > +{
> > +     struct sprd_dsi *dsi = connector_to_dsi(connector);
> > +
> > +     return drm_panel_get_modes(dsi->panel, connector);
> > +}
> > +
> > +static enum drm_mode_status
> > +sprd_dsi_connector_mode_valid(struct drm_connector *connector,
> > +                      struct drm_display_mode *mode)
> > +{
> > +     struct sprd_dsi *dsi = connector_to_dsi(connector);
> > +
> > +     drm_dbg(dsi->drm, "%s() mode: "DRM_MODE_FMT"\n", __func__, DRM_MODE_ARG(mode));
> > +
> > +     if (mode->type & DRM_MODE_TYPE_PREFERRED) {
> > +             dsi->mode = mode;
> > +             drm_display_mode_to_videomode(dsi->mode, &dsi->ctx.vm);
> > +     }
>
> I already told you this, but you shouldn't modify your state in
> mode_valid, and certainly not based on whether it's the preferred mode
> or not.
Sorry, I have modified the CRTC driver, and the encoder driver is
missing, i will fix it, thks.
>
> > +     return MODE_OK;
> > +}
> > +
> > +static struct drm_encoder *
> > +sprd_dsi_connector_best_encoder(struct drm_connector *connector)
> > +{
> > +     struct sprd_dsi *dsi = connector_to_dsi(connector);
> > +
> > +     return &dsi->encoder;
> > +}
> > +
> > +static struct drm_connector_helper_funcs sprd_dsi_connector_helper_funcs = {
> > +     .get_modes = sprd_dsi_connector_get_modes,
> > +     .mode_valid = sprd_dsi_connector_mode_valid,
> > +     .best_encoder = sprd_dsi_connector_best_encoder,
> > +};
> > +
> > +static enum drm_connector_status
> > +sprd_dsi_connector_detect(struct drm_connector *connector, bool force)
> > +{
> > +     struct sprd_dsi *dsi = connector_to_dsi(connector);
> > +
> > +     if (dsi->panel) {
> > +             drm_panel_add(dsi->panel);
> > +             return connector_status_connected;
> > +     }
> > +
> > +     return connector_status_disconnected;
> > +}
> > +
> > +static void sprd_dsi_connector_destroy(struct drm_connector *connector)
> > +{
> > +     drm_connector_unregister(connector);
> > +     drm_connector_cleanup(connector);
> > +}
> > +
> > +static const struct drm_connector_funcs sprd_dsi_atomic_connector_funcs = {
> > +     .fill_modes = drm_helper_probe_single_connector_modes,
> > +     .detect = sprd_dsi_connector_detect,
> > +     .destroy = sprd_dsi_connector_destroy,
> > +     .reset = drm_atomic_helper_connector_reset,
> > +     .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
> > +     .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> > +};
> > +
> > +static int sprd_dsi_connector_init(struct drm_device *drm, struct sprd_dsi *dsi)
> > +{
> > +     struct drm_encoder *encoder = &dsi->encoder;
> > +     struct drm_connector *connector = &dsi->connector;
> > +     int ret;
> > +
> > +     connector->polled = DRM_CONNECTOR_POLL_HPD;
> > +
> > +     ret = drm_connector_init(drm, connector,
> > +                              &sprd_dsi_atomic_connector_funcs,
> > +                              DRM_MODE_CONNECTOR_DSI);
> > +     if (ret) {
> > +             drm_err(drm, "drm_connector_init() failed\n");
> > +             return ret;
> > +     }
> > +
> > +     drm_connector_helper_add(connector,
> > +                              &sprd_dsi_connector_helper_funcs);
> > +
> > +     drm_connector_attach_encoder(connector, encoder);
> > +
> > +     return 0;
> > +}
> > +
> > +static int sprd_dsi_context_init(struct sprd_dsi *dsi,
> > +                     struct device *dev)
> > +{
> > +     struct platform_device *pdev = to_platform_device(dev);
> > +     struct dsi_context *ctx = &dsi->ctx;
> > +     struct resource *res;
> > +
> > +     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +     ctx->base = devm_ioremap(dev, res->start, resource_size(res));
> > +     if (!ctx->base) {
> > +             drm_err(dsi->drm, "failed to map dsi host registers\n");
> > +             return -ENXIO;
> > +     }
> > +
> > +     ctx->pll = devm_kzalloc(dev, sizeof(*ctx->pll), GFP_KERNEL);
> > +     if (!ctx->pll)
> > +             return -ENOMEM;
> > +
> > +     ctx->regmap = devm_regmap_init(dev, &regmap_tst_io, dsi, &byte_config);
> > +     if (IS_ERR(ctx->regmap)) {
> > +             drm_err(dsi->drm, "dphy regmap init failed\n");
> > +             return PTR_ERR(ctx->regmap);
> > +     }
> > +
> > +     ctx->data_hs2lp = 120;
> > +     ctx->data_lp2hs = 500;
> > +     ctx->clk_hs2lp = 4;
> > +     ctx->clk_lp2hs = 15;
> > +     ctx->max_rd_time = 6000;
> > +     ctx->int0_mask = 0xffffffff;
> > +     ctx->int1_mask = 0xffffffff;
> > +     ctx->enabled = true;
> > +
> > +     return 0;
> > +}
> > +
> > +static int sprd_dsi_bind(struct device *dev, struct device *master, void *data)
> > +{
> > +     struct drm_device *drm = data;
> > +     struct sprd_dsi *dsi;
> > +     int ret;
> > +
> > +     dsi = sprd_dsi_encoder_init(drm, dev);
> > +     if (IS_ERR(dsi))
> > +             return PTR_ERR(dsi);
> > +
> > +     dsi->drm = drm;
> > +     dev_set_drvdata(dev, dsi);
> > +
> > +     ret = sprd_dsi_connector_init(drm, dsi);
> > +     if (ret)
> > +             return ret;
> > +
> > +     ret = sprd_dsi_context_init(dsi, dev);
> > +     if (ret)
> > +             return ret;
> > +
> > +     ret = sprd_dsi_host_init(dsi, dev);
> > +     if (ret)
> > +             return ret;
> > +
> > +     return 0;
> > +}
> > +
> > +static void sprd_dsi_unbind(struct device *dev,
> > +                     struct device *master, void *data)
> > +{
> > +     struct sprd_dsi *dsi = dev_get_drvdata(dev);
> > +
> > +     mipi_dsi_host_unregister(&dsi->host);
> > +}
> > +
> > +static const struct component_ops dsi_component_ops = {
> > +     .bind   = sprd_dsi_bind,
> > +     .unbind = sprd_dsi_unbind,
> > +};
> > +
> > +static const struct of_device_id dsi_match_table[] = {
> > +     { .compatible = "sprd,sharkl3-dsi-host" },
> > +     { /* sentinel */ },
> > +};
> > +
> > +static int sprd_dsi_probe(struct platform_device *pdev)
> > +{
> > +     return component_add(&pdev->dev, &dsi_component_ops);
>
> In order to prevent probe issues, you need to register you mipi_dsi_host
> here, see:
> https://lore.kernel.org/dri-devel/20210910101218.1632297-3-maxime@cerno.tech/
We register mipi_dsi_hot on our panel driver, like this:

1092   ret = mipi_dsi_attach(slave);
1093   if (ret) {
1094   DRM_ERROR("failed to attach dsi panel to host\n");
1095   drm_panel_remove(&panel->base);
1096   return ret;
1097   }

>
> Maxime

Re: [PATCH v6 6/6] drm/sprd: add Unisoc's drm mipi dsi&dphy driver

[Kevin Tang]

Maxime Ripard <maxime@cerno.tech> 于2021年9月17日周五 下午11:40写道：
>
> On Fri, Aug 13, 2021 at 10:53:02PM +0800, Kevin Tang wrote:
> > Adds dsi host controller support for the Unisoc's display subsystem.
> > Adds dsi phy support for the Unisoc's display subsystem.
> > Only MIPI DSI Displays supported, DP/TV/HMDI will be support
> > in the feature.
> >
> > v1:
> >   - Remove dphy and dsi graph binding, merge the dphy driver into the dsi.
> >
> > v2:
> >   - Use drm_xxx to replace all DRM_XXX.
> >   - Use kzalloc to replace devm_kzalloc for sprd_dsi structure init.
> >
> > v4:
> >   - Use drmm_helpers to allocate encoder.
> >   - Move allocate encoder and connector to bind function.
> >
> > v5:
> >   - Drop the dsi ip file prefix.
> >   - Fix the checkpatch warnings.
> >   - Add Signed-off-by for dsi&dphy patch.
> >   - Use the mode_flags of mipi_dsi_device to setup crtc DPI and EDPI mode.
> >
> > v6:
> >   - Redesign the way to access the dsi register.
> >   - Reduce the dsi_context member variables.
> > ---
> >  drivers/gpu/drm/sprd/Kconfig         |    1 +
> >  drivers/gpu/drm/sprd/Makefile        |    4 +-
> >  drivers/gpu/drm/sprd/megacores_pll.c |  317 +++++++
> >  drivers/gpu/drm/sprd/megacores_pll.h |  146 +++
> >  drivers/gpu/drm/sprd/sprd_dpu.c      |   17 +
> >  drivers/gpu/drm/sprd/sprd_drm.c      |    1 +
> >  drivers/gpu/drm/sprd/sprd_drm.h      |    1 +
> >  drivers/gpu/drm/sprd/sprd_dsi.c      | 1260 ++++++++++++++++++++++++++
> >  drivers/gpu/drm/sprd/sprd_dsi.h      |   94 ++
> >  9 files changed, 1840 insertions(+), 1 deletion(-)
> >  create mode 100644 drivers/gpu/drm/sprd/megacores_pll.c
> >  create mode 100644 drivers/gpu/drm/sprd/megacores_pll.h
> >  create mode 100644 drivers/gpu/drm/sprd/sprd_dsi.c
> >  create mode 100644 drivers/gpu/drm/sprd/sprd_dsi.h
> >
> > diff --git a/drivers/gpu/drm/sprd/Kconfig b/drivers/gpu/drm/sprd/Kconfig
> > index 37762c333..3edeaeca0 100644
> > --- a/drivers/gpu/drm/sprd/Kconfig
> > +++ b/drivers/gpu/drm/sprd/Kconfig
> > @@ -5,6 +5,7 @@ config DRM_SPRD
> >       select DRM_GEM_CMA_HELPER
> >       select DRM_KMS_CMA_HELPER
> >       select DRM_KMS_HELPER
> > +     select DRM_MIPI_DSI
> >       select VIDEOMODE_HELPERS
> >       help
> >         Choose this option if you have a Unisoc chipset.
> > diff --git a/drivers/gpu/drm/sprd/Makefile b/drivers/gpu/drm/sprd/Makefile
> > index ab12b95e6..73f96c459 100644
> > --- a/drivers/gpu/drm/sprd/Makefile
> > +++ b/drivers/gpu/drm/sprd/Makefile
> > @@ -1,4 +1,6 @@
> >  # SPDX-License-Identifier: GPL-2.0
> >
> >  obj-y := sprd_drm.o \
> > -     sprd_dpu.o
> > +     sprd_dpu.o \
> > +     sprd_dsi.o \
> > +     megacores_pll.o
> > diff --git a/drivers/gpu/drm/sprd/megacores_pll.c b/drivers/gpu/drm/sprd/megacores_pll.c
> > new file mode 100644
> > index 000000000..0dfd3c372
> > --- /dev/null
> > +++ b/drivers/gpu/drm/sprd/megacores_pll.c
> > @@ -0,0 +1,317 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2020 Unisoc Inc.
> > + */
> > +
> > +#include <asm/div64.h>
> > +#include <linux/delay.h>
> > +#include <linux/init.h>
> > +#include <linux/kernel.h>
> > +#include <linux/regmap.h>
> > +#include <linux/string.h>
> > +
> > +#include "megacores_pll.h"
> > +
> > +#define L                                            0
> > +#define H                                            1
> > +#define CLK                                          0
> > +#define DATA                                 1
> > +#define INFINITY                             0xffffffff
> > +#define MIN_OUTPUT_FREQ                      (100)
> > +
> > +#define AVERAGE(a, b) (min(a, b) + abs((b) - (a)) / 2)
> > +
> > +/* sharkle */
> > +#define VCO_BAND_LOW 750
> > +#define VCO_BAND_MID 1100
> > +#define VCO_BAND_HIGH        1500
> > +#define PHY_REF_CLK  26000
> > +
> > +static int dphy_calc_pll_param(struct dphy_pll *pll)
> > +{
> > +     const u32 khz = 1000;
> > +     const u32 mhz = 1000000;
> > +     const unsigned long long factor = 100;
> > +     unsigned long long tmp;
> > +     int i;
> > +
> > +     pll->potential_fvco = pll->freq / khz;
> > +     pll->ref_clk = PHY_REF_CLK / khz;
> > +
> > +     for (i = 0; i < 4; ++i) {
> > +             if (pll->potential_fvco >= VCO_BAND_LOW &&
> > +                     pll->potential_fvco <= VCO_BAND_HIGH) {
> > +                     pll->fvco = pll->potential_fvco;
> > +                     pll->out_sel = BIT(i);
> > +                     break;
> > +             }
> > +             pll->potential_fvco <<= 1;
> > +     }
> > +     if (pll->fvco == 0)
> > +             return -EINVAL;
> > +
> > +     if (pll->fvco >= VCO_BAND_LOW && pll->fvco <= VCO_BAND_MID) {
> > +             /* vco band control */
> > +             pll->vco_band = 0x0;
> > +             /* low pass filter control */
> > +             pll->lpf_sel = 1;
> > +     } else if (pll->fvco > VCO_BAND_MID && pll->fvco <= VCO_BAND_HIGH) {
> > +             pll->vco_band = 0x1;
> > +             pll->lpf_sel = 0;
> > +     } else
> > +             return -EINVAL;
>
> This doesn't follow the kernel coding style, make sure all the issues
> with checkpatch.pl --strict are fixed.
Here I should have used checkpatch to check, maybe the --strict
parameter was not added, i will check it again.
>
> > +
> > +     pll->nint = pll->fvco / pll->ref_clk;
> > +     tmp = pll->fvco * factor * mhz;
> > +     do_div(tmp, pll->ref_clk);
> > +     tmp = tmp - pll->nint * factor * mhz;
> > +     tmp *= BIT(20);
> > +     do_div(tmp, 100000000);
> > +     pll->kint = (u32)tmp;
> > +     pll->refin = 3; /* pre-divider bypass */
> > +     pll->sdm_en = true; /* use fraction N PLL */
> > +     pll->fdk_s = 0x1; /* fraction */
> > +     pll->cp_s = 0x0;
> > +     pll->det_delay = 0x1;
> > +
> > +     return 0;
> > +}
> > +
> > +static void dphy_set_pll_reg(struct dphy_pll *pll, struct regmap *regmap)
> > +{
> > +     struct pll_reg *reg = &pll->reg;
> > +     u8 *val;
> > +     int i;
> > +
> > +     u8 reg_addr[] = {
> > +             0x03, 0x04, 0x06, 0x08, 0x09,
> > +             0x0a, 0x0b, 0x0e, 0x0f
> > +     };
> > +
> > +     reg->_03.bits.prbs_bist = 1;
> > +     reg->_03.bits.en_lp_treot = true;
> > +     reg->_03.bits.lpf_sel = pll->lpf_sel;
> > +     reg->_03.bits.txfifo_bypass = 0;
> > +     reg->_04.bits.div = pll->div;
> > +     reg->_04.bits.masterof8lane = 1;
> > +     reg->_04.bits.cp_s = pll->cp_s;
> > +     reg->_04.bits.fdk_s = pll->fdk_s;
> > +     reg->_06.bits.nint = pll->nint;
> > +     reg->_08.bits.vco_band = pll->vco_band;
> > +     reg->_08.bits.sdm_en = pll->sdm_en;
> > +     reg->_08.bits.refin = pll->refin;
> > +     reg->_09.bits.kint_h = pll->kint >> 12;
> > +     reg->_0a.bits.kint_m = (pll->kint >> 4) & 0xff;
> > +     reg->_0b.bits.out_sel = pll->out_sel;
> > +     reg->_0b.bits.kint_l = pll->kint & 0xf;
> > +     reg->_0e.bits.pll_pu_byp = 0;
> > +     reg->_0e.bits.pll_pu = 0;
> > +     reg->_0e.bits.stopstate_sel = 1;
> > +     reg->_0f.bits.det_delay = pll->det_delay;
> > +
> > +     val = (u8 *)&reg;
> > +
> > +     for (i = 0; i < sizeof(reg_addr); ++i) {
> > +             regmap_write(regmap, reg_addr[i], val[i]);
> > +             DRM_DEBUG("%02x: %02x\n", reg_addr[i], val[i]);
> > +     }
> > +}
>
> It would be great to also convert this part to a pattern without
> structures.
I will try it, but our pll registers, all not have official name from
aisc design owner.
If need to convert it, our pll regiters macro define, it can only be
named as reg_01, reg_02...
>
> > +
> > +int dphy_pll_config(struct dsi_context *ctx)
> > +{
> > +     struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
> > +     struct regmap *regmap = ctx->regmap;
> > +     struct dphy_pll *pll = ctx->pll;
> > +     int ret;
> > +
> > +     pll->freq = dsi->slave->hs_rate;
> > +
> > +     /* FREQ = 26M * (NINT + KINT / 2^20) / out_sel */
> > +     ret = dphy_calc_pll_param(pll);
> > +     if (ret) {
> > +             drm_err(dsi->drm, "failed to calculate dphy pll parameters\n");
> > +             return ret;
> > +     }
> > +     dphy_set_pll_reg(pll, regmap);
> > +
> > +     return 0;
> > +}
> > +
> > +static void dphy_set_timing_reg(struct regmap *regmap, int type, u8 val[])
> > +{
> > +     switch (type) {
> > +     case REQUEST_TIME:
> > +             regmap_write(regmap, 0x31, val[CLK]);
> > +             regmap_write(regmap, 0x41, val[DATA]);
> > +             regmap_write(regmap, 0x51, val[DATA]);
> > +             regmap_write(regmap, 0x61, val[DATA]);
> > +             regmap_write(regmap, 0x71, val[DATA]);
> > +
> > +             regmap_write(regmap, 0x90, val[CLK]);
> > +             regmap_write(regmap, 0xa0, val[DATA]);
> > +             regmap_write(regmap, 0xb0, val[DATA]);
> > +             regmap_write(regmap, 0xc0, val[DATA]);
> > +             regmap_write(regmap, 0xd0, val[DATA]);
> > +             break;
>
> defines and macros would help the readability here
I will try it, but our pll registers, all not have official name from
aisc design owner.
If need to convert it, our pll regiters macro define, it can only be
named as reg_01, reg_02...
>
> > +     case PREPARE_TIME:
> > +             regmap_write(regmap, 0x32, val[CLK]);
> > +             regmap_write(regmap, 0x42, val[DATA]);
> > +             regmap_write(regmap, 0x52, val[DATA]);
> > +             regmap_write(regmap, 0x62, val[DATA]);
> > +             regmap_write(regmap, 0x72, val[DATA]);
> > +
> > +             regmap_write(regmap, 0x91, val[CLK]);
> > +             regmap_write(regmap, 0xa1, val[DATA]);
> > +             regmap_write(regmap, 0xb1, val[DATA]);
> > +             regmap_write(regmap, 0xc1, val[DATA]);
> > +             regmap_write(regmap, 0xd1, val[DATA]);
> > +             break;
> > +     case ZERO_TIME:
> > +             regmap_write(regmap, 0x33, val[CLK]);
> > +             regmap_write(regmap, 0x43, val[DATA]);
> > +             regmap_write(regmap, 0x53, val[DATA]);
> > +             regmap_write(regmap, 0x63, val[DATA]);
> > +             regmap_write(regmap, 0x73, val[DATA]);
> > +
> > +             regmap_write(regmap, 0x92, val[CLK]);
> > +             regmap_write(regmap, 0xa2, val[DATA]);
> > +             regmap_write(regmap, 0xb2, val[DATA]);
> > +             regmap_write(regmap, 0xc2, val[DATA]);
> > +             regmap_write(regmap, 0xd2, val[DATA]);
> > +             break;
> > +     case TRAIL_TIME:
> > +             regmap_write(regmap, 0x34, val[CLK]);
> > +             regmap_write(regmap, 0x44, val[DATA]);
> > +             regmap_write(regmap, 0x54, val[DATA]);
> > +             regmap_write(regmap, 0x64, val[DATA]);
> > +             regmap_write(regmap, 0x74, val[DATA]);
> > +
> > +             regmap_write(regmap, 0x93, val[CLK]);
> > +             regmap_write(regmap, 0xa3, val[DATA]);
> > +             regmap_write(regmap, 0xb3, val[DATA]);
> > +             regmap_write(regmap, 0xc3, val[DATA]);
> > +             regmap_write(regmap, 0xd3, val[DATA]);
> > +             break;
> > +     case EXIT_TIME:
> > +             regmap_write(regmap, 0x36, val[CLK]);
> > +             regmap_write(regmap, 0x46, val[DATA]);
> > +             regmap_write(regmap, 0x56, val[DATA]);
> > +             regmap_write(regmap, 0x66, val[DATA]);
> > +             regmap_write(regmap, 0x76, val[DATA]);
> > +
> > +             regmap_write(regmap, 0x95, val[CLK]);
> > +             regmap_write(regmap, 0xA5, val[DATA]);
> > +             regmap_write(regmap, 0xB5, val[DATA]);
> > +             regmap_write(regmap, 0xc5, val[DATA]);
> > +             regmap_write(regmap, 0xd5, val[DATA]);
> > +             break;
> > +     case CLKPOST_TIME:
> > +             regmap_write(regmap, 0x35, val[CLK]);
> > +             regmap_write(regmap, 0x94, val[CLK]);
> > +             break;
> > +
> > +     /* the following just use default value */
> > +     case SETTLE_TIME:
> > +     case TA_GET:
> > +     case TA_GO:
> > +     case TA_SURE:
> > +             break;
>
> you need to use fallthrough; for all those cases
I get it, thks.

>
> > +     default:
> > +             break;
> > +     }
> > +}
> > +
> > +void dphy_timing_config(struct dsi_context *ctx)
> > +{
> > +     struct regmap *regmap = ctx->regmap;
> > +     struct dphy_pll *pll = ctx->pll;
> > +     const u32 factor = 2;
> > +     const u32 scale = 100;
> > +     u32 t_ui, t_byteck, t_half_byteck;
> > +     u32 range[2], constant;
> > +     u8 val[2];
> > +     u32 tmp = 0;
> > +
> > +     /* t_ui: 1 ui, byteck: 8 ui, half byteck: 4 ui */
> > +     t_ui = 1000 * scale / (pll->freq / 1000);
> > +     t_byteck = t_ui << 3;
> > +     t_half_byteck = t_ui << 2;
> > +     constant = t_ui << 1;
> > +
> > +     /* REQUEST_TIME: HS T-LPX: LP-01
> > +      * For T-LPX, mipi spec defined min value is 50ns,
> > +      * but maybe it shouldn't be too small, because BTA,
> > +      * LP-10, LP-00, LP-01, all of this is related to T-LPX.
> > +      */
> > +     range[L] = 50 * scale;
> > +     range[H] = INFINITY;
> > +     val[CLK] = DIV_ROUND_UP(range[L] * (factor << 1), t_byteck) - 2;
> > +     val[DATA] = val[CLK];
> > +     dphy_set_timing_reg(regmap, REQUEST_TIME, val);
> > +
> > +     /* PREPARE_TIME: HS sequence: LP-00 */
> > +     range[L] = 38 * scale;
> > +     range[H] = 95 * scale;
> > +     tmp = AVERAGE(range[L], range[H]);
> > +     val[CLK] = DIV_ROUND_UP(AVERAGE(range[L], range[H]),
> > +                     t_half_byteck) - 1;
> > +     range[L] = 40 * scale + 4 * t_ui;
> > +     range[H] = 85 * scale + 6 * t_ui;
> > +     tmp |= AVERAGE(range[L], range[H]) << 16;
> > +     val[DATA] = DIV_ROUND_UP(AVERAGE(range[L], range[H]),
> > +                     t_half_byteck) - 1;
> > +     dphy_set_timing_reg(regmap, PREPARE_TIME, val);
> > +
> > +     /* ZERO_TIME: HS-ZERO */
> > +     range[L] = 300 * scale;
> > +     range[H] = INFINITY;
> > +     val[CLK] = DIV_ROUND_UP(range[L] * factor + (tmp & 0xffff)
> > +                     - 525 * t_byteck / 100, t_byteck) - 2;
> > +     range[L] = 145 * scale + 10 * t_ui;
> > +     val[DATA] = DIV_ROUND_UP(range[L] * factor
> > +                     + ((tmp >> 16) & 0xffff) - 525 * t_byteck / 100,
> > +                     t_byteck) - 2;
> > +     dphy_set_timing_reg(regmap, ZERO_TIME, val);
> > +
> > +     /* TRAIL_TIME: HS-TRAIL */
> > +     range[L] = 60 * scale;
> > +     range[H] = INFINITY;
> > +     val[CLK] = DIV_ROUND_UP(range[L] * factor - constant, t_half_byteck);
> > +     range[L] = max(8 * t_ui, 60 * scale + 4 * t_ui);
> > +     val[DATA] = DIV_ROUND_UP(range[L] * 3 / 2 - constant, t_half_byteck) - 2;
> > +     dphy_set_timing_reg(regmap, TRAIL_TIME, val);
> > +
> > +     /* EXIT_TIME: */
> > +     range[L] = 100 * scale;
> > +     range[H] = INFINITY;
> > +     val[CLK] = DIV_ROUND_UP(range[L] * factor, t_byteck) - 2;
> > +     val[DATA] = val[CLK];
> > +     dphy_set_timing_reg(regmap, EXIT_TIME, val);
> > +
> > +     /* CLKPOST_TIME: */
> > +     range[L] = 60 * scale + 52 * t_ui;
> > +     range[H] = INFINITY;
> > +     val[CLK] = DIV_ROUND_UP(range[L] * factor, t_byteck) - 2;
> > +     val[DATA] = val[CLK];
> > +     dphy_set_timing_reg(regmap, CLKPOST_TIME, val);
> > +
> > +     /* SETTLE_TIME:
> > +      * This time is used for receiver. So for transmitter,
> > +      * it can be ignored.
> > +      */
> > +
> > +     /* TA_GO:
> > +      * transmitter drives bridge state(LP-00) before releasing control,
> > +      * reg 0x1f default value: 0x04, which is good.
> > +      */
> > +
> > +     /* TA_SURE:
> > +      * After LP-10 state and before bridge state(LP-00),
> > +      * reg 0x20 default value: 0x01, which is good.
> > +      */
> > +
> > +     /* TA_GET:
> > +      * receiver drives Bridge state(LP-00) before releasing control
> > +      * reg 0x21 default value: 0x03, which is good.
> > +      */
> > +}
> > diff --git a/drivers/gpu/drm/sprd/megacores_pll.h b/drivers/gpu/drm/sprd/megacores_pll.h
> > new file mode 100644
> > index 000000000..bf20aae65
> > --- /dev/null
> > +++ b/drivers/gpu/drm/sprd/megacores_pll.h
> > @@ -0,0 +1,146 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (C) 2020 Unisoc Inc.
> > + */
> > +
> > +#ifndef _MEGACORES_PLL_H_
> > +#define _MEGACORES_PLL_H_
> > +
> > +#include "sprd_dsi.h"
> > +
> > +enum PLL_TIMING {
> > +     NONE,
> > +     REQUEST_TIME,
> > +     PREPARE_TIME,
> > +     SETTLE_TIME,
> > +     ZERO_TIME,
> > +     TRAIL_TIME,
> > +     EXIT_TIME,
> > +     CLKPOST_TIME,
> > +     TA_GET,
> > +     TA_GO,
> > +     TA_SURE,
> > +     TA_WAIT,
> > +};
> > +
> > +struct pll_reg {
> > +     union __reg_03__ {
> > +             struct __03 {
> > +                     u8 prbs_bist: 1;
> > +                     u8 en_lp_treot: 1;
> > +                     u8 lpf_sel: 4;
> > +                     u8 txfifo_bypass: 1;
> > +                     u8 freq_hopping: 1;
> > +             } bits;
> > +             u8 val;
> > +     } _03;
> > +     union __reg_04__ {
> > +             struct __04 {
> > +                     u8 div: 3;
> > +                     u8 masterof8lane: 1;
> > +                     u8 hop_trig: 1;
> > +                     u8 cp_s: 2;
> > +                     u8 fdk_s: 1;
> > +             } bits;
> > +             u8 val;
> > +     } _04;
> > +     union __reg_06__ {
> > +             struct __06 {
> > +                     u8 nint: 7;
> > +                     u8 mod_en: 1;
> > +             } bits;
> > +             u8 val;
> > +     } _06;
> > +     union __reg_07__ {
> > +             struct __07 {
> > +                     u8 kdelta_h: 8;
> > +             } bits;
> > +             u8 val;
> > +     } _07;
> > +     union __reg_08__ {
> > +             struct __08 {
> > +                     u8 vco_band: 1;
> > +                     u8 sdm_en: 1;
> > +                     u8 refin: 2;
> > +                     u8 kdelta_l: 4;
> > +             } bits;
> > +             u8 val;
> > +     } _08;
> > +     union __reg_09__ {
> > +             struct __09 {
> > +                     u8 kint_h: 8;
> > +             } bits;
> > +             u8 val;
> > +     } _09;
> > +     union __reg_0a__ {
> > +             struct __0a {
> > +                     u8 kint_m: 8;
> > +             } bits;
> > +             u8 val;
> > +     } _0a;
> > +     union __reg_0b__ {
> > +             struct __0b {
> > +                     u8 out_sel: 4;
> > +                     u8 kint_l: 4;
> > +             } bits;
> > +             u8 val;
> > +     } _0b;
> > +     union __reg_0c__ {
> > +             struct __0c {
> > +                     u8 kstep_h: 8;
> > +             } bits;
> > +             u8 val;
> > +     } _0c;
> > +     union __reg_0d__ {
> > +             struct __0d {
> > +                     u8 kstep_m: 8;
> > +             } bits;
> > +             u8 val;
> > +     } _0d;
> > +     union __reg_0e__ {
> > +             struct __0e {
> > +                     u8 pll_pu_byp: 1;
> > +                     u8 pll_pu: 1;
> > +                     u8 hsbist_len: 2;
> > +                     u8 stopstate_sel: 1;
> > +                     u8 kstep_l: 3;
> > +             } bits;
> > +             u8 val;
> > +     } _0e;
> > +     union __reg_0f__ {
> > +             struct __0f {
> > +                     u8 det_delay:2;
> > +                     u8 kdelta: 4;
> > +                     u8 ldo0p4:2;
> > +             } bits;
> > +             u8 val;
> > +     } _0f;
> > +};
> > +
> > +struct dphy_pll {
> > +     u8 refin; /* Pre-divider control signal */
> > +     u8 cp_s; /* 00: SDM_EN=1, 10: SDM_EN=0 */
> > +     u8 fdk_s; /* PLL mode control: integer or fraction */
> > +     u8 sdm_en;
> > +     u8 div;
> > +     u8 int_n; /* integer N PLL */
> > +     u32 ref_clk; /* dphy reference clock, unit: MHz */
> > +     u32 freq; /* panel config, unit: KHz */
> > +     u32 fvco;
> > +     u32 potential_fvco;
> > +     u32 nint; /* sigma delta modulator NINT control */
> > +     u32 kint; /* sigma delta modulator KINT control */
> > +     u8 lpf_sel; /* low pass filter control */
> > +     u8 out_sel; /* post divider control */
> > +     u8 vco_band; /* vco range */
> > +     u8 det_delay;
> > +
> > +     struct pll_reg reg;
> > +};
> > +
> > +struct dsi_context;
> > +
> > +int dphy_pll_config(struct dsi_context *ctx);
> > +void dphy_timing_config(struct dsi_context *ctx);
> > +
> > +#endif /* _MEGACORES_PLL_H_ */
> > diff --git a/drivers/gpu/drm/sprd/sprd_dpu.c b/drivers/gpu/drm/sprd/sprd_dpu.c
> > index 448dd4fb6..4e3b30abe 100644
> > --- a/drivers/gpu/drm/sprd/sprd_dpu.c
> > +++ b/drivers/gpu/drm/sprd/sprd_dpu.c
> > @@ -25,6 +25,7 @@
> >
> >  #include "sprd_drm.h"
> >  #include "sprd_dpu.h"
> > +#include "sprd_dsi.h"
> >
> >  /* Global control registers */
> >  #define REG_DPU_CTRL 0x04
> > @@ -686,9 +687,25 @@ static void sprd_crtc_mode_set_nofb(struct drm_crtc *crtc)
> >  {
> >       struct sprd_dpu *dpu = to_sprd_crtc(crtc);
> >       struct drm_display_mode *mode = &crtc->state->adjusted_mode;
> > +     struct drm_encoder *encoder;
> > +     struct mipi_dsi_device *slave;
> > +     struct sprd_dsi *dsi;
> >
> >       drm_display_mode_to_videomode(mode, &dpu->ctx.vm);
> >
> > +     drm_for_each_encoder(encoder, crtc->dev) {
> > +             if (encoder->crtc != crtc)
> > +                     continue;
> > +
> > +             dsi = encoder_to_dsi(encoder);
> > +             slave = dsi->slave;
> > +
> > +             if (slave->mode_flags & MIPI_DSI_MODE_VIDEO)
> > +                     dpu->ctx.if_type = SPRD_DPU_IF_DPI;
> > +             else
> > +                     dpu->ctx.if_type = SPRD_DPU_IF_EDPI;
> > +     }
> > +
>
> You're not using if_type anywhere
Used in sprd_dpu.c as for crtc output type dpi or edpi.
>
> >       sprd_dpi_init(dpu);
> >  }
> >
> > diff --git a/drivers/gpu/drm/sprd/sprd_drm.c b/drivers/gpu/drm/sprd/sprd_drm.c
> > index 549b71278..68cf0933c 100644
> > --- a/drivers/gpu/drm/sprd/sprd_drm.c
> > +++ b/drivers/gpu/drm/sprd/sprd_drm.c
> > @@ -183,6 +183,7 @@ static struct platform_driver sprd_drm_driver = {
> >  static struct platform_driver *sprd_drm_drivers[]  = {
> >       &sprd_drm_driver,
> >       &sprd_dpu_driver,
> > +     &sprd_dsi_driver,
> >  };
> >
> >  static int __init sprd_drm_init(void)
> > diff --git a/drivers/gpu/drm/sprd/sprd_drm.h b/drivers/gpu/drm/sprd/sprd_drm.h
> > index 85d4a8b9f..95d1b972f 100644
> > --- a/drivers/gpu/drm/sprd/sprd_drm.h
> > +++ b/drivers/gpu/drm/sprd/sprd_drm.h
> > @@ -14,5 +14,6 @@ struct sprd_drm {
> >  };
> >
> >  extern struct platform_driver sprd_dpu_driver;
> > +extern struct platform_driver sprd_dsi_driver;
> >
> >  #endif /* _SPRD_DRM_H_ */
> > diff --git a/drivers/gpu/drm/sprd/sprd_dsi.c b/drivers/gpu/drm/sprd/sprd_dsi.c
> > new file mode 100644
> > index 000000000..5ce98fe90
> > --- /dev/null
> > +++ b/drivers/gpu/drm/sprd/sprd_dsi.c
> > @@ -0,0 +1,1260 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2020 Unisoc Inc.
> > + */
> > +
> > +#include <linux/component.h>
> > +#include <linux/module.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/of_graph.h>
> > +#include <video/mipi_display.h>
> > +
> > +#include <drm/drm_atomic_helper.h>
> > +#include <drm/drm_crtc_helper.h>
> > +#include <drm/drm_of.h>
> > +#include <drm/drm_probe_helper.h>
> > +
> > +#include "sprd_drm.h"
> > +#include "sprd_dpu.h"
> > +#include "sprd_dsi.h"
> > +
> > +#define SOFT_RESET 0x04
> > +#define MASK_PROTOCOL_INT 0x0C
> > +#define MASK_INTERNAL_INT 0x14
> > +#define DSI_MODE_CFG 0x18
> > +
> > +#define VIRTUAL_CHANNEL_ID 0x1C
> > +#define GEN_RX_VCID GENMASK(1, 0)
> > +#define VIDEO_PKT_VCID GENMASK(3, 2)
> > +
> > +#define DPI_VIDEO_FORMAT 0x20
> > +#define DPI_VIDEO_MODE_FORMAT GENMASK(5, 0)
> > +#define LOOSELY18_EN BIT(6)
> > +
> > +#define VIDEO_PKT_CONFIG 0x24
> > +#define VIDEO_PKT_SIZE GENMASK(15, 0)
> > +#define VIDEO_LINE_CHUNK_NUM GENMASK(31, 16)
> > +
> > +#define VIDEO_LINE_HBLK_TIME 0x28
> > +#define VIDEO_LINE_HBP_TIME GENMASK(15, 0)
> > +#define VIDEO_LINE_HSA_TIME GENMASK(31, 16)
> > +
> > +#define VIDEO_LINE_TIME 0x2C
> > +
> > +#define VIDEO_VBLK_LINES 0x30
> > +#define VFP_LINES GENMASK(9, 0)
> > +#define VBP_LINES GENMASK(19, 10)
> > +#define VSA_LINES GENMASK(29, 20)
> > +
> > +#define VIDEO_VACTIVE_LINES 0x34
> > +
> > +#define VID_MODE_CFG 0x38
> > +#define VID_MODE_TYPE GENMASK(1, 0)
> > +#define LP_VSA_EN BIT(8)
> > +#define LP_VBP_EN BIT(9)
> > +#define LP_VFP_EN BIT(10)
> > +#define LP_VACT_EN BIT(11)
> > +#define LP_HBP_EN BIT(12)
> > +#define LP_HFP_EN BIT(13)
> > +#define FRAME_BTA_ACK_EN BIT(14)
> > +#define LP_CMD_EN BIT(15)
> > +
> > +#define TIMEOUT_CNT_CLK_CONFIG 0x40
> > +#define HTX_TO_CONFIG 0x44
> > +#define LRX_H_TO_CONFIG 0x48
> > +
> > +#define TX_ESC_CLK_CONFIG 0x5C
> > +
> > +#define CMD_MODE_CFG 0x68
> > +#define TEAR_FX_EN BIT(0)
> > +#define ACK_RQST_EN BIT(1)
> > +#define PPS_TX BIT(5)
> > +#define EXQ_TX BIT(6)
> > +#define CMC_TX BIT(7)
> > +#define GEN_SW_0P_TX BIT(8)
> > +#define GEN_SW_1P_TX BIT(9)
> > +#define GEN_SW_2P_TX BIT(10)
> > +#define GEN_SR_0P_TX BIT(11)
> > +#define GEN_SR_1P_TX BIT(12)
> > +#define GEN_SR_2P_TX BIT(13)
> > +#define GEN_LW_TX BIT(14)
> > +#define DCS_SW_0P_TX BIT(16)
> > +#define DCS_SW_1P_TX BIT(17)
> > +#define DCS_SR_0P_TX BIT(18)
> > +#define DCS_LW_TX BIT(19)
> > +#define MAX_RD_PKT_SIZE BIT(24)
> > +
> > +#define GEN_HDR 0x6C
> > +#define GEN_DT GENMASK(5, 0)
> > +#define GEN_VC GENMASK(7, 6)
> > +#define GEN_WC_LSBYTE GENMASK(15, 8)
> > +#define GEN_WC_MSBYTE GENMASK(23, 16)
> > +
> > +#define GEN_PLD_DATA 0x70
> > +#define GEN_PLD_B1 GENMASK(7, 0)
> > +#define GEN_PLD_B2 GENMASK(15, 8)
> > +#define GEN_PLD_B3 GENMASK(23, 16)
> > +#define GEN_PLD_B4 GENMASK(31, 24)
> > +
> > +#define PHY_CLK_LANE_LP_CTRL 0x74
> > +#define PHY_CLKLANE_TX_REQ_HS BIT(0)
> > +#define AUTO_CLKLANE_CTRL_EN BIT(1)
> > +
> > +#define PHY_INTERFACE_CTRL 0x78
> > +#define RF_PHY_SHUTDOWN BIT(0)
> > +#define RF_PHY_RESET_N BIT(1)
> > +#define RF_PHY_CLK_EN BIT(2)
> > +
> > +#define CMD_MODE_STATUS 0x98
> > +#define GEN_CMD_RDCMD_ONGOING BIT(0)
> > +#define GEN_CMD_RDATA_FIFO_EMPTY BIT(1)
> > +#define GEN_CMD_RDATA_FIFO_FULL BIT(2)
> > +#define GEN_CMD_WDATA_FIFO_EMPTY BIT(3)
> > +#define GEN_CMD_WDATA_FIFO_FULL BIT(4)
> > +#define GEN_CMD_CMD_FIFO_EMPTY BIT(5)
> > +#define GEN_CMD_CMD_FIFO_FULL BIT(6)
> > +#define GEN_CMD_RDCMD_DONE BIT(7)
> > +
> > +#define PHY_STATUS 0x9C
> > +#define PHY_LOCK BIT(1)
> > +
> > +#define PHY_MIN_STOP_TIME 0xA0
> > +#define PHY_LANE_NUM_CONFIG 0xA4
> > +
> > +#define PHY_CLKLANE_TIME_CONFIG 0xA8
> > +#define PHY_CLKLANE_LP_TO_HS_TIME GENMASK(15, 0)
> > +#define PHY_CLKLANE_HS_TO_LP_TIME GENMASK(31, 16)
> > +
> > +#define PHY_DATALANE_TIME_CONFIG 0xAC
> > +#define PHY_DATALANE_LP_TO_HS_TIME GENMASK(15, 0)
> > +#define PHY_DATALANE_HS_TO_LP_TIME GENMASK(31, 16)
> > +
> > +#define MAX_READ_TIME 0xB0
> > +
> > +#define RX_PKT_CHECK_CONFIG 0xB4
> > +#define RX_PKT_ECC_EN BIT(0)
> > +#define RX_PKT_CRC_EN BIT(1)
> > +
> > +#define TA_EN 0xB8
> > +
> > +#define EOTP_EN 0xBC
> > +#define TX_EOTP_EN BIT(0)
> > +#define RX_EOTP_EN BIT(1)
> > +
> > +#define VIDEO_NULLPKT_SIZE 0xC0
> > +#define DCS_WM_PKT_SIZE 0xC4
> > +#define PROTOCOL_INT_CLR 0xC8
> > +#define INTERNAL_INT_CLR 0xCC
> > +
> > +#define VIDEO_SIG_DELAY_CONFIG 0xD0
> > +#define VIDEO_SIG_DELAY GENMASK(23, 0)
> > +#define VIDEO_SIG_DELAY_MODE BIT(24)
> > +
> > +#define PHY_TST_CTRL0 0xF0
> > +#define PHY_TESTCLR BIT(0)
> > +#define PHY_TESTCLK BIT(1)
> > +
> > +#define PHY_TST_CTRL1 0xF4
> > +#define PHY_TESTDIN GENMASK(7, 0)
> > +#define PHY_TESTDOUT GENMASK(15, 8)
> > +#define PHY_TESTEN BIT(16)
> > +
> > +#define host_to_dsi(host) \
> > +     container_of(host, struct sprd_dsi, host)
> > +#define connector_to_dsi(connector) \
> > +     container_of(connector, struct sprd_dsi, connector)
> > +
> > +static inline u32
> > +dsi_reg_rd(struct dsi_context *ctx, u32 offset, u32 mask,
> > +                     u32 shift)
> > +{
> > +     return (readl(ctx->base + offset) & mask) >> shift;
> > +}
> > +
> > +static inline void
> > +dsi_reg_wr(struct dsi_context *ctx, u32 offset, u32 mask,
> > +                     u32 shift, u32 val)
> > +{
> > +     u32 ret;
> > +
> > +     ret = readl(ctx->base + offset);
> > +     ret &= ~mask;
> > +     ret |= (val << shift) & mask;
> > +     writel(ret, ctx->base + offset);
> > +}
> > +
> > +static inline void
> > +dsi_reg_up(struct dsi_context *ctx, u32 offset, u32 mask,
> > +                     u32 val)
> > +{
> > +     u32 ret = readl(ctx->base + offset);
> > +
> > +     writel((ret & ~mask) | (val & mask), ctx->base + offset);
> > +}
> > +
> > +static int regmap_tst_io_write(void *context, u32 reg, u32 val)
> > +{
> > +     struct sprd_dsi *dsi = context;
> > +     struct dsi_context *ctx = &dsi->ctx;
> > +
> > +     if (val > 0xff || reg > 0xff)
> > +             return -EINVAL;
> > +
> > +     drm_dbg(dsi->drm, "reg = 0x%02x, val = 0x%02x\n", reg, val);
> > +
> > +     dsi_reg_up(ctx, PHY_TST_CTRL1, PHY_TESTEN, PHY_TESTEN);
> > +     dsi_reg_wr(ctx, PHY_TST_CTRL1, PHY_TESTDIN, 0, reg);
> > +     dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, PHY_TESTCLK);
> > +     dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, 0);
> > +     dsi_reg_up(ctx, PHY_TST_CTRL1, PHY_TESTEN, 0);
> > +     dsi_reg_wr(ctx, PHY_TST_CTRL1, PHY_TESTDIN, 0, val);
> > +     dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, PHY_TESTCLK);
> > +     dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, 0);
> > +
> > +     return 0;
> > +}
> > +
> > +static int regmap_tst_io_read(void *context, u32 reg, u32 *val)
> > +{
> > +     struct sprd_dsi *dsi = context;
> > +     struct dsi_context *ctx = &dsi->ctx;
> > +     int ret;
> > +
> > +     if (reg > 0xff)
> > +             return -EINVAL;
> > +
> > +     dsi_reg_up(ctx, PHY_TST_CTRL1, PHY_TESTEN, PHY_TESTEN);
> > +     dsi_reg_wr(ctx, PHY_TST_CTRL1, PHY_TESTDIN, 0, reg);
> > +     dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, PHY_TESTCLK);
> > +     dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, 0);
> > +     dsi_reg_up(ctx, PHY_TST_CTRL1, PHY_TESTEN, 0);
> > +
> > +     udelay(1);
> > +
> > +     ret = dsi_reg_rd(ctx, PHY_TST_CTRL1, PHY_TESTDOUT, 8);
> > +     if (ret < 0)
> > +             return ret;
> > +
> > +     *val = ret;
> > +
> > +     drm_dbg(dsi->drm, "reg = 0x%02x, val = 0x%02x\n", reg, *val);
> > +     return 0;
> > +}
> > +
> > +static struct regmap_bus regmap_tst_io = {
> > +     .reg_write = regmap_tst_io_write,
> > +     .reg_read = regmap_tst_io_read,
> > +};
> > +
> > +static const struct regmap_config byte_config = {
> > +     .reg_bits = 8,
> > +     .val_bits = 8,
> > +};
> > +
> > +static int dphy_wait_pll_locked(struct dsi_context *ctx)
> > +{
> > +     struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
> > +     int i;
> > +
> > +     for (i = 0; i < 50000; i++) {
> > +             if (dsi_reg_rd(ctx, PHY_STATUS, PHY_LOCK, 1))
> > +                     return 0;
> > +             udelay(3);
> > +     }
> > +
> > +     drm_err(dsi->drm, "dphy pll can not be locked\n");
> > +     return -ETIMEDOUT;
> > +}
> > +
> > +static int dsi_wait_tx_payload_fifo_empty(struct dsi_context *ctx)
> > +{
> > +     int i;
> > +
> > +     for (i = 0; i < 5000; i++) {
> > +             if (dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_WDATA_FIFO_EMPTY, 3))
> > +                     return 0;
> > +             udelay(1);
> > +     }
> > +
> > +     return -ETIMEDOUT;
> > +}
> > +
> > +static int dsi_wait_tx_cmd_fifo_empty(struct dsi_context *ctx)
> > +{
> > +     int i;
> > +
> > +     for (i = 0; i < 5000; i++) {
> > +             if (dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_CMD_FIFO_EMPTY, 5))
> > +                     return 0;
> > +             udelay(1);
> > +     }
> > +
> > +     return -ETIMEDOUT;
> > +}
> > +
> > +static int dsi_wait_rd_resp_completed(struct dsi_context *ctx)
> > +{
> > +     int i;
> > +
> > +     for (i = 0; i < 10000; i++) {
> > +             if (dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_RDCMD_DONE, 7))
> > +                     return 0;
> > +             udelay(10);
> > +     }
> > +
> > +     return -ETIMEDOUT;
> > +}
> > +
> > +static u16 calc_bytes_per_pixel_x100(int coding)
> > +{
> > +     u16 Bpp_x100;
> > +
> > +     switch (coding) {
> > +     case COLOR_CODE_16BIT_CONFIG1:
> > +     case COLOR_CODE_16BIT_CONFIG2:
> > +     case COLOR_CODE_16BIT_CONFIG3:
> > +             Bpp_x100 = 200;
> > +             break;
> > +     case COLOR_CODE_18BIT_CONFIG1:
> > +     case COLOR_CODE_18BIT_CONFIG2:
> > +             Bpp_x100 = 225;
> > +             break;
> > +     case COLOR_CODE_24BIT:
> > +             Bpp_x100 = 300;
> > +             break;
> > +     case COLOR_CODE_COMPRESSTION:
> > +             Bpp_x100 = 100;
> > +             break;
> > +     case COLOR_CODE_20BIT_YCC422_LOOSELY:
> > +             Bpp_x100 = 250;
> > +             break;
> > +     case COLOR_CODE_24BIT_YCC422:
> > +             Bpp_x100 = 300;
> > +             break;
> > +     case COLOR_CODE_16BIT_YCC422:
> > +             Bpp_x100 = 200;
> > +             break;
> > +     case COLOR_CODE_30BIT:
> > +             Bpp_x100 = 375;
> > +             break;
> > +     case COLOR_CODE_36BIT:
> > +             Bpp_x100 = 450;
> > +             break;
> > +     case COLOR_CODE_12BIT_YCC420:
> > +             Bpp_x100 = 150;
> > +             break;
> > +     default:
> > +             DRM_ERROR("invalid color coding");
> > +             Bpp_x100 = 0;
> > +             break;
> > +     }
> > +
> > +     return Bpp_x100;
> > +}
> > +
> > +static u8 calc_video_size_step(int coding)
> > +{
> > +     u8 video_size_step;
> > +
> > +     switch (coding) {
> > +     case COLOR_CODE_16BIT_CONFIG1:
> > +     case COLOR_CODE_16BIT_CONFIG2:
> > +     case COLOR_CODE_16BIT_CONFIG3:
> > +     case COLOR_CODE_18BIT_CONFIG1:
> > +     case COLOR_CODE_18BIT_CONFIG2:
> > +     case COLOR_CODE_24BIT:
> > +     case COLOR_CODE_COMPRESSTION:
> > +             return video_size_step = 1;
> > +     case COLOR_CODE_20BIT_YCC422_LOOSELY:
> > +     case COLOR_CODE_24BIT_YCC422:
> > +     case COLOR_CODE_16BIT_YCC422:
> > +     case COLOR_CODE_30BIT:
> > +     case COLOR_CODE_36BIT:
> > +     case COLOR_CODE_12BIT_YCC420:
> > +             return video_size_step = 2;
> > +     default:
> > +             DRM_ERROR("invalid color coding");
> > +             return 0;
> > +     }
> > +}
> > +
> > +static u16 round_video_size(int coding, u16 video_size)
> > +{
> > +     switch (coding) {
> > +     case COLOR_CODE_16BIT_YCC422:
> > +     case COLOR_CODE_24BIT_YCC422:
> > +     case COLOR_CODE_20BIT_YCC422_LOOSELY:
> > +     case COLOR_CODE_12BIT_YCC420:
> > +             /* round up active H pixels to a multiple of 2 */
> > +             if ((video_size % 2) != 0)
> > +                     video_size += 1;
> > +             break;
> > +     default:
> > +             break;
> > +     }
> > +
> > +     return video_size;
> > +}
> > +
> > +#define SPRD_MIPI_DSI_FMT_DSC 0xff
> > +static u32 fmt_to_coding(u32 fmt)
> > +{
> > +     switch (fmt) {
> > +     case MIPI_DSI_FMT_RGB565:
> > +             return COLOR_CODE_16BIT_CONFIG1;
> > +     case MIPI_DSI_FMT_RGB666:
> > +     case MIPI_DSI_FMT_RGB666_PACKED:
> > +             return COLOR_CODE_18BIT_CONFIG1;
> > +     case MIPI_DSI_FMT_RGB888:
> > +             return COLOR_CODE_24BIT;
> > +     case SPRD_MIPI_DSI_FMT_DSC:
> > +             return COLOR_CODE_COMPRESSTION;
> > +     default:
> > +             DRM_ERROR("Unsupported format (%d)\n", fmt);
> > +             return COLOR_CODE_24BIT;
> > +     }
> > +}
> > +
> > +#define ns_to_cycle(ns, byte_clk) \
> > +     DIV_ROUND_UP((ns) * (byte_clk), 1000000)
> > +
> > +static void sprd_dsi_init(struct dsi_context *ctx)
> > +{
> > +     struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
> > +     u32 byte_clk = dsi->slave->hs_rate / 8;
> > +     u16 data_hs2lp, data_lp2hs, clk_hs2lp, clk_lp2hs;
> > +     u16 max_rd_time;
> > +     int div;
> > +
> > +     writel(0, ctx->base + SOFT_RESET);
> > +     writel(0xffffffff, ctx->base + MASK_PROTOCOL_INT);
> > +     writel(0xffffffff, ctx->base + MASK_INTERNAL_INT);
> > +     writel(1, ctx->base + DSI_MODE_CFG);
> > +     dsi_reg_up(ctx, EOTP_EN, RX_EOTP_EN, 0);
> > +     dsi_reg_up(ctx, EOTP_EN, TX_EOTP_EN, 0);
> > +     dsi_reg_up(ctx, RX_PKT_CHECK_CONFIG, RX_PKT_ECC_EN, RX_PKT_ECC_EN);
> > +     dsi_reg_up(ctx, RX_PKT_CHECK_CONFIG, RX_PKT_CRC_EN, RX_PKT_CRC_EN);
> > +     writel(1, ctx->base + TA_EN);
> > +     dsi_reg_up(ctx, VIRTUAL_CHANNEL_ID, VIDEO_PKT_VCID, 0);
> > +     dsi_reg_up(ctx, VIRTUAL_CHANNEL_ID, GEN_RX_VCID, 0);
> > +
> > +     div = DIV_ROUND_UP(byte_clk, dsi->slave->lp_rate);
> > +     writel(div, ctx->base + TX_ESC_CLK_CONFIG);
> > +
> > +     max_rd_time = ns_to_cycle(ctx->max_rd_time, byte_clk);
> > +     writel(max_rd_time, ctx->base + MAX_READ_TIME);
> > +
> > +     data_hs2lp = ns_to_cycle(ctx->data_hs2lp, byte_clk);
> > +     data_lp2hs = ns_to_cycle(ctx->data_lp2hs, byte_clk);
> > +     clk_hs2lp = ns_to_cycle(ctx->clk_hs2lp, byte_clk);
> > +     clk_lp2hs = ns_to_cycle(ctx->clk_lp2hs, byte_clk);
> > +     dsi_reg_wr(ctx, PHY_DATALANE_TIME_CONFIG,
> > +             PHY_DATALANE_HS_TO_LP_TIME, 16, data_hs2lp);
> > +     dsi_reg_wr(ctx, PHY_DATALANE_TIME_CONFIG,
> > +             PHY_DATALANE_LP_TO_HS_TIME, 0, data_lp2hs);
> > +     dsi_reg_wr(ctx, PHY_CLKLANE_TIME_CONFIG,
> > +             PHY_CLKLANE_HS_TO_LP_TIME, 16, clk_hs2lp);
> > +     dsi_reg_wr(ctx, PHY_CLKLANE_TIME_CONFIG,
> > +             PHY_CLKLANE_LP_TO_HS_TIME, 0, clk_lp2hs);
> > +
> > +     writel(1, ctx->base + SOFT_RESET);
> > +}
> > +
> > +/*
> > + * Free up resources and shutdown host controller and PHY
> > + */
> > +static void sprd_dsi_fini(struct dsi_context *ctx)
> > +{
> > +     writel(0xffffffff, ctx->base + MASK_PROTOCOL_INT);
> > +     writel(0xffffffff, ctx->base + MASK_INTERNAL_INT);
> > +     writel(0, ctx->base + SOFT_RESET);
> > +}
> > +
> > +/*
> > + * If not in burst mode, it will compute the video and null packet sizes
> > + * according to necessity.
> > + * Configure timers for data lanes and/or clock lane to return to LP when
> > + * bandwidth is not filled by data.
> > + */
> > +static int sprd_dsi_dpi_video(struct dsi_context *ctx)
> > +{
> > +     struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
> > +     struct videomode *vm = &ctx->vm;
> > +     u32 byte_clk = dsi->slave->hs_rate / 8;
> > +     u16 Bpp_x100;
> > +     u16 video_size;
> > +     u32 ratio_x1000;
> > +     u16 null_pkt_size = 0;
> > +     u8 video_size_step;
> > +     u32 hs_to;
> > +     u32 total_bytes;
> > +     u32 bytes_per_chunk;
> > +     u32 chunks = 0;
> > +     u32 bytes_left = 0;
> > +     u32 chunk_overhead;
> > +     const u8 pkt_header = 6;
> > +     u8 coding;
> > +     int div;
> > +     u16 hline;
> > +     u16 byte_cycle;
> > +
> > +     coding = fmt_to_coding(dsi->slave->format);
> > +     video_size = round_video_size(coding, vm->hactive);
> > +     Bpp_x100 = calc_bytes_per_pixel_x100(coding);
> > +     video_size_step = calc_video_size_step(coding);
> > +     ratio_x1000 = byte_clk * 1000 / (vm->pixelclock / 1000);
> > +     hline = vm->hactive + vm->hsync_len + vm->hfront_porch +
> > +             vm->hback_porch;
> > +
> > +     writel(0, ctx->base + SOFT_RESET);
> > +     dsi_reg_wr(ctx, VID_MODE_CFG, FRAME_BTA_ACK_EN, 15, ctx->frame_ack_en);
> > +     dsi_reg_wr(ctx, DPI_VIDEO_FORMAT, DPI_VIDEO_MODE_FORMAT, 0, coding);
> > +     dsi_reg_wr(ctx, VID_MODE_CFG, VID_MODE_TYPE, 0, ctx->burst_mode);
> > +     byte_cycle = 95 * hline * ratio_x1000 / 100000;
> > +     dsi_reg_wr(ctx, VIDEO_SIG_DELAY_CONFIG, VIDEO_SIG_DELAY, 0, byte_cycle);
> > +     byte_cycle = hline * ratio_x1000 / 1000;
> > +     writel(byte_cycle, ctx->base + VIDEO_LINE_TIME);
> > +     byte_cycle = vm->hsync_len * ratio_x1000 / 1000;
> > +     dsi_reg_wr(ctx, VIDEO_LINE_HBLK_TIME, VIDEO_LINE_HSA_TIME, 16, byte_cycle);
> > +     byte_cycle = vm->hback_porch * ratio_x1000 / 1000;
> > +     dsi_reg_wr(ctx, VIDEO_LINE_HBLK_TIME, VIDEO_LINE_HBP_TIME, 0, byte_cycle);
> > +     writel(vm->vactive, ctx->base + VIDEO_VACTIVE_LINES);
> > +     dsi_reg_wr(ctx, VIDEO_VBLK_LINES, VFP_LINES, 0, vm->vfront_porch);
> > +     dsi_reg_wr(ctx, VIDEO_VBLK_LINES, VBP_LINES, 10, vm->vback_porch);
> > +     dsi_reg_wr(ctx, VIDEO_VBLK_LINES, VSA_LINES, 20, vm->vsync_len);
> > +     dsi_reg_up(ctx, VID_MODE_CFG, LP_HBP_EN | LP_HFP_EN | LP_VACT_EN |
> > +                     LP_VFP_EN | LP_VBP_EN | LP_VSA_EN, LP_HBP_EN | LP_HFP_EN |
> > +                     LP_VACT_EN | LP_VFP_EN | LP_VBP_EN | LP_VSA_EN);
> > +
> > +     hs_to = (hline * vm->vactive) + (2 * Bpp_x100) / 100;
> > +     for (div = 0x80; (div < hs_to) && (div > 2); div--) {
> > +             if ((hs_to % div) == 0) {
> > +                     writel(div, ctx->base + TIMEOUT_CNT_CLK_CONFIG);
> > +                     writel(hs_to / div, ctx->base + LRX_H_TO_CONFIG);
> > +                     writel(hs_to / div, ctx->base + HTX_TO_CONFIG);
> > +                     break;
> > +             }
> > +     }
> > +
> > +     if (ctx->burst_mode == VIDEO_BURST_WITH_SYNC_PULSES) {
> > +             dsi_reg_wr(ctx, VIDEO_PKT_CONFIG, VIDEO_PKT_SIZE, 0, video_size);
> > +             writel(0, ctx->base + VIDEO_NULLPKT_SIZE);
> > +             dsi_reg_up(ctx, VIDEO_PKT_CONFIG, VIDEO_LINE_CHUNK_NUM, 0);
> > +     } else {
> > +             /* non burst transmission */
> > +             null_pkt_size = 0;
> > +
> > +             /* bytes to be sent - first as one chunk */
> > +             bytes_per_chunk = vm->hactive * Bpp_x100 / 100 + pkt_header;
> > +
> > +             /* hline total bytes from the DPI interface */
> > +             total_bytes = (vm->hactive + vm->hfront_porch) *
> > +                             ratio_x1000 / dsi->slave->lanes / 1000;
> > +
> > +             /* check if the pixels actually fit on the DSI link */
> > +             if (total_bytes < bytes_per_chunk) {
> > +                     drm_err(dsi->drm, "current resolution can not be set\n");
> > +                     return -EINVAL;
> > +             }
> > +
> > +             chunk_overhead = total_bytes - bytes_per_chunk;
> > +
> > +             /* overhead higher than 1 -> enable multi packets */
> > +             if (chunk_overhead > 1) {
> > +
> > +                     /* multi packets */
> > +                     for (video_size = video_size_step;
> > +                          video_size < vm->hactive;
> > +                          video_size += video_size_step) {
> > +
> > +                             if (vm->hactive * 1000 / video_size % 1000)
> > +                                     continue;
> > +
> > +                             chunks = vm->hactive / video_size;
> > +                             bytes_per_chunk = Bpp_x100 * video_size / 100
> > +                                               + pkt_header;
> > +                             if (total_bytes >= (bytes_per_chunk * chunks)) {
> > +                                     bytes_left = total_bytes -
> > +                                                  bytes_per_chunk * chunks;
> > +                                     break;
> > +                             }
> > +                     }
> > +
> > +                     /* prevent overflow (unsigned - unsigned) */
> > +                     if (bytes_left > (pkt_header * chunks)) {
> > +                             null_pkt_size = (bytes_left -
> > +                                             pkt_header * chunks) / chunks;
> > +                             /* avoid register overflow */
> > +                             if (null_pkt_size > 1023)
> > +                                     null_pkt_size = 1023;
> > +                     }
> > +
> > +             } else {
> > +
> > +                     /* single packet */
> > +                     chunks = 1;
> > +
> > +                     /* must be a multiple of 4 except 18 loosely */
> > +                     for (video_size = vm->hactive;
> > +                         (video_size % video_size_step) != 0;
> > +                          video_size++)
> > +                             ;
> > +             }
> > +
> > +             dsi_reg_wr(ctx, VIDEO_PKT_CONFIG, VIDEO_PKT_SIZE, 0, video_size);
> > +             writel(null_pkt_size, ctx->base + VIDEO_NULLPKT_SIZE);
> > +             dsi_reg_wr(ctx, VIDEO_PKT_CONFIG, VIDEO_LINE_CHUNK_NUM, 16, chunks);
> > +     }
> > +
> > +     writel(ctx->int0_mask, ctx->base + MASK_PROTOCOL_INT);
> > +     writel(ctx->int1_mask, ctx->base + MASK_INTERNAL_INT);
> > +     writel(1, ctx->base + SOFT_RESET);
> > +
> > +     return 0;
> > +}
> > +
> > +static void sprd_dsi_edpi_video(struct dsi_context *ctx)
> > +{
> > +     struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
> > +     const u32 fifo_depth = 1096;
> > +     const u32 word_length = 4;
> > +     u32 hactive = ctx->vm.hactive;
> > +     u32 Bpp_x100;
> > +     u32 max_fifo_len;
> > +     u8 coding;
> > +
> > +     coding = fmt_to_coding(dsi->slave->format);
> > +     Bpp_x100 = calc_bytes_per_pixel_x100(coding);
> > +     max_fifo_len = word_length * fifo_depth * 100 / Bpp_x100;
> > +
> > +     writel(0, ctx->base + SOFT_RESET);
> > +     dsi_reg_wr(ctx, DPI_VIDEO_FORMAT, DPI_VIDEO_MODE_FORMAT, 0, coding);
> > +     dsi_reg_wr(ctx, CMD_MODE_CFG, TEAR_FX_EN, 0, ctx->te_ack_en);
> > +
> > +     if (max_fifo_len > hactive)
> > +             writel(hactive, ctx->base + DCS_WM_PKT_SIZE);
> > +     else
> > +             writel(max_fifo_len, ctx->base + DCS_WM_PKT_SIZE);
> > +
> > +     writel(ctx->int0_mask, ctx->base + MASK_PROTOCOL_INT);
> > +     writel(ctx->int1_mask, ctx->base + MASK_INTERNAL_INT);
> > +     writel(1, ctx->base + SOFT_RESET);
> > +}
> > +
> > +/*
> > + * Send a packet on the generic interface,
> > + * this function has an active delay to wait for the buffer to clear.
> > + * The delay is limited to:
> > + * (param_length / 4) x DSIH_FIFO_ACTIVE_WAIT x register access time
> > + * the controller restricts the sending of.
> > + *
> > + * This function will not be able to send Null and Blanking packets due to
> > + * controller restriction
> > + */
> > +static int sprd_dsi_wr_pkt(struct dsi_context *ctx, u8 vc, u8 type,
> > +                     const u8 *param, u16 len)
> > +{
> > +     struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
> > +     u8 wc_lsbyte, wc_msbyte;
> > +     u32 payload;
> > +     int i, j, ret;
> > +
> > +     if (vc > 3)
> > +             return -EINVAL;
> > +
> > +
> > +     /* 1st: for long packet, must config payload first */
> > +     ret = dsi_wait_tx_payload_fifo_empty(ctx);
> > +     if (ret) {
> > +             drm_err(dsi->drm, "tx payload fifo is not empty\n");
> > +             return ret;
> > +     }
> > +
> > +     if (len > 2) {
> > +             for (i = 0, j = 0; i < len; i += j) {
> > +                     payload = 0;
> > +                     for (j = 0; (j < 4) && ((j + i) < (len)); j++)
> > +                             payload |= param[i + j] << (j * 8);
> > +
> > +                     writel(payload, ctx->base + GEN_PLD_DATA);
> > +             }
> > +             wc_lsbyte = len & 0xff;
> > +             wc_msbyte = len >> 8;
> > +     } else {
> > +             wc_lsbyte = (len > 0) ? param[0] : 0;
> > +             wc_msbyte = (len > 1) ? param[1] : 0;
> > +     }
> > +
> > +     /* 2nd: then set packet header */
> > +     ret = dsi_wait_tx_cmd_fifo_empty(ctx);
> > +     if (ret) {
> > +             drm_err(dsi->drm, "tx cmd fifo is not empty\n");
> > +             return ret;
> > +     }
> > +
> > +     writel(type | (vc << 6) | (wc_lsbyte << 8) | (wc_msbyte << 16),
> > +                     ctx->base + GEN_HDR);
> > +
> > +     return 0;
> > +}
> > +
> > +/*
> > + * Send READ packet to peripheral using the generic interface,
> > + * this will force command mode and stop video mode (because of BTA).
> > + *
> > + * This function has an active delay to wait for the buffer to clear,
> > + * the delay is limited to 2 x DSIH_FIFO_ACTIVE_WAIT
> > + * (waiting for command buffer, and waiting for receiving)
> > + * @note this function will enable BTA
> > + */
> > +static int sprd_dsi_rd_pkt(struct dsi_context *ctx, u8 vc, u8 type,
> > +                     u8 msb_byte, u8 lsb_byte,
> > +                     u8 *buffer, u8 bytes_to_read)
> > +{
> > +     struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
> > +     int i, ret;
> > +     int count = 0;
> > +     u32 temp;
> > +
> > +     if (vc > 3)
> > +             return -EINVAL;
> > +
> > +     /* 1st: send read command to peripheral */
> > +     ret = dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_CMD_FIFO_EMPTY, 5);
> > +     if (!ret)
> > +             return -EIO;
> > +
> > +     writel(type | (vc << 6) | (lsb_byte << 8) | (msb_byte << 16),
> > +                     ctx->base + GEN_HDR);
> > +
> > +     /* 2nd: wait peripheral response completed */
> > +     ret = dsi_wait_rd_resp_completed(ctx);
> > +     if (ret) {
> > +             drm_err(dsi->drm, "wait read response time out\n");
> > +             return ret;
> > +     }
> > +
> > +     /* 3rd: get data from rx payload fifo */
> > +     ret = dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_RDATA_FIFO_EMPTY, 1);
> > +     if (ret) {
> > +             drm_err(dsi->drm, "rx payload fifo empty\n");
> > +             return -EIO;
> > +     }
> > +
> > +     for (i = 0; i < 100; i++) {
> > +             temp = readl(ctx->base + GEN_PLD_DATA);
> > +
> > +             if (count < bytes_to_read)
> > +                     buffer[count++] = temp & 0xff;
> > +             if (count < bytes_to_read)
> > +                     buffer[count++] = (temp >> 8) & 0xff;
> > +             if (count < bytes_to_read)
> > +                     buffer[count++] = (temp >> 16) & 0xff;
> > +             if (count < bytes_to_read)
> > +                     buffer[count++] = (temp >> 24) & 0xff;
> > +
> > +             ret = dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_RDATA_FIFO_EMPTY, 1);
> > +             if (ret)
> > +                     return count;
> > +     }
> > +
> > +     return 0;
> > +}
> > +
> > +static void sprd_dsi_set_work_mode(struct dsi_context *ctx, u8 mode)
> > +{
> > +     if (mode == DSI_MODE_CMD)
> > +             writel(1, ctx->base + DSI_MODE_CFG);
> > +     else
> > +             writel(0, ctx->base + DSI_MODE_CFG);
> > +}
> > +
> > +static void sprd_dsi_lp_cmd_enable(struct dsi_context *ctx)
> > +{
> > +     if (readl(ctx->base + DSI_MODE_CFG))
> > +             dsi_reg_up(ctx, CMD_MODE_CFG, GEN_SW_0P_TX | GEN_SW_1P_TX |
> > +                     GEN_SW_2P_TX | GEN_SR_0P_TX | GEN_SR_1P_TX | GEN_SR_2P_TX |
> > +                     GEN_LW_TX | DCS_SW_0P_TX | DCS_SW_1P_TX | DCS_SR_0P_TX |
> > +                     DCS_LW_TX | MAX_RD_PKT_SIZE, GEN_SW_0P_TX | GEN_SW_1P_TX |
> > +                     GEN_SW_2P_TX | GEN_SR_0P_TX | GEN_SR_1P_TX | GEN_SR_2P_TX |
> > +                     GEN_LW_TX | DCS_SW_0P_TX | DCS_SW_1P_TX | DCS_SR_0P_TX |
> > +                     DCS_LW_TX | MAX_RD_PKT_SIZE);
> > +     else
> > +             dsi_reg_up(ctx, VID_MODE_CFG, LP_CMD_EN, LP_CMD_EN);
> > +}
> > +
> > +static void sprd_dsi_state_reset(struct dsi_context *ctx)
> > +{
> > +     writel(0, ctx->base + SOFT_RESET);
> > +     udelay(100);
> > +     writel(1, ctx->base + SOFT_RESET);
> > +}
> > +
> > +static int sprd_dphy_init(struct dsi_context *ctx)
> > +{
> > +     struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
> > +     int ret;
> > +
> > +     dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_RESET_N, 0);
> > +     dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_SHUTDOWN, 0);
> > +     dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_CLK_EN, 0);
> > +
> > +     dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLR, 0);
> > +     dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLR, PHY_TESTCLR);
> > +     dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLR, 0);
> > +
> > +     dphy_pll_config(ctx);
> > +     dphy_timing_config(ctx);
> > +
> > +     dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_SHUTDOWN, RF_PHY_SHUTDOWN);
> > +     dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_RESET_N, RF_PHY_RESET_N);
> > +     writel(0x1C, ctx->base + PHY_MIN_STOP_TIME);
> > +     dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_CLK_EN, RF_PHY_CLK_EN);
> > +     writel(dsi->slave->lanes - 1, ctx->base + PHY_LANE_NUM_CONFIG);
> > +
> > +     ret = dphy_wait_pll_locked(ctx);
> > +     if (ret) {
> > +             drm_err(dsi->drm, "dphy initial failed\n");
> > +             return ret;
> > +     }
> > +
> > +     return 0;
> > +}
> > +
> > +static void sprd_dphy_fini(struct dsi_context *ctx)
> > +{
> > +     dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_RESET_N, 0);
> > +     dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_SHUTDOWN, 0);
> > +     dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_RESET_N, RF_PHY_RESET_N);
> > +}
> > +
> > +static void sprd_dsi_encoder_enable(struct drm_encoder *encoder)
> > +{
> > +     struct sprd_dsi *dsi = encoder_to_dsi(encoder);
> > +     struct sprd_dpu *dpu = to_sprd_crtc(encoder->crtc);
> > +     struct dsi_context *ctx = &dsi->ctx;
> > +
> > +     if (ctx->enabled) {
> > +             drm_warn(dsi->drm, "dsi is initialized\n");
> > +             return;
> > +     }
> > +
> > +     sprd_dsi_init(ctx);
> > +     if (ctx->work_mode == DSI_MODE_VIDEO)
> > +             sprd_dsi_dpi_video(ctx);
> > +     else
> > +             sprd_dsi_edpi_video(ctx);
> > +
> > +     sprd_dphy_init(ctx);
> > +
> > +     sprd_dsi_lp_cmd_enable(ctx);
> > +
> > +     if (dsi->panel) {
> > +             drm_panel_prepare(dsi->panel);
> > +             drm_panel_enable(dsi->panel);
> > +     }
>
> Please use the new devm_drm_of_get_bridge helper here, and use the
> bridge API instead.
We use drm_panel_init and drm_panel_add API to add panel, so here is a
panel device, not a bridge.
>
> > +     sprd_dsi_set_work_mode(ctx, ctx->work_mode);
> > +     sprd_dsi_state_reset(ctx);
> > +
> > +     if (dsi->slave->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
> > +             dsi_reg_up(ctx, PHY_CLK_LANE_LP_CTRL, AUTO_CLKLANE_CTRL_EN,
> > +                             AUTO_CLKLANE_CTRL_EN);
> > +     else {
> > +             dsi_reg_up(ctx, PHY_CLK_LANE_LP_CTRL, RF_PHY_CLK_EN, RF_PHY_CLK_EN);
> > +             dsi_reg_up(ctx, PHY_CLK_LANE_LP_CTRL, PHY_CLKLANE_TX_REQ_HS,
> > +                             PHY_CLKLANE_TX_REQ_HS);
> > +             dphy_wait_pll_locked(ctx);
> > +     }
> > +
> > +     sprd_dpu_run(dpu);
> > +
> > +     ctx->enabled = true;
> > +}
> > +
> > +static void sprd_dsi_encoder_disable(struct drm_encoder *encoder)
> > +{
> > +     struct sprd_dsi *dsi = encoder_to_dsi(encoder);
> > +     struct sprd_dpu *dpu = to_sprd_crtc(encoder->crtc);
> > +     struct dsi_context *ctx = &dsi->ctx;
> > +
> > +     if (!ctx->enabled) {
> > +             drm_warn(dsi->drm, "dsi isn't initialized\n");
> > +             return;
> > +     }
> > +
> > +     sprd_dpu_stop(dpu);
> > +     sprd_dsi_set_work_mode(ctx, DSI_MODE_CMD);
> > +     sprd_dsi_lp_cmd_enable(ctx);
> > +
> > +     if (dsi->panel) {
> > +             drm_panel_disable(dsi->panel);
> > +             drm_panel_unprepare(dsi->panel);
> > +     }
> > +
> > +     sprd_dphy_fini(ctx);
> > +     sprd_dsi_fini(ctx);
> > +
> > +     ctx->enabled = false;
> > +}
> > +
> > +static void sprd_dsi_encoder_mode_set(struct drm_encoder *encoder,
> > +                              struct drm_display_mode *mode,
> > +                              struct drm_display_mode *adj_mode)
> > +{
> > +     struct sprd_dsi *dsi = encoder_to_dsi(encoder);
> > +
> > +     drm_dbg(dsi->drm, "%s() set mode: %s\n", __func__, dsi->mode->name);
> > +}
>
> You don't need that function?
No need for now. need to delete it?
>
> > +static int sprd_dsi_encoder_atomic_check(struct drm_encoder *encoder,
> > +                                 struct drm_crtc_state *crtc_state,
> > +                                 struct drm_connector_state *conn_state)
> > +{
> > +     return 0;
> > +}
>
> Ditto
No need for now. need to delete it?
>
> > +static const struct drm_encoder_helper_funcs sprd_encoder_helper_funcs = {
> > +     .atomic_check   = sprd_dsi_encoder_atomic_check,
> > +     .mode_set       = sprd_dsi_encoder_mode_set,
> > +     .enable         = sprd_dsi_encoder_enable,
> > +     .disable        = sprd_dsi_encoder_disable
> > +};
> > +
> > +static const struct drm_encoder_funcs sprd_encoder_funcs = {
> > +     .destroy = drm_encoder_cleanup,
> > +};
> > +
> > +static struct sprd_dsi *sprd_dsi_encoder_init(struct drm_device *drm,
> > +                            struct device *dev)
> > +{
> > +     struct sprd_dsi *dsi;
> > +     u32 crtc_mask;
> > +
> > +     crtc_mask = drm_of_find_possible_crtcs(drm, dev->of_node);
> > +     if (!crtc_mask) {
> > +             drm_err(drm, "failed to find crtc mask\n");
> > +             return ERR_PTR(-EINVAL);
> > +     }
> > +
> > +     drm_dbg(drm, "find possible crtcs: 0x%08x\n", crtc_mask);
> > +
> > +     dsi = drmm_encoder_alloc(drm, struct sprd_dsi, encoder,
> > +                            &sprd_encoder_funcs, DRM_MODE_ENCODER_DSI, NULL);
> > +     if (IS_ERR(dsi)) {
> > +             drm_err(drm, "failed to init dsi encoder.\n");
> > +             return dsi;
> > +     }
> > +
> > +     dsi->encoder.possible_crtcs = crtc_mask;
> > +     drm_encoder_helper_add(&dsi->encoder, &sprd_encoder_helper_funcs);
> > +
> > +     return dsi;
> > +}
> > +
> > +static int sprd_dsi_find_panel(struct sprd_dsi *dsi)
> > +{
> > +     struct device *dev = dsi->host.dev;
> > +     struct device_node *child, *lcds_node;
> > +     struct drm_panel *panel;
> > +
> > +     /* search /lcds child node first */
> > +     lcds_node = of_find_node_by_path("/lcds");
> > +     for_each_child_of_node(lcds_node, child) {
> > +             panel = of_drm_find_panel(child);
> > +             if (!IS_ERR(panel)) {
> > +                     dsi->panel = panel;
> > +                     return 0;
> > +             }
> > +     }
> > +
> > +     /*
> > +      * If /lcds child node search failed, we search
> > +      * the child of dsi host node.
> > +      */
> > +     for_each_child_of_node(dev->of_node, child) {
> > +             panel = of_drm_find_panel(child);
> > +             if (!IS_ERR(panel)) {
> > +                     dsi->panel = panel;
> > +                     return 0;
> > +             }
> > +     }
> > +
> > +     drm_err(dsi->drm, "of_drm_find_panel() failed\n");
> > +     return -ENODEV;
> > +}
>
> Just use devm_drm_of_get_bridge there
We use drm_panel_init and drm_panel_add API to add panel, so here is a
panel device, not a bridge.
>
> > +static int sprd_dsi_host_attach(struct mipi_dsi_host *host,
> > +                        struct mipi_dsi_device *slave)
> > +{
> > +     struct sprd_dsi *dsi = host_to_dsi(host);
> > +     struct dsi_context *ctx = &dsi->ctx;
> > +     int ret;
> > +
> > +     dsi->slave = slave;
> > +
> > +     if (slave->mode_flags & MIPI_DSI_MODE_VIDEO)
> > +             ctx->work_mode = DSI_MODE_VIDEO;
> > +     else
> > +             ctx->work_mode = DSI_MODE_CMD;
> > +
> > +     if (slave->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
> > +             ctx->burst_mode = VIDEO_BURST_WITH_SYNC_PULSES;
> > +     else if (slave->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
> > +             ctx->burst_mode = VIDEO_NON_BURST_WITH_SYNC_PULSES;
> > +     else
> > +             ctx->burst_mode = VIDEO_NON_BURST_WITH_SYNC_EVENTS;
> > +
> > +     ret = sprd_dsi_find_panel(dsi);
> > +     if (ret)
> > +             return ret;
> > +
> > +     return 0;
> > +}
> > +
> > +static int sprd_dsi_host_detach(struct mipi_dsi_host *host,
> > +                        struct mipi_dsi_device *slave)
> > +{
> > +     /* do nothing */
> > +     return 0;
> > +}
> > +
> > +static ssize_t sprd_dsi_host_transfer(struct mipi_dsi_host *host,
> > +                             const struct mipi_dsi_msg *msg)
> > +{
> > +     struct sprd_dsi *dsi = host_to_dsi(host);
> > +     const u8 *tx_buf = msg->tx_buf;
> > +
> > +     if (msg->rx_buf && msg->rx_len) {
> > +             u8 lsb = (msg->tx_len > 0) ? tx_buf[0] : 0;
> > +             u8 msb = (msg->tx_len > 1) ? tx_buf[1] : 0;
> > +
> > +             return sprd_dsi_rd_pkt(&dsi->ctx, msg->channel, msg->type,
> > +                             msb, lsb, msg->rx_buf, msg->rx_len);
> > +     }
> > +
> > +     if (msg->tx_buf && msg->tx_len)
> > +             return sprd_dsi_wr_pkt(&dsi->ctx, msg->channel, msg->type,
> > +                                     tx_buf, msg->tx_len);
> > +
> > +     return 0;
> > +}
> > +
> > +static const struct mipi_dsi_host_ops sprd_dsi_host_ops = {
> > +     .attach = sprd_dsi_host_attach,
> > +     .detach = sprd_dsi_host_detach,
> > +     .transfer = sprd_dsi_host_transfer,
> > +};
> > +
> > +static int sprd_dsi_host_init(struct sprd_dsi *dsi, struct device *dev)
> > +{
> > +     int ret;
> > +
> > +     dsi->host.dev = dev;
> > +     dsi->host.ops = &sprd_dsi_host_ops;
> > +
> > +     ret = mipi_dsi_host_register(&dsi->host);
> > +     if (ret)
> > +             drm_err(dsi->drm, "failed to register dsi host\n");
> > +
> > +     return ret;
> > +}
> > +
> > +static int sprd_dsi_connector_get_modes(struct drm_connector *connector)
> > +{
> > +     struct sprd_dsi *dsi = connector_to_dsi(connector);
> > +
> > +     return drm_panel_get_modes(dsi->panel, connector);
> > +}
> > +
> > +static enum drm_mode_status
> > +sprd_dsi_connector_mode_valid(struct drm_connector *connector,
> > +                      struct drm_display_mode *mode)
> > +{
> > +     struct sprd_dsi *dsi = connector_to_dsi(connector);
> > +
> > +     drm_dbg(dsi->drm, "%s() mode: "DRM_MODE_FMT"\n", __func__, DRM_MODE_ARG(mode));
> > +
> > +     if (mode->type & DRM_MODE_TYPE_PREFERRED) {
> > +             dsi->mode = mode;
> > +             drm_display_mode_to_videomode(dsi->mode, &dsi->ctx.vm);
> > +     }
>
> I already told you this, but you shouldn't modify your state in
> mode_valid, and certainly not based on whether it's the preferred mode
> or not.
Sorry, I have modified the CRTC driver, and the encoder driver is
missing, i will fix it, thks.
>
> > +     return MODE_OK;
> > +}
> > +
> > +static struct drm_encoder *
> > +sprd_dsi_connector_best_encoder(struct drm_connector *connector)
> > +{
> > +     struct sprd_dsi *dsi = connector_to_dsi(connector);
> > +
> > +     return &dsi->encoder;
> > +}
> > +
> > +static struct drm_connector_helper_funcs sprd_dsi_connector_helper_funcs = {
> > +     .get_modes = sprd_dsi_connector_get_modes,
> > +     .mode_valid = sprd_dsi_connector_mode_valid,
> > +     .best_encoder = sprd_dsi_connector_best_encoder,
> > +};
> > +
> > +static enum drm_connector_status
> > +sprd_dsi_connector_detect(struct drm_connector *connector, bool force)
> > +{
> > +     struct sprd_dsi *dsi = connector_to_dsi(connector);
> > +
> > +     if (dsi->panel) {
> > +             drm_panel_add(dsi->panel);
> > +             return connector_status_connected;
> > +     }
> > +
> > +     return connector_status_disconnected;
> > +}
> > +
> > +static void sprd_dsi_connector_destroy(struct drm_connector *connector)
> > +{
> > +     drm_connector_unregister(connector);
> > +     drm_connector_cleanup(connector);
> > +}
> > +
> > +static const struct drm_connector_funcs sprd_dsi_atomic_connector_funcs = {
> > +     .fill_modes = drm_helper_probe_single_connector_modes,
> > +     .detect = sprd_dsi_connector_detect,
> > +     .destroy = sprd_dsi_connector_destroy,
> > +     .reset = drm_atomic_helper_connector_reset,
> > +     .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
> > +     .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> > +};
> > +
> > +static int sprd_dsi_connector_init(struct drm_device *drm, struct sprd_dsi *dsi)
> > +{
> > +     struct drm_encoder *encoder = &dsi->encoder;
> > +     struct drm_connector *connector = &dsi->connector;
> > +     int ret;
> > +
> > +     connector->polled = DRM_CONNECTOR_POLL_HPD;
> > +
> > +     ret = drm_connector_init(drm, connector,
> > +                              &sprd_dsi_atomic_connector_funcs,
> > +                              DRM_MODE_CONNECTOR_DSI);
> > +     if (ret) {
> > +             drm_err(drm, "drm_connector_init() failed\n");
> > +             return ret;
> > +     }
> > +
> > +     drm_connector_helper_add(connector,
> > +                              &sprd_dsi_connector_helper_funcs);
> > +
> > +     drm_connector_attach_encoder(connector, encoder);
> > +
> > +     return 0;
> > +}
> > +
> > +static int sprd_dsi_context_init(struct sprd_dsi *dsi,
> > +                     struct device *dev)
> > +{
> > +     struct platform_device *pdev = to_platform_device(dev);
> > +     struct dsi_context *ctx = &dsi->ctx;
> > +     struct resource *res;
> > +
> > +     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +     ctx->base = devm_ioremap(dev, res->start, resource_size(res));
> > +     if (!ctx->base) {
> > +             drm_err(dsi->drm, "failed to map dsi host registers\n");
> > +             return -ENXIO;
> > +     }
> > +
> > +     ctx->pll = devm_kzalloc(dev, sizeof(*ctx->pll), GFP_KERNEL);
> > +     if (!ctx->pll)
> > +             return -ENOMEM;
> > +
> > +     ctx->regmap = devm_regmap_init(dev, &regmap_tst_io, dsi, &byte_config);
> > +     if (IS_ERR(ctx->regmap)) {
> > +             drm_err(dsi->drm, "dphy regmap init failed\n");
> > +             return PTR_ERR(ctx->regmap);
> > +     }
> > +
> > +     ctx->data_hs2lp = 120;
> > +     ctx->data_lp2hs = 500;
> > +     ctx->clk_hs2lp = 4;
> > +     ctx->clk_lp2hs = 15;
> > +     ctx->max_rd_time = 6000;
> > +     ctx->int0_mask = 0xffffffff;
> > +     ctx->int1_mask = 0xffffffff;
> > +     ctx->enabled = true;
> > +
> > +     return 0;
> > +}
> > +
> > +static int sprd_dsi_bind(struct device *dev, struct device *master, void *data)
> > +{
> > +     struct drm_device *drm = data;
> > +     struct sprd_dsi *dsi;
> > +     int ret;
> > +
> > +     dsi = sprd_dsi_encoder_init(drm, dev);
> > +     if (IS_ERR(dsi))
> > +             return PTR_ERR(dsi);
> > +
> > +     dsi->drm = drm;
> > +     dev_set_drvdata(dev, dsi);
> > +
> > +     ret = sprd_dsi_connector_init(drm, dsi);
> > +     if (ret)
> > +             return ret;
> > +
> > +     ret = sprd_dsi_context_init(dsi, dev);
> > +     if (ret)
> > +             return ret;
> > +
> > +     ret = sprd_dsi_host_init(dsi, dev);
> > +     if (ret)
> > +             return ret;
> > +
> > +     return 0;
> > +}
> > +
> > +static void sprd_dsi_unbind(struct device *dev,
> > +                     struct device *master, void *data)
> > +{
> > +     struct sprd_dsi *dsi = dev_get_drvdata(dev);
> > +
> > +     mipi_dsi_host_unregister(&dsi->host);
> > +}
> > +
> > +static const struct component_ops dsi_component_ops = {
> > +     .bind   = sprd_dsi_bind,
> > +     .unbind = sprd_dsi_unbind,
> > +};
> > +
> > +static const struct of_device_id dsi_match_table[] = {
> > +     { .compatible = "sprd,sharkl3-dsi-host" },
> > +     { /* sentinel */ },
> > +};
> > +
> > +static int sprd_dsi_probe(struct platform_device *pdev)
> > +{
> > +     return component_add(&pdev->dev, &dsi_component_ops);
>
> In order to prevent probe issues, you need to register you mipi_dsi_host
> here, see:
> https://lore.kernel.org/dri-devel/20210910101218.1632297-3-maxime@cerno.tech/
We register mipi_dsi_hot on our panel driver, like this:

1092   ret = mipi_dsi_attach(slave);
1093   if (ret) {
1094   DRM_ERROR("failed to attach dsi panel to host\n");
1095   drm_panel_remove(&panel->base);
1096   return ret;
1097   }

>
> Maxime

Re: [PATCH v6 6/6] drm/sprd: add Unisoc's drm mipi dsi&dphy driver

[Sam Ravnborg]

Hi Kevin,

> > > +     reg->_0b.bits.out_sel = pll->out_sel;
> > > +     reg->_0b.bits.kint_l = pll->kint & 0xf;
> > > +     reg->_0e.bits.pll_pu_byp = 0;
> > > +     reg->_0e.bits.pll_pu = 0;
> > > +     reg->_0e.bits.stopstate_sel = 1;
> > > +     reg->_0f.bits.det_delay = pll->det_delay;
> > > +
> > > +     val = (u8 *)®
> > > +
> > > +     for (i = 0; i < sizeof(reg_addr); ++i) {
> > > +             regmap_write(regmap, reg_addr[i], val[i]);
> > > +             DRM_DEBUG("%02x: %02x\n", reg_addr[i], val[i]);
> > > +     }
> > > +}
> >
> > It would be great to also convert this part to a pattern without
> > structures.
> I will try it, but our pll registers, all not have official name from
> aisc design owner.
> If need to convert it, our pll regiters macro define, it can only be
> named as reg_01, reg_02...
IT is better to use the stupid names provided by you asic design owner,
than just numbers. Add a comment explaining this is due to the asic
design owner the names are stupid and not your fault.

> > > +
> > > +     if (dsi->panel) {
> > > +             drm_panel_prepare(dsi->panel);
> > > +             drm_panel_enable(dsi->panel);
> > > +     }
> >
> > Please use the new devm_drm_of_get_bridge helper here, and use the
> > bridge API instead.
> We use drm_panel_init and drm_panel_add API to add panel, so here is a
> panel device, not a bridge.

The new way to do this is to always wrap the panel in a bridge. We will
start to slowly migrate away from direct use of the panel API, and let
display drivers always wrap the panles in a bridge.
So please do as Maxime suggests.

	Sam

Re: [PATCH v6 6/6] drm/sprd: add Unisoc's drm mipi dsi&dphy driver

[Maxime Ripard]

On Sun, Sep 26, 2021 at 10:31:53PM +0800, Kevin Tang wrote:
> Maxime Ripard <maxime@cerno.tech> 于2021年9月17日周五 下午11:40写道：
> > > +static void sprd_dsi_encoder_mode_set(struct drm_encoder *encoder,
> > > +                              struct drm_display_mode *mode,
> > > +                              struct drm_display_mode *adj_mode)
> > > +{
> > > +     struct sprd_dsi *dsi = encoder_to_dsi(encoder);
> > > +
> > > +     drm_dbg(dsi->drm, "%s() set mode: %s\n", __func__, dsi->mode->name);
> > > +}
> >
> > You don't need that function?
> No need for now. need to delete it?

Yes

> > > +static int sprd_dsi_encoder_atomic_check(struct drm_encoder *encoder,
> > > +                                 struct drm_crtc_state *crtc_state,
> > > +                                 struct drm_connector_state *conn_state)
> > > +{
> > > +     return 0;
> > > +}
> >
> > Ditto
>
> No need for now. need to delete it?

Yep

> > > +static int sprd_dsi_find_panel(struct sprd_dsi *dsi)
> > > +{
> > > +     struct device *dev = dsi->host.dev;
> > > +     struct device_node *child, *lcds_node;
> > > +     struct drm_panel *panel;
> > > +
> > > +     /* search /lcds child node first */
> > > +     lcds_node = of_find_node_by_path("/lcds");
> > > +     for_each_child_of_node(lcds_node, child) {
> > > +             panel = of_drm_find_panel(child);
> > > +             if (!IS_ERR(panel)) {
> > > +                     dsi->panel = panel;
> > > +                     return 0;
> > > +             }
> > > +     }
> > > +
> > > +     /*
> > > +      * If /lcds child node search failed, we search
> > > +      * the child of dsi host node.
> > > +      */
> > > +     for_each_child_of_node(dev->of_node, child) {
> > > +             panel = of_drm_find_panel(child);
> > > +             if (!IS_ERR(panel)) {
> > > +                     dsi->panel = panel;
> > > +                     return 0;
> > > +             }
> > > +     }
> > > +
> > > +     drm_err(dsi->drm, "of_drm_find_panel() failed\n");
> > > +     return -ENODEV;
> > > +}
> >
> > Just use devm_drm_of_get_bridge there
>
> We use drm_panel_init and drm_panel_add API to add panel, so here is a
> panel device, not a bridge.

Like Sam said, the panel API is on its way out and is being superseded
by bridge_panels.

> > > +static int sprd_dsi_host_init(struct sprd_dsi *dsi, struct device *dev)
> > > +{
> > > +     int ret;
> > > +
> > > +     dsi->host.dev = dev;
> > > +     dsi->host.ops = &sprd_dsi_host_ops;
> > > +
> > > +     ret = mipi_dsi_host_register(&dsi->host);
> > > +     if (ret)
> > > +             drm_err(dsi->drm, "failed to register dsi host\n");
> > > +
> > > +     return ret;
> > > +}
> > >
> > > [...]
> > >
> > > +static int sprd_dsi_connector_init(struct drm_device *drm, struct sprd_dsi *dsi)
> > > +{
> > > +     struct drm_encoder *encoder = &dsi->encoder;
> > > +     struct drm_connector *connector = &dsi->connector;
> > > +     int ret;
> > > +
> > > +     connector->polled = DRM_CONNECTOR_POLL_HPD;
> > > +
> > > +     ret = drm_connector_init(drm, connector,
> > > +                              &sprd_dsi_atomic_connector_funcs,
> > > +                              DRM_MODE_CONNECTOR_DSI);
> > > +     if (ret) {
> > > +             drm_err(drm, "drm_connector_init() failed\n");
> > > +             return ret;
> > > +     }
> > > +
> > > +     drm_connector_helper_add(connector,
> > > +                              &sprd_dsi_connector_helper_funcs);
> > > +
> > > +     drm_connector_attach_encoder(connector, encoder);
> > > +
> > > +     return 0;
> > > +}
> > > +
> > > +static int sprd_dsi_context_init(struct sprd_dsi *dsi,
> > > +                     struct device *dev)
> > > +{
> > > +     struct platform_device *pdev = to_platform_device(dev);
> > > +     struct dsi_context *ctx = &dsi->ctx;
> > > +     struct resource *res;
> > > +
> > > +     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > > +     ctx->base = devm_ioremap(dev, res->start, resource_size(res));
> > > +     if (!ctx->base) {
> > > +             drm_err(dsi->drm, "failed to map dsi host registers\n");
> > > +             return -ENXIO;
> > > +     }
> > > +
> > > +     ctx->pll = devm_kzalloc(dev, sizeof(*ctx->pll), GFP_KERNEL);
> > > +     if (!ctx->pll)
> > > +             return -ENOMEM;
> > > +
> > > +     ctx->regmap = devm_regmap_init(dev, &regmap_tst_io, dsi, &byte_config);
> > > +     if (IS_ERR(ctx->regmap)) {
> > > +             drm_err(dsi->drm, "dphy regmap init failed\n");
> > > +             return PTR_ERR(ctx->regmap);
> > > +     }
> > > +
> > > +     ctx->data_hs2lp = 120;
> > > +     ctx->data_lp2hs = 500;
> > > +     ctx->clk_hs2lp = 4;
> > > +     ctx->clk_lp2hs = 15;
> > > +     ctx->max_rd_time = 6000;
> > > +     ctx->int0_mask = 0xffffffff;
> > > +     ctx->int1_mask = 0xffffffff;
> > > +     ctx->enabled = true;
> > > +
> > > +     return 0;
> > > +}
> > > +
> > > +static int sprd_dsi_bind(struct device *dev, struct device *master, void *data)
> > > +{
> > > +     struct drm_device *drm = data;
> > > +     struct sprd_dsi *dsi;
> > > +     int ret;
> > > +
> > > +     dsi = sprd_dsi_encoder_init(drm, dev);
> > > +     if (IS_ERR(dsi))
> > > +             return PTR_ERR(dsi);
> > > +
> > > +     dsi->drm = drm;
> > > +     dev_set_drvdata(dev, dsi);
> > > +
> > > +     ret = sprd_dsi_connector_init(drm, dsi);
> > > +     if (ret)
> > > +             return ret;
> > > +
> > > +     ret = sprd_dsi_context_init(dsi, dev);
> > > +     if (ret)
> > > +             return ret;
> > > +
> > > +     ret = sprd_dsi_host_init(dsi, dev);
> > > +     if (ret)
> > > +             return ret;
> > > +
> > > +     return 0;
> > > +}
> > > +
> > > +static void sprd_dsi_unbind(struct device *dev,
> > > +                     struct device *master, void *data)
> > > +{
> > > +     struct sprd_dsi *dsi = dev_get_drvdata(dev);
> > > +
> > > +     mipi_dsi_host_unregister(&dsi->host);
> > > +}
> > > +
> > > +static const struct component_ops dsi_component_ops = {
> > > +     .bind   = sprd_dsi_bind,
> > > +     .unbind = sprd_dsi_unbind,
> > > +};
> > > +
> > > +static const struct of_device_id dsi_match_table[] = {
> > > +     { .compatible = "sprd,sharkl3-dsi-host" },
> > > +     { /* sentinel */ },
> > > +};
> > > +
> > > +static int sprd_dsi_probe(struct platform_device *pdev)
> > > +{
> > > +     return component_add(&pdev->dev, &dsi_component_ops);
> >
> > In order to prevent probe issues, you need to register you mipi_dsi_host
> > here, see:
> > https://lore.kernel.org/dri-devel/20210910101218.1632297-3-maxime@cerno.tech/
>
> We register mipi_dsi_hot on our panel driver, like this:
> 
> 1092   ret = mipi_dsi_attach(slave);
> 1093   if (ret) {
> 1094   DRM_ERROR("failed to attach dsi panel to host\n");
> 1095   drm_panel_remove(&panel->base);
> 1096   return ret;
> 1097   }

It's not about when you attach, but when you call
mipi_dsi_host_register. You're doing it in sprd_dsi_host_init that you
call in bind(), which is against the best practices and will create
probing issues in the future.

Maxime

Re: [PATCH v6 6/6] drm/sprd: add Unisoc's drm mipi dsi&dphy driver

[Kevin Tang]

Maxime Ripard <maxime@cerno.tech> 于2021年9月28日周二 下午5:28写道：
>
> On Sun, Sep 26, 2021 at 10:31:53PM +0800, Kevin Tang wrote:
> > Maxime Ripard <maxime@cerno.tech> 于2021年9月17日周五 下午11:40写道：
> > > > +static void sprd_dsi_encoder_mode_set(struct drm_encoder *encoder,
> > > > +                              struct drm_display_mode *mode,
> > > > +                              struct drm_display_mode *adj_mode)
> > > > +{
> > > > +     struct sprd_dsi *dsi = encoder_to_dsi(encoder);
> > > > +
> > > > +     drm_dbg(dsi->drm, "%s() set mode: %s\n", __func__, dsi->mode->name);
> > > > +}
> > >
> > > You don't need that function?
> > No need for now. need to delete it?
>
> Yes
>
> > > > +static int sprd_dsi_encoder_atomic_check(struct drm_encoder *encoder,
> > > > +                                 struct drm_crtc_state *crtc_state,
> > > > +                                 struct drm_connector_state *conn_state)
> > > > +{
> > > > +     return 0;
> > > > +}
> > >
> > > Ditto
> >
> > No need for now. need to delete it?
>
> Yep
>
> > > > +static int sprd_dsi_find_panel(struct sprd_dsi *dsi)
> > > > +{
> > > > +     struct device *dev = dsi->host.dev;
> > > > +     struct device_node *child, *lcds_node;
> > > > +     struct drm_panel *panel;
> > > > +
> > > > +     /* search /lcds child node first */
> > > > +     lcds_node = of_find_node_by_path("/lcds");
> > > > +     for_each_child_of_node(lcds_node, child) {
> > > > +             panel = of_drm_find_panel(child);
> > > > +             if (!IS_ERR(panel)) {
> > > > +                     dsi->panel = panel;
> > > > +                     return 0;
> > > > +             }
> > > > +     }
> > > > +
> > > > +     /*
> > > > +      * If /lcds child node search failed, we search
> > > > +      * the child of dsi host node.
> > > > +      */
> > > > +     for_each_child_of_node(dev->of_node, child) {
> > > > +             panel = of_drm_find_panel(child);
> > > > +             if (!IS_ERR(panel)) {
> > > > +                     dsi->panel = panel;
> > > > +                     return 0;
> > > > +             }
> > > > +     }
> > > > +
> > > > +     drm_err(dsi->drm, "of_drm_find_panel() failed\n");
> > > > +     return -ENODEV;
> > > > +}
> > >
> > > Just use devm_drm_of_get_bridge there
> >
> > We use drm_panel_init and drm_panel_add API to add panel, so here is a
> > panel device, not a bridge.
>
> Like Sam said, the panel API is on its way out and is being superseded
> by bridge_panels.
Ok, i will try it.
>
> > > > +static int sprd_dsi_host_init(struct sprd_dsi *dsi, struct device *dev)
> > > > +{
> > > > +     int ret;
> > > > +
> > > > +     dsi->host.dev = dev;
> > > > +     dsi->host.ops = &sprd_dsi_host_ops;
> > > > +
> > > > +     ret = mipi_dsi_host_register(&dsi->host);
> > > > +     if (ret)
> > > > +             drm_err(dsi->drm, "failed to register dsi host\n");
> > > > +
> > > > +     return ret;
> > > > +}
> > > >
> > > > [...]
> > > >
> > > > +static int sprd_dsi_connector_init(struct drm_device *drm, struct sprd_dsi *dsi)
> > > > +{
> > > > +     struct drm_encoder *encoder = &dsi->encoder;
> > > > +     struct drm_connector *connector = &dsi->connector;
> > > > +     int ret;
> > > > +
> > > > +     connector->polled = DRM_CONNECTOR_POLL_HPD;
> > > > +
> > > > +     ret = drm_connector_init(drm, connector,
> > > > +                              &sprd_dsi_atomic_connector_funcs,
> > > > +                              DRM_MODE_CONNECTOR_DSI);
> > > > +     if (ret) {
> > > > +             drm_err(drm, "drm_connector_init() failed\n");
> > > > +             return ret;
> > > > +     }
> > > > +
> > > > +     drm_connector_helper_add(connector,
> > > > +                              &sprd_dsi_connector_helper_funcs);
> > > > +
> > > > +     drm_connector_attach_encoder(connector, encoder);
> > > > +
> > > > +     return 0;
> > > > +}
> > > > +
> > > > +static int sprd_dsi_context_init(struct sprd_dsi *dsi,
> > > > +                     struct device *dev)
> > > > +{
> > > > +     struct platform_device *pdev = to_platform_device(dev);
> > > > +     struct dsi_context *ctx = &dsi->ctx;
> > > > +     struct resource *res;
> > > > +
> > > > +     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > > > +     ctx->base = devm_ioremap(dev, res->start, resource_size(res));
> > > > +     if (!ctx->base) {
> > > > +             drm_err(dsi->drm, "failed to map dsi host registers\n");
> > > > +             return -ENXIO;
> > > > +     }
> > > > +
> > > > +     ctx->pll = devm_kzalloc(dev, sizeof(*ctx->pll), GFP_KERNEL);
> > > > +     if (!ctx->pll)
> > > > +             return -ENOMEM;
> > > > +
> > > > +     ctx->regmap = devm_regmap_init(dev, &regmap_tst_io, dsi, &byte_config);
> > > > +     if (IS_ERR(ctx->regmap)) {
> > > > +             drm_err(dsi->drm, "dphy regmap init failed\n");
> > > > +             return PTR_ERR(ctx->regmap);
> > > > +     }
> > > > +
> > > > +     ctx->data_hs2lp = 120;
> > > > +     ctx->data_lp2hs = 500;
> > > > +     ctx->clk_hs2lp = 4;
> > > > +     ctx->clk_lp2hs = 15;
> > > > +     ctx->max_rd_time = 6000;
> > > > +     ctx->int0_mask = 0xffffffff;
> > > > +     ctx->int1_mask = 0xffffffff;
> > > > +     ctx->enabled = true;
> > > > +
> > > > +     return 0;
> > > > +}
> > > > +
> > > > +static int sprd_dsi_bind(struct device *dev, struct device *master, void *data)
> > > > +{
> > > > +     struct drm_device *drm = data;
> > > > +     struct sprd_dsi *dsi;
> > > > +     int ret;
> > > > +
> > > > +     dsi = sprd_dsi_encoder_init(drm, dev);
> > > > +     if (IS_ERR(dsi))
> > > > +             return PTR_ERR(dsi);
> > > > +
> > > > +     dsi->drm = drm;
> > > > +     dev_set_drvdata(dev, dsi);
> > > > +
> > > > +     ret = sprd_dsi_connector_init(drm, dsi);
> > > > +     if (ret)
> > > > +             return ret;
> > > > +
> > > > +     ret = sprd_dsi_context_init(dsi, dev);
> > > > +     if (ret)
> > > > +             return ret;
> > > > +
> > > > +     ret = sprd_dsi_host_init(dsi, dev);
> > > > +     if (ret)
> > > > +             return ret;
> > > > +
> > > > +     return 0;
> > > > +}
> > > > +
> > > > +static void sprd_dsi_unbind(struct device *dev,
> > > > +                     struct device *master, void *data)
> > > > +{
> > > > +     struct sprd_dsi *dsi = dev_get_drvdata(dev);
> > > > +
> > > > +     mipi_dsi_host_unregister(&dsi->host);
> > > > +}
> > > > +
> > > > +static const struct component_ops dsi_component_ops = {
> > > > +     .bind   = sprd_dsi_bind,
> > > > +     .unbind = sprd_dsi_unbind,
> > > > +};
> > > > +
> > > > +static const struct of_device_id dsi_match_table[] = {
> > > > +     { .compatible = "sprd,sharkl3-dsi-host" },
> > > > +     { /* sentinel */ },
> > > > +};
> > > > +
> > > > +static int sprd_dsi_probe(struct platform_device *pdev)
> > > > +{
> > > > +     return component_add(&pdev->dev, &dsi_component_ops);
> > >
> > > In order to prevent probe issues, you need to register you mipi_dsi_host
> > > here, see:
> > > https://lore.kernel.org/dri-devel/20210910101218.1632297-3-maxime@cerno.tech/
> >
> > We register mipi_dsi_hot on our panel driver, like this:
> >
> > 1092   ret = mipi_dsi_attach(slave);
> > 1093   if (ret) {
> > 1094   DRM_ERROR("failed to attach dsi panel to host\n");
> > 1095   drm_panel_remove(&panel->base);
> > 1096   return ret;
> > 1097   }
>
> It's not about when you attach, but when you call
> mipi_dsi_host_register. You're doing it in sprd_dsi_host_init that you
> call in bind(), which is against the best practices and will create
> probing issues in the future.
If we call mipi_dsi_host_register on probe phase, it looks like can't
call drmm_encoder_alloc to create dsi device on bind.
It may be necessary to go back to the devm_kzalloc method used before

static int sprd_dsi_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct sprd_dsi *dsi;

dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
if (!dsi)
    return -ENOMEM;

dsi->host.dev = dev;
dsi->host.ops = &sprd_dsi_host_ops;
ret = mipi_dsi_host_register(&dsi->host);
if (ret)
    dev_err(dev, "failed to register dsi host\n");

......
return 0;
}

>
> Maxime

Re: [PATCH v6 6/6] drm/sprd: add Unisoc's drm mipi dsi&dphy driver

[Kevin Tang]

Sam,
Thanks for your response.

Sam Ravnborg <sam@ravnborg.org> 于2021年9月27日周一 上午12:33写道：
>
> Hi Kevin,
>
> > > > +     reg->_0b.bits.out_sel = pll->out_sel;
> > > > +     reg->_0b.bits.kint_l = pll->kint & 0xf;
> > > > +     reg->_0e.bits.pll_pu_byp = 0;
> > > > +     reg->_0e.bits.pll_pu = 0;
> > > > +     reg->_0e.bits.stopstate_sel = 1;
> > > > +     reg->_0f.bits.det_delay = pll->det_delay;
> > > > +
> > > > +     val = (u8 *)&reg;
> > > > +
> > > > +     for (i = 0; i < sizeof(reg_addr); ++i) {
> > > > +             regmap_write(regmap, reg_addr[i], val[i]);
> > > > +             DRM_DEBUG("%02x: %02x\n", reg_addr[i], val[i]);
> > > > +     }
> > > > +}
> > >
> > > It would be great to also convert this part to a pattern without
> > > structures.
> > I will try it, but our pll registers, all not have official name from
> > aisc design owner.
> > If need to convert it, our pll regiters macro define, it can only be
> > named as reg_01, reg_02...
> IT is better to use the stupid names provided by you asic design owner,
> than just numbers. Add a comment explaining this is due to the asic
> design owner the names are stupid and not your fault.
The chip manual released to us by the asic designer is like this for
many years ago.
As for the specific reason, unable to find out now, i will try use
"stupid names" rather than numbers.
>
> > > > +
> > > > +     if (dsi->panel) {
> > > > +             drm_panel_prepare(dsi->panel);
> > > > +             drm_panel_enable(dsi->panel);
> > > > +     }
> > >
> > > Please use the new devm_drm_of_get_bridge helper here, and use the
> > > bridge API instead.
> > We use drm_panel_init and drm_panel_add API to add panel, so here is a
> > panel device, not a bridge.
>
> The new way to do this is to always wrap the panel in a bridge. We will
> start to slowly migrate away from direct use of the panel API, and let
> display drivers always wrap the panles in a bridge.
> So please do as Maxime suggests.
I only found a demo about the use of devm_drm_of_get_bridge in the vc4
dsi driver, i
will try to follow it.
>
>         Sam

Re: [PATCH v6 6/6] drm/sprd: add Unisoc's drm mipi dsi&dphy driver

[Kevin Tang]

Maxime Ripard <maxime@cerno.tech> 于2021年9月28日周二 下午5:28写道：
>
> On Sun, Sep 26, 2021 at 10:31:53PM +0800, Kevin Tang wrote:
> > Maxime Ripard <maxime@cerno.tech> 于2021年9月17日周五 下午11:40写道：
> > > > +static void sprd_dsi_encoder_mode_set(struct drm_encoder *encoder,
> > > > +                              struct drm_display_mode *mode,
> > > > +                              struct drm_display_mode *adj_mode)
> > > > +{
> > > > +     struct sprd_dsi *dsi = encoder_to_dsi(encoder);
> > > > +
> > > > +     drm_dbg(dsi->drm, "%s() set mode: %s\n", __func__, dsi->mode->name);
> > > > +}
> > >
> > > You don't need that function?
> > No need for now. need to delete it?
>
> Yes
>
> > > > +static int sprd_dsi_encoder_atomic_check(struct drm_encoder *encoder,
> > > > +                                 struct drm_crtc_state *crtc_state,
> > > > +                                 struct drm_connector_state *conn_state)
> > > > +{
> > > > +     return 0;
> > > > +}
> > >
> > > Ditto
> >
> > No need for now. need to delete it?
>
> Yep
>
> > > > +static int sprd_dsi_find_panel(struct sprd_dsi *dsi)
> > > > +{
> > > > +     struct device *dev = dsi->host.dev;
> > > > +     struct device_node *child, *lcds_node;
> > > > +     struct drm_panel *panel;
> > > > +
> > > > +     /* search /lcds child node first */
> > > > +     lcds_node = of_find_node_by_path("/lcds");
> > > > +     for_each_child_of_node(lcds_node, child) {
> > > > +             panel = of_drm_find_panel(child);
> > > > +             if (!IS_ERR(panel)) {
> > > > +                     dsi->panel = panel;
> > > > +                     return 0;
> > > > +             }
> > > > +     }
> > > > +
> > > > +     /*
> > > > +      * If /lcds child node search failed, we search
> > > > +      * the child of dsi host node.
> > > > +      */
> > > > +     for_each_child_of_node(dev->of_node, child) {
> > > > +             panel = of_drm_find_panel(child);
> > > > +             if (!IS_ERR(panel)) {
> > > > +                     dsi->panel = panel;
> > > > +                     return 0;
> > > > +             }
> > > > +     }
> > > > +
> > > > +     drm_err(dsi->drm, "of_drm_find_panel() failed\n");
> > > > +     return -ENODEV;
> > > > +}
> > >
> > > Just use devm_drm_of_get_bridge there
> >
> > We use drm_panel_init and drm_panel_add API to add panel, so here is a
> > panel device, not a bridge.
>
> Like Sam said, the panel API is on its way out and is being superseded
> by bridge_panels.
hi maxime,
If get a panel by devm_drm_of_get_bridge, how to use bridge api to access panel?
it seems that pre_enable/enable still needs to be implemented, so we
need to add drm_bridge_func,
then move the panel-related operations in drm_encoder_helper_funcs to
drm_bridge_funcs callback?
>
> > > > +static int sprd_dsi_host_init(struct sprd_dsi *dsi, struct device *dev)
> > > > +{
> > > > +     int ret;
> > > > +
> > > > +     dsi->host.dev = dev;
> > > > +     dsi->host.ops = &sprd_dsi_host_ops;
> > > > +
> > > > +     ret = mipi_dsi_host_register(&dsi->host);
> > > > +     if (ret)
> > > > +             drm_err(dsi->drm, "failed to register dsi host\n");
> > > > +
> > > > +     return ret;
> > > > +}
> > > >
> > > > [...]
> > > >
> > > > +static int sprd_dsi_connector_init(struct drm_device *drm, struct sprd_dsi *dsi)
> > > > +{
> > > > +     struct drm_encoder *encoder = &dsi->encoder;
> > > > +     struct drm_connector *connector = &dsi->connector;
> > > > +     int ret;
> > > > +
> > > > +     connector->polled = DRM_CONNECTOR_POLL_HPD;
> > > > +
> > > > +     ret = drm_connector_init(drm, connector,
> > > > +                              &sprd_dsi_atomic_connector_funcs,
> > > > +                              DRM_MODE_CONNECTOR_DSI);
> > > > +     if (ret) {
> > > > +             drm_err(drm, "drm_connector_init() failed\n");
> > > > +             return ret;
> > > > +     }
> > > > +
> > > > +     drm_connector_helper_add(connector,
> > > > +                              &sprd_dsi_connector_helper_funcs);
> > > > +
> > > > +     drm_connector_attach_encoder(connector, encoder);
> > > > +
> > > > +     return 0;
> > > > +}
> > > > +
> > > > +static int sprd_dsi_context_init(struct sprd_dsi *dsi,
> > > > +                     struct device *dev)
> > > > +{
> > > > +     struct platform_device *pdev = to_platform_device(dev);
> > > > +     struct dsi_context *ctx = &dsi->ctx;
> > > > +     struct resource *res;
> > > > +
> > > > +     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > > > +     ctx->base = devm_ioremap(dev, res->start, resource_size(res));
> > > > +     if (!ctx->base) {
> > > > +             drm_err(dsi->drm, "failed to map dsi host registers\n");
> > > > +             return -ENXIO;
> > > > +     }
> > > > +
> > > > +     ctx->pll = devm_kzalloc(dev, sizeof(*ctx->pll), GFP_KERNEL);
> > > > +     if (!ctx->pll)
> > > > +             return -ENOMEM;
> > > > +
> > > > +     ctx->regmap = devm_regmap_init(dev, &regmap_tst_io, dsi, &byte_config);
> > > > +     if (IS_ERR(ctx->regmap)) {
> > > > +             drm_err(dsi->drm, "dphy regmap init failed\n");
> > > > +             return PTR_ERR(ctx->regmap);
> > > > +     }
> > > > +
> > > > +     ctx->data_hs2lp = 120;
> > > > +     ctx->data_lp2hs = 500;
> > > > +     ctx->clk_hs2lp = 4;
> > > > +     ctx->clk_lp2hs = 15;
> > > > +     ctx->max_rd_time = 6000;
> > > > +     ctx->int0_mask = 0xffffffff;
> > > > +     ctx->int1_mask = 0xffffffff;
> > > > +     ctx->enabled = true;
> > > > +
> > > > +     return 0;
> > > > +}
> > > > +
> > > > +static int sprd_dsi_bind(struct device *dev, struct device *master, void *data)
> > > > +{
> > > > +     struct drm_device *drm = data;
> > > > +     struct sprd_dsi *dsi;
> > > > +     int ret;
> > > > +
> > > > +     dsi = sprd_dsi_encoder_init(drm, dev);
> > > > +     if (IS_ERR(dsi))
> > > > +             return PTR_ERR(dsi);
> > > > +
> > > > +     dsi->drm = drm;
> > > > +     dev_set_drvdata(dev, dsi);
> > > > +
> > > > +     ret = sprd_dsi_connector_init(drm, dsi);
> > > > +     if (ret)
> > > > +             return ret;
> > > > +
> > > > +     ret = sprd_dsi_context_init(dsi, dev);
> > > > +     if (ret)
> > > > +             return ret;
> > > > +
> > > > +     ret = sprd_dsi_host_init(dsi, dev);
> > > > +     if (ret)
> > > > +             return ret;
> > > > +
> > > > +     return 0;
> > > > +}
> > > > +
> > > > +static void sprd_dsi_unbind(struct device *dev,
> > > > +                     struct device *master, void *data)
> > > > +{
> > > > +     struct sprd_dsi *dsi = dev_get_drvdata(dev);
> > > > +
> > > > +     mipi_dsi_host_unregister(&dsi->host);
> > > > +}
> > > > +
> > > > +static const struct component_ops dsi_component_ops = {
> > > > +     .bind   = sprd_dsi_bind,
> > > > +     .unbind = sprd_dsi_unbind,
> > > > +};
> > > > +
> > > > +static const struct of_device_id dsi_match_table[] = {
> > > > +     { .compatible = "sprd,sharkl3-dsi-host" },
> > > > +     { /* sentinel */ },
> > > > +};
> > > > +
> > > > +static int sprd_dsi_probe(struct platform_device *pdev)
> > > > +{
> > > > +     return component_add(&pdev->dev, &dsi_component_ops);
> > >
> > > In order to prevent probe issues, you need to register you mipi_dsi_host
> > > here, see:
> > > https://lore.kernel.org/dri-devel/20210910101218.1632297-3-maxime@cerno.tech/
> >
> > We register mipi_dsi_hot on our panel driver, like this:
> >
> > 1092   ret = mipi_dsi_attach(slave);
> > 1093   if (ret) {
> > 1094   DRM_ERROR("failed to attach dsi panel to host\n");
> > 1095   drm_panel_remove(&panel->base);
> > 1096   return ret;
> > 1097   }
>
> It's not about when you attach, but when you call
> mipi_dsi_host_register. You're doing it in sprd_dsi_host_init that you
> call in bind(), which is against the best practices and will create
> probing issues in the future.
>
> Maxime

Re: [PATCH v6 6/6] drm/sprd: add Unisoc's drm mipi dsi&dphy driver

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 2615 bytes --]

Hi,

On Wed, Oct 20, 2021 at 06:09:32PM +0800, Kevin Tang wrote:
> Maxime Ripard <maxime@cerno.tech> 于2021年9月28日周二 下午5:28写道：
> > > > > +static int sprd_dsi_find_panel(struct sprd_dsi *dsi)
> > > > > +{
> > > > > +     struct device *dev = dsi->host.dev;
> > > > > +     struct device_node *child, *lcds_node;
> > > > > +     struct drm_panel *panel;
> > > > > +
> > > > > +     /* search /lcds child node first */
> > > > > +     lcds_node = of_find_node_by_path("/lcds");
> > > > > +     for_each_child_of_node(lcds_node, child) {
> > > > > +             panel = of_drm_find_panel(child);
> > > > > +             if (!IS_ERR(panel)) {
> > > > > +                     dsi->panel = panel;
> > > > > +                     return 0;
> > > > > +             }
> > > > > +     }
> > > > > +
> > > > > +     /*
> > > > > +      * If /lcds child node search failed, we search
> > > > > +      * the child of dsi host node.
> > > > > +      */
> > > > > +     for_each_child_of_node(dev->of_node, child) {
> > > > > +             panel = of_drm_find_panel(child);
> > > > > +             if (!IS_ERR(panel)) {
> > > > > +                     dsi->panel = panel;
> > > > > +                     return 0;
> > > > > +             }
> > > > > +     }
> > > > > +
> > > > > +     drm_err(dsi->drm, "of_drm_find_panel() failed\n");
> > > > > +     return -ENODEV;
> > > > > +}
> > > >
> > > > Just use devm_drm_of_get_bridge there
> > >
> > > We use drm_panel_init and drm_panel_add API to add panel, so here is a
> > > panel device, not a bridge.
> >
> > Like Sam said, the panel API is on its way out and is being superseded
> > by bridge_panels.
>
> If get a panel by devm_drm_of_get_bridge, how to use bridge api to
> access panel?

You don't.

You'd get a panel-bridge driver (drivers/gpu/drm/bridge/panel.c), that
behaves like a bridge and will call the panel functions itself.

And since it's a bridge, everything (enable, pre_enable, etc.) is called
by the core framework (in drm_atomic_helper_commit_modeset_enables for
enable and pre_enable).

> it seems that pre_enable/enable still needs to be implemented, so we
> need to add drm_bridge_func, then move the panel-related operations in
> drm_encoder_helper_funcs to drm_bridge_funcs callback?

You're confusing two things. Our comment wasn't that this DSI needed to
be converted to a bridge itself (which is what you're talking about),
but that it needs to use the bridge API instead of the panel API to deal
with whatever is connected at the other end of the DSI link.

Maxime

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]