From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79432C433F5 for ; Thu, 30 Sep 2021 05:32:52 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A8D9A6162E for ; Thu, 30 Sep 2021 05:32:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org A8D9A6162E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 200E780F5F; Thu, 30 Sep 2021 07:32:49 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="HP8mWT0j"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id E94A580F6A; Thu, 30 Sep 2021 07:32:47 +0200 (CEST) Received: from mail-ot1-x332.google.com (mail-ot1-x332.google.com [IPv6:2607:f8b0:4864:20::332]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id DEA2F80D2E for ; Thu, 30 Sep 2021 07:32:43 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=tkuw584924@gmail.com Received: by mail-ot1-x332.google.com with SMTP id c6-20020a9d2786000000b005471981d559so5858644otb.5 for ; Wed, 29 Sep 2021 22:32:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=gjRTlOQMVbnDcjmDj4YEL1CiseiFcxYpmpzeUAiREhM=; b=HP8mWT0jyakKnPyQ67zZaE2CNn/yu1GoQ47UxKNGMhFB3NAlr4DT3NeYPBfnoOG5ks q97M3PSsZGdWAtgzWaEb5rhoi+PeDof2b7Dg7Fb4MoLEABUqTcbymbyMEXTUDOXppPsw icaKvGD1soJexS1veoFITZuBJWWyMFd9gF4i6KkVWzSxE5JB/EiY+1BCRH9u0UBjWhnl dzbZnp1X0QSKd8wio8xvPhMWjaaW5zxLDqPuNNvclkWDDUe5HF7IjUMYEQwozqAwuQbJ Wz3F5sIZ8EYA3ZNy5iHR1ImCVFRnqGyuUYFX4N90BDdAITHjGO9TvstQSBVqyPDFyfQG rcJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=gjRTlOQMVbnDcjmDj4YEL1CiseiFcxYpmpzeUAiREhM=; b=O6PeK4ySx+yqDUdoa5ZETsMcKQsJWRLKje1gntjxCTnRH/38f0EJYTyA+sLKRtBAHE wWBxBYl6fy58zNoNZ//QToDj+nMwCiGqsmy9UidNQhGkBB55JV7Zc6z88Y0I1uM/Fo9X BUXQOpbZ+Gh8nvQsrk4pUvfRG3A+Y0GlhrLWvPpLhC7BTV1FSdMCFAB4h82xbw71btEB KwwRnZWHRyQqqsX9V8wCFWn9O8TzTbuS2RFsnnf32QWfRBbZDXdsYLXPwTybxOhhAGtt Q4uP8zFA1WBJ6ZYZ86UqUlg1S3lKZBeVYb+D1rMzVBbnjG763XVgTpPGlIr/MBMp7a+C hyQQ== X-Gm-Message-State: AOAM5330limhqezC7pUY989nD85lSKmSGoGGOaSE2T2pwBO0AB2CQugZ pd1cl076x0h9OxwmsPL98egYJOMcKwfZJw== X-Google-Smtp-Source: ABdhPJzJ+7DWzsg35iH97lLO/Mj7ZrPiNW1wT9PPf+MTKOlbytKOvL1tNdOQHSVz4nn0cmcBQmYQGA== X-Received: by 2002:a9d:68c2:: with SMTP id i2mr3504773oto.338.1632979962532; Wed, 29 Sep 2021 22:32:42 -0700 (PDT) Received: from ISCNPF1JZGWX.infineon.com (fp76ee264d.knge102.ap.nuro.jp. [118.238.38.77]) by smtp.gmail.com with ESMTPSA id i127sm415991oia.43.2021.09.29.22.32.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Sep 2021 22:32:41 -0700 (PDT) From: tkuw584924@gmail.com X-Google-Original-From: Takahiro.Kuwano@infineon.com To: u-boot@lists.denx.de Cc: jagan@amarulasolutions.com, vigneshr@ti.com, p.yadav@ti.com, tkuw584924@gmail.com, Bacem.Daassi@infineon.com, Takahiro Kuwano Subject: [PATCH v2] mtd: spi-nor-core: Add fixups for s25fs512s Date: Thu, 30 Sep 2021 14:32:28 +0900 Message-Id: <20210930053228.10760-1-Takahiro.Kuwano@infineon.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean From: Takahiro Kuwano The current S25FS512S support has following issues that need to be fixed. - Non-uniform sectors by factory default. The setting needs to be checked and assign erase hook as needed. - Page size is wrongly advertised in SFDP. - READ_1_1_2 (3Bh/3Ch), READ_1_1_4 (6Bh/6Ch), and PP_1_1_4 (32h/34h) are not supported. - Bank Address Register (BAR) is not supported. In addtion, volatile version of Quad Enable is used for safety. For future use, the fixups is assigned for S25FS-S family. The datasheet can be found in the following link. https://www.cypress.com/file/216376/download Tested on Xilinx Zynq-7000 FPGA board. Signed-off-by: Takahiro Kuwano --- Changes in v2: - Add #define S25FS_S_RDAR_DUMMY and remove hard-coding - Remove #ifdef CONFIG_SPI_FLASH_BAR drivers/mtd/spi/spi-nor-core.c | 108 +++++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index f1b4e5ea8e..349b2f3f23 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3099,6 +3099,109 @@ static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, } #ifdef CONFIG_SPI_FLASH_SPANSION + +/* Number of dummy cycle for Read Any Register (RDAR) op. */ +#define S25FS_S_RDAR_DUMMY 8 + +static int s25fs_s_quad_enable(struct spi_nor *nor) +{ + return spansion_quad_enable_volatile(nor, 0, S25FS_S_RDAR_DUMMY); +} + +static int s25fs_s_erase_non_uniform(struct spi_nor *nor, loff_t addr) +{ + /* Support 8 x 4KB sectors at bottom */ + return spansion_erase_non_uniform(nor, addr, SPINOR_OP_BE_4K_4B, 0, + SZ_32K); +} + +static int s25fs_s_setup(struct spi_nor *nor, const struct flash_info *info, + const struct spi_nor_flash_parameter *params) +{ + int ret; + u8 cfr3v; + + /* Bank Address Register is not supported */ + if (CONFIG_IS_ENABLED(SPI_FLASH_BAR)) + return -ENOTSUPP; + + /* + * Read CR3V to check if uniform sector is selected. If not, assign an + * erase hook that supports non-uniform erase. + */ + ret = spansion_read_any_reg(nor, SPINOR_REG_ADDR_CFR3V, + S25FS_S_RDAR_DUMMY, &cfr3v); + if (ret) + return ret; + if (!(cfr3v & CFR3V_UNHYSA)) + nor->erase = s25fs_s_erase_non_uniform; + + return spi_nor_default_setup(nor, info, params); +} + +static void s25fs_s_default_init(struct spi_nor *nor) +{ + nor->setup = s25fs_s_setup; +} + +static int s25fs_s_post_bfpt_fixup(struct spi_nor *nor, + const struct sfdp_parameter_header *header, + const struct sfdp_bfpt *bfpt, + struct spi_nor_flash_parameter *params) +{ + int ret; + u8 cfr3v; + + /* The erase size is set to 4K from BFPT, but it's wrong. Fix it. */ + nor->erase_opcode = SPINOR_OP_SE; + nor->mtd.erasesize = nor->info->sector_size; + + if (params->size > SZ_16M) { + ret = nor->write_reg(nor, SPINOR_OP_EN4B, NULL, 0); + if (ret) + return ret; + nor->addr_width = 4; + } else { + nor->addr_width = 3; + } + + /* + * The page_size is set to 512B from BFPT, but it actually depends on + * the configuration register. Look up the CFR3V and determine the + * page_size. + */ + ret = spansion_read_any_reg(nor, SPINOR_REG_ADDR_CFR3V, + S25FS_S_RDAR_DUMMY, &cfr3v); + if (ret) + return ret; + + if (cfr3v & CFR3V_PGMBUF) + params->page_size = 512; + else + params->page_size = 256; + + return 0; +} + +static void s25fs_s_post_sfdp_fixup(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) +{ + /* READ_1_1_2 is not supported */ + params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_2; + /* READ_1_1_4 is not supported */ + params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_4; + /* PP_1_1_4 is not supported */ + params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4; + /* Use volatile register to enable quad */ + params->quad_enable = s25fs_s_quad_enable; +} + +static struct spi_nor_fixups s25fs_s_fixups = { + .default_init = s25fs_s_default_init, + .post_bfpt = s25fs_s_post_bfpt_fixup, + .post_sfdp = s25fs_s_post_sfdp_fixup, +}; + static int s25hx_t_mdp_ready(struct spi_nor *nor) { u32 addr; @@ -3646,6 +3749,11 @@ void spi_nor_set_fixups(struct spi_nor *nor) break; } } + + /* For FS-S (family ID = 0x81) */ + if (JEDEC_MFR(nor->info) == SNOR_MFR_SPANSION && + nor->info->id[5] == 0x81) + nor->fixups = &s25fs_s_fixups; #endif #ifdef CONFIG_SPI_FLASH_S28HS512T -- 2.25.1