From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CE62C433EF for ; Fri, 1 Oct 2021 13:07:23 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E613661039 for ; Fri, 1 Oct 2021 13:07:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org E613661039 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=roeck-us.net Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:51852 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mWIG1-00039P-Tr for qemu-devel@archiver.kernel.org; Fri, 01 Oct 2021 09:07:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51664) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWIDG-0000IL-T0; Fri, 01 Oct 2021 09:04:32 -0400 Received: from mail-ot1-x32c.google.com ([2607:f8b0:4864:20::32c]:33698) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mWIDE-0002rv-HD; Fri, 01 Oct 2021 09:04:30 -0400 Received: by mail-ot1-x32c.google.com with SMTP id d12-20020a05683025cc00b0054d8486c6b8so11448890otu.0; Fri, 01 Oct 2021 06:04:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=1pEjhzod8KyDXjZmqcJnYQWCNQss8/wgABk2YIvtLRY=; b=QCeo3rzey7an0e625o5biBzt/Dx4XqWT6VX49TWSMyy+cZ/IRx5hsmi3KwrE3ryexg RXl4rD5sb+JD/5d6J1dEhS5hgAgtAia9I7TTwLdxMWmCHk6AJKBChHFMlBfGNLfspT4/ jUAXzLso+xV9kwKPpAtqoV1w2cyQ+Ke1QQZEIbCmDlAKttBjIyUO1JXtOTcFtDB9adhe rdxsN0x9a9Swm45XAHbsDOs/KMhJ9UPE2ZNwkZKpkkT/qYVR1BO2LLRMsAZ9bX6e+R7R b21oaaEMXsMOjfb6ogtgSlB0VIluLx/hwaXywRrmtgWp3suew/7wX7G3Tk8mW/GkVWVe kgXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:date:from:to:cc:subject:message-id :references:mime-version:content-disposition:in-reply-to; bh=1pEjhzod8KyDXjZmqcJnYQWCNQss8/wgABk2YIvtLRY=; b=I9rRY/Y9T8xWD/OY/fCbC7gN4erH8fGdUgIYXddb00P8Dx3QklNnc6XLzKLZJlK7Ko /QFxWidg21eC+mT2zxRaSAOh1xNHWPT8ppx/J5XOaHbK78OLqqewi9wgn4kTy9tE5CB3 +8SEJSqDAh4EXt/U8C50TqJHc4PbbDGss/TspRrsjR9xNsQyt4PG4Vn+zTYYcN8nagTN flBmZAK92lixBmq4Ac4T8AnPkTCTKIakYM6xzU1JL6zPGe0IDsW/uxwZNb4HVf4zVCK3 jr/KH1YzU2IDRITCBHlaLPe+mbcn/3Nl1QvXs5A/gg81r1T73eIbVodfJaPIMkGpLxlT /ztQ== X-Gm-Message-State: AOAM533AvFmz7CKmtGch6Yj+Ge0tKdwGwU78rpiW7GjcccmLCIiFHbsA 6YX8a/v3eyc83O8ZkL83xDY= X-Google-Smtp-Source: ABdhPJxEva5SIHYceATrGNRkkQBkGXBRAxilzFovP24tekb/3hQ/fDYdnlILUxDiZTnnS+RO1PRfUg== X-Received: by 2002:a9d:67cf:: with SMTP id c15mr10286049otn.232.1633093465962; Fri, 01 Oct 2021 06:04:25 -0700 (PDT) Received: from server.roeck-us.net ([2600:1700:e321:62f0:329c:23ff:fee3:9d7c]) by smtp.gmail.com with ESMTPSA id bf15sm1247344oib.4.2021.10.01.06.04.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Oct 2021 06:04:25 -0700 (PDT) Date: Fri, 1 Oct 2021 06:04:23 -0700 From: Guenter Roeck To: Bin Meng Subject: Re: [PATCH] hw/ssi: imx_spi: Improve chip select handling Message-ID: <20211001130423.GA549865@roeck-us.net> References: <8b86d434-a2e6-8122-0a88-dc9a15fbfe87@roeck-us.net> <20210916142140.GA252836@roeck-us.net> <2cd83a88-952c-6f86-74b2-8c0da3ce4394@roeck-us.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::32c; envelope-from=groeck7@gmail.com; helo=mail-ot1-x32c.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , "Cheng, Xuzhou" , Alistair Francis , QEMU Developers , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , qemu-arm , Jean-Christophe Dubois Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Sun, Sep 26, 2021 at 10:49:53AM +0800, Bin Meng wrote: > On Sat, Sep 18, 2021 at 12:19 PM Guenter Roeck wrote: > > > > On 9/17/21 8:09 PM, Cheng, Xuzhou wrote: > > >>> I got some free time in the past days to investigate this issue. Guenter is right, the Linux imx-spi driver does not work on QEMU. > > >>> > > >>> The reason is that the state of m25p80 machine loops in STATE_READING_DATA state after receiving RDSR command, the new command is ignored. Before sending a new command, the CS line should be pulled to high, this make the state of m25p80 back to IDLE. > > >>> > > >>> I have same point with Guenter, it's that set CS to 1 when burst is zero. But i don't think it is necessary to set CS to 0 in imx_spi_flush_txfifo(). I will send a new patch to fix this issue. > > >>> > > >> > > >> Thanks a lot for looking into this. If you have a better solution than mine, by all means, please go for it. As I mentioned in my patch, I didn't really like it, but I was unable to find a better solution. > > > I am doing some experiment to verify that the new patch is reasonable, so the new patch will be delayed few days. > > > > > > > No problem. Note that I'll be traveling for the next 2-3 weeks, and I won't be able > > to test any patches during that time. > > > > I have some updates to share, as I have been working with Xuzhou > internally on this issue for the past days: > > Current mods using BURST_LEN to determine the timing to pull up the CS > line in the SPI controller codes is a workaround. Hardware does not do > this. To understand what real hardware behavior is, Xuzhou used an > oscilloscope to verify our guess. > > It turns out the root cause is elsewhere, and a proper fix will be > sent out soon. > Thanks a lot for tracking this down! Guenter