From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52507C433F5 for ; Fri, 1 Oct 2021 13:41:20 +0000 (UTC) Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by mail.kernel.org (Postfix) with ESMTP id 045DF619E5 for ; Fri, 1 Oct 2021 13:41:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 045DF619E5 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=marvell.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=dpdk.org Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6631E411BD; Fri, 1 Oct 2021 15:40:53 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 73FFC411BD for ; Fri, 1 Oct 2021 15:40:51 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 191A8GOi029756 for ; Fri, 1 Oct 2021 06:40:50 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=51RnhpBfBjqbOPKvicNQ+i9Cp0tgbz3hX/CdNvcaBTY=; b=Rv2QVrJWjSrZFZ5PVn5YiVjLxln5++KRHS+O3B2kS1cgs5BQo2ybID7GDphuYf/6q3LU /J6bdmHpHTkBFkdMaDn7IiBYTQpwrdT0fPT1uaISRqCoT23Jgto3WieBBs2FvIJ9FCVF wkugiyhtzKYuLKDnodZYivDnvy60yx0BDzZ56vyuYTpGXn2gOEfYJIxZEx1GB7sZQqmP pQAYBwpDuhMQN5BABKe3xcbGkC60EM3rLDpKTqsYiW7yzsOetiCjY/Fqspx7nJUREAt1 6nHZebs0wD5ChB/68lJOc3WlArwfATyG75Sno3geVpuNfHUA8CFB4tb4WvpCELcuPMkQ 2A== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3bdrxmhx9t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 01 Oct 2021 06:40:50 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 1 Oct 2021 06:40:48 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Fri, 1 Oct 2021 06:40:48 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id D47343F7043; Fri, 1 Oct 2021 06:40:46 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: Date: Fri, 1 Oct 2021 19:10:02 +0530 Message-ID: <20211001134022.22700-9-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20211001134022.22700-1-ndabilpuram@marvell.com> References: <20210902021505.17607-1-ndabilpuram@marvell.com> <20211001134022.22700-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-GUID: gjFdZVU1VNcq1JT3pAS1U6E5s93KA3bd X-Proofpoint-ORIG-GUID: gjFdZVU1VNcq1JT3pAS1U6E5s93KA3bd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-10-01_02,2021-10-01_02,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 08/28] common/cnxk: disable CQ drop when inline inbound is enabled X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Disable CQ drop when inline inbound is enabled. CQ drop is not supported for second pass IPsec decrypted packets. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_nix_queue.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index 41e8f2c..41a1422 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -492,15 +492,20 @@ roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq) cq->drop_thresh = min_rx_drop; } else { cq->drop_thresh = NIX_CQ_THRESH_LEVEL; - cq_ctx->drop = cq->drop_thresh; - cq_ctx->drop_ena = 1; + /* Drop processing or red drop cannot be enabled due to + * due to packets coming for second pass from CPT. + */ + if (!roc_nix_inl_inb_is_enabled(roc_nix)) { + cq_ctx->drop = cq->drop_thresh; + cq_ctx->drop_ena = 1; + } } /* TX pause frames enable flow ctrl on RX side */ if (nix->tx_pause) { /* Single BPID is allocated for all rx channels for now */ cq_ctx->bpid = nix->bpid[0]; - cq_ctx->bp = cq_ctx->drop; + cq_ctx->bp = cq->drop_thresh; cq_ctx->bp_ena = 1; } -- 2.8.4