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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Richard Henderson" <richard.henderson@linaro.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Aurelien Jarno" <aurelien@aurel32.net>,
	"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>
Subject: [PATCH 7/8] target/mips: Use tcg_constant_i32() in gen_msa_i5()
Date: Sun,  3 Oct 2021 19:57:42 +0200	[thread overview]
Message-ID: <20211003175743.3738710-8-f4bug@amsat.org> (raw)
In-Reply-To: <20211003175743.3738710-1-f4bug@amsat.org>

Avoid using a TCG temporary by moving Data Format to the constant pool.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa_translate.c | 40 ++++++++++++++++++++-------------
 1 file changed, 24 insertions(+), 16 deletions(-)

diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 3ef912da6b8..3ede2f643c0 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -473,14 +473,32 @@ static void gen_msa_i8(DisasContext *ctx)
 static void gen_msa_i5(DisasContext *ctx)
 {
 #define MASK_MSA_I5(op)    (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
-    int8_t s5 = (int8_t) sextract32(ctx->opcode, 16, 5);
-    uint8_t u5 = extract32(ctx->opcode, 16, 5);
-
     TCGv_i32 tdf = tcg_const_i32(extract32(ctx->opcode, 21, 2));
     TCGv_i32 twd = tcg_const_i32(extract32(ctx->opcode, 11, 5));
     TCGv_i32 tws = tcg_const_i32(extract32(ctx->opcode, 6, 5));
-    TCGv_i32 timm = tcg_temp_new_i32();
-    tcg_gen_movi_i32(timm, u5);
+    TCGv_i32 timm;
+
+    switch (MASK_MSA_I5(ctx->opcode)) {
+    case OPC_ADDVI_df:
+    case OPC_MAXI_U_df:
+    case OPC_MINI_U_df:
+    case OPC_CLTI_U_df:
+    case OPC_CLEI_U_df:
+        timm = tcg_constant_i32(extract32(ctx->opcode, 16, 5));
+        break;
+    case OPC_MAXI_S_df:
+    case OPC_MINI_S_df:
+    case OPC_CEQI_df:
+    case OPC_CLTI_S_df:
+    case OPC_CLEI_S_df:
+        timm = tcg_constant_i32(sextract32(ctx->opcode, 16, 5));
+        break;
+    case OPC_LDI_df:
+        timm = tcg_constant_i32(sextract32(ctx->opcode, 11, 10));
+        break;
+    default:
+        break;
+    }
 
     switch (MASK_MSA_I5(ctx->opcode)) {
     case OPC_ADDVI_df:
@@ -490,43 +508,34 @@ static void gen_msa_i5(DisasContext *ctx)
         gen_helper_msa_subvi_df(cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_MAXI_S_df:
-        tcg_gen_movi_i32(timm, s5);
         gen_helper_msa_maxi_s_df(cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_MAXI_U_df:
         gen_helper_msa_maxi_u_df(cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_MINI_S_df:
-        tcg_gen_movi_i32(timm, s5);
         gen_helper_msa_mini_s_df(cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_MINI_U_df:
         gen_helper_msa_mini_u_df(cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_CEQI_df:
-        tcg_gen_movi_i32(timm, s5);
         gen_helper_msa_ceqi_df(cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_CLTI_S_df:
-        tcg_gen_movi_i32(timm, s5);
         gen_helper_msa_clti_s_df(cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_CLTI_U_df:
         gen_helper_msa_clti_u_df(cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_CLEI_S_df:
-        tcg_gen_movi_i32(timm, s5);
         gen_helper_msa_clei_s_df(cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_CLEI_U_df:
         gen_helper_msa_clei_u_df(cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_LDI_df:
-        {
-            int32_t s10 = sextract32(ctx->opcode, 11, 10);
-            tcg_gen_movi_i32(timm, s10);
-            gen_helper_msa_ldi_df(cpu_env, tdf, twd, timm);
-        }
+        gen_helper_msa_ldi_df(cpu_env, tdf, twd, timm);
         break;
     default:
         MIPS_INVAL("MSA instruction");
@@ -537,7 +546,6 @@ static void gen_msa_i5(DisasContext *ctx)
     tcg_temp_free_i32(tdf);
     tcg_temp_free_i32(twd);
     tcg_temp_free_i32(tws);
-    tcg_temp_free_i32(timm);
 }
 
 static void gen_msa_bit(DisasContext *ctx)
-- 
2.31.1



  parent reply	other threads:[~2021-10-03 18:09 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-03 17:57 [PATCH 0/8] target/mips: Use tcg_constant_* Philippe Mathieu-Daudé
2021-10-03 17:57 ` [PATCH 1/8] target/mips: Remove unused register from MSA 2R/2RF instruction format Philippe Mathieu-Daudé
2021-10-03 17:57 ` [PATCH 2/8] target/mips: Use tcg_constant_i32() in gen_msa_elm_df() Philippe Mathieu-Daudé
2021-10-03 19:25   ` Richard Henderson
2021-10-03 17:57 ` [PATCH 3/8] target/mips: Use tcg_constant_i32() in gen_msa_2rf() Philippe Mathieu-Daudé
2021-10-03 19:26   ` Richard Henderson
2021-10-03 17:57 ` [PATCH 4/8] target/mips: Use tcg_constant_i32() in gen_msa_2r() Philippe Mathieu-Daudé
2021-10-03 19:28   ` Richard Henderson
2021-10-03 17:57 ` [PATCH 5/8] target/mips: Use tcg_constant_i32() in gen_msa_3rf() Philippe Mathieu-Daudé
2021-10-03 19:30   ` Richard Henderson
2021-10-03 17:57 ` [PATCH 6/8] target/mips: Use explicit extract32() calls in gen_msa_i5() Philippe Mathieu-Daudé
2021-10-03 19:35   ` Richard Henderson
2021-10-03 17:57 ` Philippe Mathieu-Daudé [this message]
2021-10-03 19:37   ` [PATCH 7/8] target/mips: Use tcg_constant_i32() " Richard Henderson
2021-10-03 17:57 ` [PATCH 8/8] target/mips: Use tcg_constant_tl() in gen_compute_compact_branch() Philippe Mathieu-Daudé
2021-10-03 19:37   ` Richard Henderson
2021-10-11 22:22 ` [PATCH 0/8] target/mips: Use tcg_constant_* Philippe Mathieu-Daudé

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