From: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
To: <lukma@denx.de>, <trini@konsulko.com>, <sjg@chromium.org>,
<u-boot@lists.denx.de>
Cc: <joel@jms.id.au>, <ryan_chen@aspeedtech.com>,
<johnny_huang@aspeedtech.com>
Subject: [PATCH next v5 08/12] ARM: dts: ast2600: Add ACRY to device tree
Date: Mon, 4 Oct 2021 09:54:15 +0800 [thread overview]
Message-ID: <20211004015419.8190-9-chiawei_wang@aspeedtech.com> (raw)
In-Reply-To: <20211004015419.8190-1-chiawei_wang@aspeedtech.com>
Add ACRY DTS node and enable it for AST2600 EVB.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
---
arch/arm/dts/ast2600-evb.dts | 5 +++++
arch/arm/dts/ast2600.dtsi | 9 +++++++++
2 files changed, 14 insertions(+)
diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts
index adb80a30ef..05362d19bd 100644
--- a/arch/arm/dts/ast2600-evb.dts
+++ b/arch/arm/dts/ast2600-evb.dts
@@ -182,3 +182,8 @@
u-boot,dm-pre-reloc;
status = "okay";
};
+
+&acry {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi
index b8fe966c7d..31905fd208 100644
--- a/arch/arm/dts/ast2600.dtsi
+++ b/arch/arm/dts/ast2600.dtsi
@@ -195,6 +195,15 @@
status = "disabled";
};
+ acry: acry@1e6fa000 {
+ compatible = "aspeed,ast2600-acry";
+ reg = <0x1e6fa000 0x1000>,
+ <0x1e710000 0x10000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scu ASPEED_CLK_GATE_RSACLK>;
+ status = "disabled";
+ };
+
edac: sdram@1e6e0000 {
compatible = "aspeed,ast2600-sdram-edac";
reg = <0x1e6e0000 0x174>;
--
2.17.1
next prev parent reply other threads:[~2021-10-04 1:55 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-04 1:54 [PATCH next v5 00/12] aspeed: Support secure boot chain with FIT image verification Chia-Wei Wang
2021-10-04 1:54 ` [PATCH next v5 01/12] image: fit: Fix parameter name for hash algorithm Chia-Wei Wang
2021-10-14 15:09 ` Simon Glass
2021-10-15 1:34 ` ChiaWei Wang
2021-10-04 1:54 ` [PATCH next v5 02/12] aspeed: ast2600: Enlarge SRAM size Chia-Wei Wang
2021-10-04 1:54 ` [PATCH next v5 03/12] clk: ast2600: Add YCLK control for HACE Chia-Wei Wang
2021-10-04 1:54 ` [PATCH next v5 04/12] crypto: aspeed: Add AST2600 HACE support Chia-Wei Wang
2021-10-04 1:54 ` [PATCH next v5 05/12] ARM: dts: ast2600: Add HACE to device tree Chia-Wei Wang
2021-10-04 1:54 ` [PATCH next v5 06/12] clk: ast2600: Add RSACLK control for ACRY Chia-Wei Wang
2021-10-04 1:54 ` [PATCH next v5 07/12] crypto: aspeed: Add AST2600 ACRY support Chia-Wei Wang
2021-10-04 1:54 ` Chia-Wei Wang [this message]
2021-10-04 1:54 ` [PATCH next v5 09/12] ast2600: spl: Locate load buffer in DRAM space Chia-Wei Wang
2021-10-04 1:54 ` [PATCH next v5 10/12] configs: ast2600-evb: Enable SPL FIT support Chia-Wei Wang
2021-10-04 1:54 ` [PATCH next v5 11/12] configs: aspeed: Make EXTRA_ENV_SETTINGS board specific Chia-Wei Wang
2021-10-04 1:54 ` [PATCH next v5 12/12] configs: ast2600: Boot kernel FIT in DRAM Chia-Wei Wang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211004015419.8190-9-chiawei_wang@aspeedtech.com \
--to=chiawei_wang@aspeedtech.com \
--cc=joel@jms.id.au \
--cc=johnny_huang@aspeedtech.com \
--cc=lukma@denx.de \
--cc=ryan_chen@aspeedtech.com \
--cc=sjg@chromium.org \
--cc=trini@konsulko.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.