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Mon, 4 Oct 2021 07:43:11 -0700 Received: from wayne-System-Product-Name.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2308.8 via Frontend Transport; Mon, 4 Oct 2021 09:42:59 -0500 From: Wayne Lin To: CC: , , , , , , , , , Jimmy Kizito , Jun Lei , Wayne Lin Subject: [PATCH 09/23] drm/amd/display: Implement DPIA training loop Date: Mon, 4 Oct 2021 22:40:36 +0800 Message-ID: <20211004144050.3425351-10-Wayne.Lin@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211004144050.3425351-1-Wayne.Lin@amd.com> References: <20211004144050.3425351-1-Wayne.Lin@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ee0a92b7-ddef-452d-040b-08d987454ad0 X-MS-TrafficTypeDiagnostic: SN6PR12MB4672: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:152; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Oct 2021 14:43:12.6845 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ee0a92b7-ddef-452d-040b-08d987454ad0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT050.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB4672 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Jimmy Kizito [Why] Training of DPIA link differs enough from that of conventional DP link to warrant a separate implementation. [How] - Implement top-level of DPIA training loop. - Make functions shared between DP and DPIA link training "public". Reviewed-by: Jun Lei Acked-by: Wayne Lin Acked-by: Nicholas Kazlauskas Signed-off-by: Jimmy Kizito --- .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 17 --- .../drm/amd/display/dc/core/dc_link_dpia.c | 109 ++++++++++++++++++ .../gpu/drm/amd/display/dc/inc/dc_link_dpia.h | 10 ++ drivers/gpu/drm/amd/display/dc/os_types.h | 1 + 4 files changed, 120 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index d7dddc0998db..7f6fd0a3bf18 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -2320,23 +2320,6 @@ enum link_training_result dc_link_dp_perform_link_training( return status; } -/* - * Train DP tunneling link for USB4 DPIA display endpoint. - * - * DPIA equivalent of dc_link_dp_perfrorm_link_training. - */ -enum link_training_result dc_link_dpia_perform_link_training(struct dc_link *link, - const struct dc_link_settings *link_setting, - bool skip_video_pattern) -{ - enum link_training_result status; - - /** @todo Always fail until USB4 DPIA training implemented. */ - status = LINK_TRAINING_CR_FAIL_LANE0; - - return status; -} - bool perform_link_training_with_retries( const struct dc_link_settings *link_setting, bool skip_video_pattern, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c index 183601e300fe..4e9bbc9180d0 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c @@ -23,12 +23,121 @@ * */ +#include "dc.h" #include "dc_link_dpia.h" #include "inc/core_status.h" #include "dc_link.h" +#include "dc_link_dp.h" enum dc_status dpcd_get_tunneling_device_data(struct dc_link *link) { /** @todo Read corresponding DPCD region and update link caps. */ return DC_OK; } + +/* Configure link as prescribed in link_setting; set LTTPR mode; and + * Initialize link training settings. + */ +static enum link_training_result dpia_configure_link(struct dc_link *link, + const struct dc_link_settings *link_setting, + struct link_training_settings *lt_settings) +{ + enum link_training_result result; + + /** @todo Fail until implemented. */ + result = LINK_TRAINING_ABORT; + + return result; +} + +/* Execute clock recovery phase of link training for specified hop in display + * path. + */ +static enum link_training_result dpia_training_cr_phase(struct dc_link *link, + struct link_training_settings *lt_settings, + uint32_t hop) +{ + enum link_training_result result; + + /** @todo Fail until implemented. */ + result = LINK_TRAINING_ABORT; + + return result; +} + +/* Execute equalization phase of link training for specified hop in display + * path. + */ +static enum link_training_result dpia_training_eq_phase(struct dc_link *link, + struct link_training_settings *lt_settings, + uint32_t hop) +{ + enum link_training_result result; + + /** @todo Fail until implemented. */ + result = LINK_TRAINING_ABORT; + + return result; +} + +/* End training of specified hop in display path. */ +static enum link_training_result dpia_training_end(struct dc_link *link, + uint32_t hop) +{ + enum link_training_result result; + + /** @todo Fail until implemented. */ + result = LINK_TRAINING_ABORT; + + return result; +} + +enum link_training_result dc_link_dpia_perform_link_training(struct dc_link *link, + const struct dc_link_settings *link_setting, + bool skip_video_pattern) +{ + enum link_training_result result; + struct link_training_settings lt_settings; + uint8_t repeater_cnt = 0; /* Number of hops/repeaters in display path. */ + uint8_t repeater_id; /* Current hop. */ + + /* Configure link as prescribed in link_setting and set LTTPR mode. */ + result = dpia_configure_link(link, link_setting, <_settings); + if (result != LINK_TRAINING_SUCCESS) + return result; + + if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) + repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt); + + /* Train each hop in turn starting with the one closest to DPTX. + * In transparent or non-LTTPR mode, train only the final hop (DPRX). + */ + for (repeater_id = repeater_cnt; repeater_id >= 0; repeater_id--) { + /* Clock recovery. */ + result = dpia_training_cr_phase(link, <_settings, repeater_id); + if (result != LINK_TRAINING_SUCCESS) + break; + + /* Equalization. */ + result = dpia_training_eq_phase(link, <_settings, repeater_id); + if (result != LINK_TRAINING_SUCCESS) + break; + + /* Stop training hop. */ + result = dpia_training_end(link, repeater_id); + if (result != LINK_TRAINING_SUCCESS) + break; + } + + /* Double-check link status if training successful; gracefully stop + * training of current hop if training failed for any reason other than + * sink unplug. + */ + if (result == LINK_TRAINING_SUCCESS) { + msleep(5); + result = dp_check_link_loss_status(link, <_settings); + } else if (result != LINK_TRAINING_ABORT) { + dpia_training_end(link, repeater_id); + } + return result; +} diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dpia.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dpia.h index 8ed0c9f6414b..1392eb689d1e 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dpia.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dpia.h @@ -29,10 +29,20 @@ /* This module implements functionality for training DPIA links. */ struct dc_link; +struct dc_link_settings; /* Read tunneling device capability from DPCD and update link capability * accordingly. */ enum dc_status dpcd_get_tunneling_device_data(struct dc_link *link); +/* Train DP tunneling link for USB4 DPIA display endpoint. + * DPIA equivalent of dc_link_dp_perfrorm_link_training. + * Aborts link training upon detection of sink unplug. + */ +enum link_training_result +dc_link_dpia_perform_link_training(struct dc_link *link, + const struct dc_link_settings *link_setting, + bool skip_video_pattern); + #endif /* __DC_LINK_DPIA_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/os_types.h b/drivers/gpu/drm/amd/display/dc/os_types.h index f50cae252de4..415b56223bcf 100644 --- a/drivers/gpu/drm/amd/display/dc/os_types.h +++ b/drivers/gpu/drm/amd/display/dc/os_types.h @@ -31,6 +31,7 @@ #include #include #include +#include #include -- 2.25.1