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From: Wayne Lin <Wayne.Lin@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: <alexander.deucher@amd.com>, <Harry.Wentland@amd.com>,
	<nicholas.kazlauskas@amd.com>, <Rodrigo.Siqueira@amd.com>,
	<wayne.lin@amd.com>, <stylon.wang@amd.com>, <jude.shih@amd.com>,
	<jimmy.kizito@amd.com>, <meenakshikumar.somasundaram@amd.com>,
	Jimmy Kizito <Jimmy.Kizito@amd.com>, Jun Lei <Jun.Lei@amd.com>,
	Wayne Lin <Wayne.Lin@amd.com>
Subject: [PATCH 10/23] drm/amd/display: Implement DPIA link configuration
Date: Mon, 4 Oct 2021 22:40:37 +0800	[thread overview]
Message-ID: <20211004144050.3425351-11-Wayne.Lin@amd.com> (raw)
In-Reply-To: <20211004144050.3425351-1-Wayne.Lin@amd.com>

From: Jimmy Kizito <Jimmy.Kizito@amd.com>

[Why]
Training settings need to be applied to DPIA link at start of each
training loop. Note: FEC readiness should be configured before link
training while FEC enablement should be configured once training is
complete.

[How]
- Implement DPIA link configuration function.
- Account for dynamically assigned link encoders during link
configuration.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
---
 .../drm/amd/display/dc/core/dc_link_dpia.c    | 49 ++++++++++++++++---
 .../display/dc/dcn31/dcn31_dio_link_encoder.c |  2 +
 2 files changed, 45 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
index 4e9bbc9180d0..5ffaf6ca372b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
@@ -29,6 +29,9 @@
 #include "dc_link.h"
 #include "dc_link_dp.h"
 
+#define DC_LOGGER \
+	link->ctx->logger
+
 enum dc_status dpcd_get_tunneling_device_data(struct dc_link *link)
 {
 	/** @todo Read corresponding DPCD region and update link caps. */
@@ -37,17 +40,51 @@ enum dc_status dpcd_get_tunneling_device_data(struct dc_link *link)
 
 /* Configure link as prescribed in link_setting; set LTTPR mode; and
  * Initialize link training settings.
+ * Abort link training if sink unplug detected.
+ *
+ * @param link DPIA link being trained.
+ * @param[in] link_setting Lane count, link rate and downspread control.
+ * @param[out] lt_settings Link settings and drive settings (voltage swing and pre-emphasis).
  */
 static enum link_training_result dpia_configure_link(struct dc_link *link,
 		const struct dc_link_settings *link_setting,
 		struct link_training_settings *lt_settings)
 {
-	enum link_training_result result;
-
-	/** @todo Fail until implemented. */
-	result = LINK_TRAINING_ABORT;
-
-	return result;
+	enum dc_status status;
+	bool fec_enable;
+
+	DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) configuring\n - LTTPR mode(%d)\n",
+				__func__,
+				link->link_id.enum_id - ENUM_ID_1,
+				link->lttpr_mode);
+
+	dp_decide_training_settings(link,
+		link_setting,
+		lt_settings);
+
+	status = dpcd_configure_channel_coding(link, lt_settings);
+	if (status != DC_OK && !link->hpd_status)
+		return LINK_TRAINING_ABORT;
+
+	/* Configure lttpr mode */
+	status = dpcd_configure_lttpr_mode(link, lt_settings);
+	if (status != DC_OK && !link->hpd_status)
+		return LINK_TRAINING_ABORT;
+
+	/* Set link rate, lane count and spread. */
+	status = dpcd_set_link_settings(link, lt_settings);
+	if (status != DC_OK && !link->hpd_status)
+		return LINK_TRAINING_ABORT;
+
+	if (link->preferred_training_settings.fec_enable)
+		fec_enable = *link->preferred_training_settings.fec_enable;
+	else
+		fec_enable = true;
+	status = dp_set_fec_ready(link, fec_enable);
+	if (status != DC_OK && !link->hpd_status)
+		return LINK_TRAINING_ABORT;
+
+	return LINK_TRAINING_SUCCESS;
 }
 
 /* Execute clock recovery phase of link training for specified hop in display
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
index f86d4446f347..a5266d5999d7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
@@ -428,6 +428,7 @@ void dcn31_link_encoder_enable_dp_output(
 
 		if (link) {
 			dpia_control.dpia_id = link->ddc_hw_inst;
+			dpia_control.fec_rdy = link->fec_state == dc_link_fec_ready ? 1 : 0;
 		} else {
 			DC_LOG_ERROR("%s: Failed to execute DPIA enable DMUB command.\n", __func__);
 			BREAK_TO_DEBUGGER();
@@ -469,6 +470,7 @@ void dcn31_link_encoder_enable_dp_mst_output(
 
 		if (link) {
 			dpia_control.dpia_id = link->ddc_hw_inst;
+			dpia_control.fec_rdy = link->fec_state == dc_link_fec_ready ? 1 : 0;
 		} else {
 			DC_LOG_ERROR("%s: Failed to execute DPIA enable DMUB command.\n", __func__);
 			BREAK_TO_DEBUGGER();
-- 
2.25.1


  parent reply	other threads:[~2021-10-04 14:43 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-04 14:40 [PATCH 00/23] USB4 DP tunneling Wayne Lin
2021-10-04 14:40 ` [PATCH 01/23] drm/amd/display: Update link encoder object creation Wayne Lin
2021-10-04 14:40 ` [PATCH 02/23] drm/amd/display: USB4 DPIA enumeration and AUX Tunneling Wayne Lin
2021-10-04 14:40 ` [PATCH 03/23] drm/amd/display: Support for DMUB HPD and HPD RX interrupt handling Wayne Lin
2021-10-04 14:40 ` [PATCH 04/23] drm/amd/display: Support USB4 dynamic link encoder selection Wayne Lin
2021-10-04 14:40 ` [PATCH 05/23] drm/amd/display: Support USB4 for display endpoint control path Wayne Lin
2021-10-04 14:40 ` [PATCH 06/23] drm/amd/display: Support DP tunneling when DPRX detection Wayne Lin
2021-10-04 14:40 ` [PATCH 07/23] drm/amd/display: Update training parameters for DPIA links Wayne Lin
2021-10-04 14:40 ` [PATCH 08/23] drm/amd/display: Support USB4 when DP link training Wayne Lin
2021-10-04 14:40 ` [PATCH 09/23] drm/amd/display: Implement DPIA training loop Wayne Lin
2021-10-04 14:40 ` Wayne Lin [this message]
2021-10-04 14:40 ` [PATCH 11/23] drm/amd/display: Implement DPIA clock recovery phase Wayne Lin
2021-10-04 14:40 ` [PATCH 12/23] drm/amd/display: Implement DPIA equalisation phase Wayne Lin
2021-10-04 14:40 ` [PATCH 13/23] drm/amd/display: Implement end of training for hop in DPIA display path Wayne Lin
2021-10-04 14:40 ` [PATCH 14/23] drm/amd/display: Support for SET_CONFIG processing with DMUB Wayne Lin
2021-10-04 14:40 ` [PATCH 15/23] drm/amd/display: Read USB4 DP tunneling data from DPCD Wayne Lin
2021-10-04 14:40 ` [PATCH 16/23] drm/amd/display: Add dpia debug options Wayne Lin
2021-10-04 14:40 ` [PATCH 17/23] drm/amd/display: Support for SET_CONFIG processing with DMUB Wayne Lin
2021-10-04 14:40 ` [PATCH 18/23] drm/amd/display: Fix DIG_HPD_SELECT for USB4 display endpoints Wayne Lin
2021-10-04 14:40 ` [PATCH 19/23] drm/amd/display: Add debug flags for USB4 DP link training Wayne Lin
2021-10-04 14:40 ` [PATCH 20/23] drm/amd/display: Fix for access for ddc pin and aux engine Wayne Lin
2021-10-04 14:40 ` [PATCH 21/23] drm/amd/display: Deadlock/HPD Status/Crash Bug Fix Wayne Lin
2021-10-04 14:40 ` [PATCH 22/23] drm/amd/display: Fix USB4 Aux via DMUB terminate unexpectedly Wayne Lin
2021-10-04 14:40 ` [PATCH 23/23] drm/amd/display: USB4 bring up set correct address Wayne Lin
2021-10-04 14:48 ` [PATCH 00/23] USB4 DP tunneling Harry Wentland
2021-10-05  6:30   ` Lin, Wayne

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