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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Oct 2021 07:59:48.0243 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e70f92df-d6e8-4450-b627-08d987d61a1f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT025.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3316 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Jimmy Kizito [Why] DIB_BE_CNTL.DIG_HPD_SELECT selects the HPD block being used by the display endpoint assigned to DIG. In the case of USB4 display endpoints, no physical HPD block is assigned. [How] Setting DIB_BE_CNTL.DIG_HPD_SELECT to 5 indicates that no HPD is assigned to a display endpoint. Firmware decrements the HPD_SELECT value by 1 before writing it to the register. Reviewed-by: Meenakshikumar Somasundaram Acked-by: Wayne Lin Acked-by: Nicholas Kazlauskas Signed-off-by: Jimmy Kizito --- .../amd/display/dc/dcn31/dcn31_dio_link_encoder.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c index a5266d5999d7..8f8eee475144 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c @@ -388,7 +388,7 @@ static bool link_dpia_control(struct dc_context *dc_ctx, dc_dmub_srv_cmd_execute(dmub); dc_dmub_srv_wait_idle(dmub); - return false; + return true; } static void link_encoder_disable(struct dcn10_link_encoder *enc10) @@ -424,7 +424,10 @@ void dcn31_link_encoder_enable_dp_output( dpia_control.lanenum = (uint8_t)link_settings->lane_count; dpia_control.symclk_10khz = link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ / 10; - dpia_control.hpdsel = 5; /* Unused by DPIA */ + /* DIG_BE_CNTL.DIG_HPD_SELECT set to 5 (hpdsel - 1) to indicate HPD pin + * unused by DPIA. + */ + dpia_control.hpdsel = 6; if (link) { dpia_control.dpia_id = link->ddc_hw_inst; @@ -466,7 +469,10 @@ void dcn31_link_encoder_enable_dp_mst_output( dpia_control.lanenum = (uint8_t)link_settings->lane_count; dpia_control.symclk_10khz = link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ / 10; - dpia_control.hpdsel = 5; /* Unused by DPIA */ + /* DIG_BE_CNTL.DIG_HPD_SELECT set to 5 (hpdsel - 1) to indicate HPD pin + * unused by DPIA. + */ + dpia_control.hpdsel = 6; if (link) { dpia_control.dpia_id = link->ddc_hw_inst; -- 2.25.1