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Tue, 5 Oct 2021 12:28:04 +0000 From: Raja Zidane To: Date: Tue, 5 Oct 2021 12:27:31 +0000 Message-ID: <20211005122733.12444-4-rzidane@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211005122733.12444-1-rzidane@nvidia.com> References: <20210930054438.5960-1-rzidane@nvidia.com> <20211005122733.12444-1-rzidane@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 04712319-f8dd-4cc4-0c46-08d987fb95dd X-MS-TrafficTypeDiagnostic: BY5PR12MB4274: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:792; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: M6fxPk5RaMDiD45xj0RJ2Q1EPQM5QE47qmMXTdJGn+ZZ8Ny4FWuZkP9yJdqxtU7oxe8EnyZEBxfNk0hlp9jN3c50F44qIAbVpkRBqNu1j5P5VgT+lRwT9/A9cCYD5/3P6y3TowACCzzeFKDrl4WAPP2E6nlUF/HA9Rl0Kf6rQMa4jvSwz52zszgej+915+KiEGQcrEI9ZxB1riqMVfERBwc9RYXw29O1Lt2428zwLK4iY/Wlihq1hlBlfiSdW+zAtBQ52D/WF9NcpNol+Nk105ROdU2+UOJgGOpSmkL3JHZb0X06m66JDSRyoqst6C9kBmGyy7Yen191/eRHQtVoTzVTXmLKV9OxpR3HDXjE6jIC4hiic2V641/r9EOGScJiFbw49G3+qO+601/BnYbKtjF7PkMs3NIEqZewuXjKpxcrPhEDDsHUa4btjHtmqCu0ZjGd9UCTR0h+StyLNYRIjPa7ggEEAxicBLZitE7lN362Dqs4m7B9lv+CYpc4eNJAzH6Kju0HRCs7XrMWUnqQMpSCLofJkNos9g0Kj7J9Watg8/kPJ9tzZSv9wly9RUM4RCG8iWxCQW6fQgaIVlaRyUUI84RpiTGbK4mU67aRt/TaUQ5A5Mm1Zl4oV6fHkFIgSn+n9/5ZfLGvhWGIivf3INHA9brCbSrUxW+vhxUfZREfzzsJlu3FUH2L8GaOnL+0TPZu7GCZRQ+QcZ0AsdnDTQ== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(70206006)(83380400001)(316002)(356005)(426003)(6286002)(8676002)(6666004)(8936002)(7696005)(2906002)(36860700001)(336012)(7636003)(5660300002)(26005)(86362001)(70586007)(16526019)(55016002)(47076005)(1076003)(6916009)(82310400003)(36756003)(186003)(2616005)(508600001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Oct 2021 12:28:06.9280 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 04712319-f8dd-4cc4-0c46-08d987fb95dd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT027.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4274 Subject: [dpdk-dev] [PATCH V6 3/5] common/mlx5: add MMO configuration for the DevX QP X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" A new configuration MMO was added to QP Context. If set, MMO WQEs are supported on this QP. For DMA MMO, supported only when dma_mmo_qp==1. For REGEXP MMO, supported only when regexp_mmo_qp==1. For COMPRESS MMO, supported only when compress_mmo_qp==1. For DECOMPRESS MMO, supported only when decompress_mmo_qp==1. Add support to DevX interface to set MMO bit. Signed-off-by: Raja Zidane Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_devx_cmds.c | 7 +++++++ drivers/common/mlx5/mlx5_devx_cmds.h | 1 + drivers/common/mlx5/mlx5_prm.h | 28 +++++++++++++++++++++++++++- 3 files changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 00c78b1288..eefb869b7d 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -2032,6 +2032,13 @@ mlx5_devx_cmd_create_qp(void *ctx, MLX5_SET(qpc, qpc, ts_format, attr->ts_format); MLX5_SET(qpc, qpc, user_index, attr->user_index); if (attr->uar_index) { + if (attr->mmo) { + void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in, + in, qpc_extension_and_pas_list); + void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list, + qpc_ext_and_pas_list, qpc_data_extension); + MLX5_SET(qpc_extension, qpc_ext, mmo, 1); + } MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); MLX5_SET(qpc, qpc, uar_page, attr->uar_index); if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index b21df0fd9b..e149f8b4f5 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -403,6 +403,7 @@ struct mlx5_devx_qp_attr { uint32_t wq_umem_id; uint64_t wq_umem_offset; uint32_t user_index:24; + uint32_t mmo:1; }; struct mlx5_devx_virtio_q_couners_attr { diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index ec5f871c61..54e62aa153 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -3243,6 +3243,28 @@ struct mlx5_ifc_create_qp_out_bits { u8 reserved_at_60[0x20]; }; +struct mlx5_ifc_qpc_extension_bits { + u8 reserved_at_0[0x2]; + u8 mmo[0x1]; + u8 reserved_at_3[0x5fd]; +}; + +#ifdef PEDANTIC +#pragma GCC diagnostic ignored "-Wpedantic" +#endif +struct mlx5_ifc_qpc_pas_list_bits { + u8 pas[0][0x40]; +}; + +#ifdef PEDANTIC +#pragma GCC diagnostic ignored "-Wpedantic" +#endif +struct mlx5_ifc_qpc_extension_and_pas_list_bits { + struct mlx5_ifc_qpc_extension_bits qpc_data_extension; + u8 pas[0][0x40]; +}; + + #ifdef PEDANTIC #pragma GCC diagnostic ignored "-Wpedantic" #endif @@ -3260,7 +3282,11 @@ struct mlx5_ifc_create_qp_in_bits { u8 wq_umem_id[0x20]; u8 wq_umem_valid[0x1]; u8 reserved_at_861[0x1f]; - u8 pas[0][0x40]; + union { + struct mlx5_ifc_qpc_pas_list_bits qpc_pas_list; + struct mlx5_ifc_qpc_extension_and_pas_list_bits + qpc_extension_and_pas_list; + }; }; #ifdef PEDANTIC #pragma GCC diagnostic error "-Wpedantic" -- 2.17.1