From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33141C433F5 for ; Wed, 6 Oct 2021 00:18:14 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 131526117A for ; Wed, 6 Oct 2021 00:18:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 131526117A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 37A9882DA1; Wed, 6 Oct 2021 02:18:10 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 92D7A82DA1; Wed, 6 Oct 2021 02:18:07 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id CCA9A807DA for ; Wed, 6 Oct 2021 02:18:00 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CDFD11FB; Tue, 5 Oct 2021 17:17:59 -0700 (PDT) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 075C73F66F; Tue, 5 Oct 2021 17:17:58 -0700 (PDT) Date: Wed, 6 Oct 2021 01:17:25 +0100 From: Andre Przywara To: Samuel Holland Cc: u-boot@lists.denx.de, Jagan Teki , Lukasz Majewski Subject: Re: [PATCH 1/2] clk: sunxi: Add support for I2C gates/resets Message-ID: <20211006011725.2512cd13@slackpad.fritz.box> In-Reply-To: <20210912144726.28546-1-samuel@sholland.org> References: <20210912144726.28546-1-samuel@sholland.org> Organization: Arm Ltd. X-Mailer: Claws Mail 3.17.1 (GTK+ 2.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On Sun, 12 Sep 2021 09:47:24 -0500 Samuel Holland wrote: > Currently, the I2C clocks are configured in the sunxi board code. Add > the I2C clocks to the DM clock driver so they can be enabled from the > DM I2C driver using the normal uclass methods. > > Signed-off-by: Samuel Holland Compared against the kernel's drivers/clk/sunxi-ng/ccu-*.c. Reviewed-by: Andre Przywara Thanks, Andre > --- > > drivers/clk/sunxi/clk_a10.c | 5 +++++ > drivers/clk/sunxi/clk_a10s.c | 3 +++ > drivers/clk/sunxi/clk_a23.c | 6 ++++++ > drivers/clk/sunxi/clk_a31.c | 8 ++++++++ > drivers/clk/sunxi/clk_a64.c | 6 ++++++ > drivers/clk/sunxi/clk_a80.c | 10 ++++++++++ > drivers/clk/sunxi/clk_a83t.c | 6 ++++++ > drivers/clk/sunxi/clk_h3.c | 6 ++++++ > drivers/clk/sunxi/clk_h6.c | 10 ++++++++++ > drivers/clk/sunxi/clk_h616.c | 12 ++++++++++++ > drivers/clk/sunxi/clk_r40.c | 10 ++++++++++ > drivers/clk/sunxi/clk_v3s.c | 4 ++++ > 12 files changed, 86 insertions(+) > > diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c > index 1b5de86e204..20006925f1e 100644 > --- a/drivers/clk/sunxi/clk_a10.c > +++ b/drivers/clk/sunxi/clk_a10.c > @@ -31,6 +31,11 @@ static struct ccu_clk_gate a10_gates[] = { > > [CLK_AHB_GMAC] = GATE(0x064, BIT(17)), > > + [CLK_APB1_I2C0] = GATE(0x06c, BIT(0)), > + [CLK_APB1_I2C1] = GATE(0x06c, BIT(1)), > + [CLK_APB1_I2C2] = GATE(0x06c, BIT(2)), > + [CLK_APB1_I2C3] = GATE(0x06c, BIT(3)), > + [CLK_APB1_I2C4] = GATE(0x06c, BIT(15)), > [CLK_APB1_UART0] = GATE(0x06c, BIT(16)), > [CLK_APB1_UART1] = GATE(0x06c, BIT(17)), > [CLK_APB1_UART2] = GATE(0x06c, BIT(18)), > diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c > index 184f61ab234..7e7b2bf7009 100644 > --- a/drivers/clk/sunxi/clk_a10s.c > +++ b/drivers/clk/sunxi/clk_a10s.c > @@ -25,6 +25,9 @@ static struct ccu_clk_gate a10s_gates[] = { > [CLK_AHB_SPI1] = GATE(0x060, BIT(21)), > [CLK_AHB_SPI2] = GATE(0x060, BIT(22)), > > + [CLK_APB1_I2C0] = GATE(0x06c, BIT(0)), > + [CLK_APB1_I2C1] = GATE(0x06c, BIT(1)), > + [CLK_APB1_I2C2] = GATE(0x06c, BIT(2)), > [CLK_APB1_UART0] = GATE(0x06c, BIT(16)), > [CLK_APB1_UART1] = GATE(0x06c, BIT(17)), > [CLK_APB1_UART2] = GATE(0x06c, BIT(18)), > diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c > index 5750514a74f..87011525dcf 100644 > --- a/drivers/clk/sunxi/clk_a23.c > +++ b/drivers/clk/sunxi/clk_a23.c > @@ -23,6 +23,9 @@ static struct ccu_clk_gate a23_gates[] = { > [CLK_BUS_EHCI] = GATE(0x060, BIT(26)), > [CLK_BUS_OHCI] = GATE(0x060, BIT(29)), > > + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), > + [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), > + [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)), > [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), > [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), > [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), > @@ -53,6 +56,9 @@ static struct ccu_reset a23_resets[] = { > [RST_BUS_EHCI] = RESET(0x2c0, BIT(26)), > [RST_BUS_OHCI] = RESET(0x2c0, BIT(29)), > > + [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), > + [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), > + [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)), > [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), > [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), > [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), > diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c > index 9226112f4af..2554762df9d 100644 > --- a/drivers/clk/sunxi/clk_a31.c > +++ b/drivers/clk/sunxi/clk_a31.c > @@ -30,6 +30,10 @@ static struct ccu_clk_gate a31_gates[] = { > [CLK_AHB1_OHCI1] = GATE(0x060, BIT(30)), > [CLK_AHB1_OHCI2] = GATE(0x060, BIT(31)), > > + [CLK_APB2_I2C0] = GATE(0x06c, BIT(0)), > + [CLK_APB2_I2C1] = GATE(0x06c, BIT(1)), > + [CLK_APB2_I2C2] = GATE(0x06c, BIT(2)), > + [CLK_APB2_I2C3] = GATE(0x06c, BIT(3)), > [CLK_APB2_UART0] = GATE(0x06c, BIT(16)), > [CLK_APB2_UART1] = GATE(0x06c, BIT(17)), > [CLK_APB2_UART2] = GATE(0x06c, BIT(18)), > @@ -71,6 +75,10 @@ static struct ccu_reset a31_resets[] = { > [RST_AHB1_OHCI1] = RESET(0x2c0, BIT(30)), > [RST_AHB1_OHCI2] = RESET(0x2c0, BIT(31)), > > + [RST_APB2_I2C0] = RESET(0x2d8, BIT(0)), > + [RST_APB2_I2C1] = RESET(0x2d8, BIT(1)), > + [RST_APB2_I2C2] = RESET(0x2d8, BIT(2)), > + [RST_APB2_I2C3] = RESET(0x2d8, BIT(3)), > [RST_APB2_UART0] = RESET(0x2d8, BIT(16)), > [RST_APB2_UART1] = RESET(0x2d8, BIT(17)), > [RST_APB2_UART2] = RESET(0x2d8, BIT(18)), > diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c > index 0553ffa4399..013801c7e41 100644 > --- a/drivers/clk/sunxi/clk_a64.c > +++ b/drivers/clk/sunxi/clk_a64.c > @@ -26,6 +26,9 @@ static const struct ccu_clk_gate a64_gates[] = { > [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)), > [CLK_BUS_OHCI1] = GATE(0x060, BIT(29)), > > + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), > + [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), > + [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)), > [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), > [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), > [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), > @@ -60,6 +63,9 @@ static const struct ccu_reset a64_resets[] = { > [RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)), > [RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)), > > + [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), > + [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), > + [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)), > [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), > [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), > [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), > diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c > index 68973d528ed..79083e846f9 100644 > --- a/drivers/clk/sunxi/clk_a80.c > +++ b/drivers/clk/sunxi/clk_a80.c > @@ -25,6 +25,11 @@ static const struct ccu_clk_gate a80_gates[] = { > [CLK_BUS_SPI2] = GATE(0x580, BIT(22)), > [CLK_BUS_SPI3] = GATE(0x580, BIT(23)), > > + [CLK_BUS_I2C0] = GATE(0x594, BIT(0)), > + [CLK_BUS_I2C1] = GATE(0x594, BIT(1)), > + [CLK_BUS_I2C2] = GATE(0x594, BIT(2)), > + [CLK_BUS_I2C3] = GATE(0x594, BIT(3)), > + [CLK_BUS_I2C4] = GATE(0x594, BIT(4)), > [CLK_BUS_UART0] = GATE(0x594, BIT(16)), > [CLK_BUS_UART1] = GATE(0x594, BIT(17)), > [CLK_BUS_UART2] = GATE(0x594, BIT(18)), > @@ -40,6 +45,11 @@ static const struct ccu_reset a80_resets[] = { > [RST_BUS_SPI2] = RESET(0x5a0, BIT(22)), > [RST_BUS_SPI3] = RESET(0x5a0, BIT(23)), > > + [RST_BUS_I2C0] = RESET(0x5b4, BIT(0)), > + [RST_BUS_I2C1] = RESET(0x5b4, BIT(1)), > + [RST_BUS_I2C2] = RESET(0x5b4, BIT(2)), > + [RST_BUS_I2C3] = RESET(0x5b4, BIT(3)), > + [RST_BUS_I2C4] = RESET(0x5b4, BIT(4)), > [RST_BUS_UART0] = RESET(0x5b4, BIT(16)), > [RST_BUS_UART1] = RESET(0x5b4, BIT(17)), > [RST_BUS_UART2] = RESET(0x5b4, BIT(18)), > diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c > index 880c7d75997..b21bd1db2c2 100644 > --- a/drivers/clk/sunxi/clk_a83t.c > +++ b/drivers/clk/sunxi/clk_a83t.c > @@ -25,6 +25,9 @@ static struct ccu_clk_gate a83t_gates[] = { > [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)), > [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)), > > + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), > + [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), > + [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)), > [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), > [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), > [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), > @@ -57,6 +60,9 @@ static struct ccu_reset a83t_resets[] = { > [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)), > [RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)), > > + [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), > + [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), > + [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)), > [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), > [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), > [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), > diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c > index f81633b92d5..5741b5e6be6 100644 > --- a/drivers/clk/sunxi/clk_h3.c > +++ b/drivers/clk/sunxi/clk_h3.c > @@ -30,6 +30,9 @@ static struct ccu_clk_gate h3_gates[] = { > [CLK_BUS_OHCI2] = GATE(0x060, BIT(30)), > [CLK_BUS_OHCI3] = GATE(0x060, BIT(31)), > > + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), > + [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), > + [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)), > [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), > [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), > [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), > @@ -74,6 +77,9 @@ static struct ccu_reset h3_resets[] = { > > [RST_BUS_EPHY] = RESET(0x2c8, BIT(2)), > > + [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), > + [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), > + [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)), > [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), > [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), > [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), > diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c > index df93d96b3b0..0ee089295e0 100644 > --- a/drivers/clk/sunxi/clk_h6.c > +++ b/drivers/clk/sunxi/clk_h6.c > @@ -22,6 +22,11 @@ static struct ccu_clk_gate h6_gates[] = { > [CLK_BUS_UART2] = GATE(0x90c, BIT(2)), > [CLK_BUS_UART3] = GATE(0x90c, BIT(3)), > > + [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)), > + [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)), > + [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)), > + [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)), > + > [CLK_SPI0] = GATE(0x940, BIT(31)), > [CLK_SPI1] = GATE(0x944, BIT(31)), > > @@ -57,6 +62,11 @@ static struct ccu_reset h6_resets[] = { > [RST_BUS_UART2] = RESET(0x90c, BIT(18)), > [RST_BUS_UART3] = RESET(0x90c, BIT(19)), > > + [RST_BUS_I2C0] = RESET(0x91c, BIT(16)), > + [RST_BUS_I2C1] = RESET(0x91c, BIT(17)), > + [RST_BUS_I2C2] = RESET(0x91c, BIT(18)), > + [RST_BUS_I2C3] = RESET(0x91c, BIT(19)), > + > [RST_BUS_SPI0] = RESET(0x96c, BIT(16)), > [RST_BUS_SPI1] = RESET(0x96c, BIT(17)), > > diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c > index 553d7c6e550..bebefc9caa1 100644 > --- a/drivers/clk/sunxi/clk_h616.c > +++ b/drivers/clk/sunxi/clk_h616.c > @@ -24,6 +24,12 @@ static struct ccu_clk_gate h616_gates[] = { > [CLK_BUS_UART4] = GATE(0x90c, BIT(4)), > [CLK_BUS_UART5] = GATE(0x90c, BIT(5)), > > + [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)), > + [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)), > + [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)), > + [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)), > + [CLK_BUS_I2C4] = GATE(0x91c, BIT(4)), > + > [CLK_SPI0] = GATE(0x940, BIT(31)), > [CLK_SPI1] = GATE(0x944, BIT(31)), > > @@ -68,6 +74,12 @@ static struct ccu_reset h616_resets[] = { > [RST_BUS_UART4] = RESET(0x90c, BIT(20)), > [RST_BUS_UART5] = RESET(0x90c, BIT(21)), > > + [RST_BUS_I2C0] = RESET(0x91c, BIT(16)), > + [RST_BUS_I2C1] = RESET(0x91c, BIT(17)), > + [RST_BUS_I2C2] = RESET(0x91c, BIT(18)), > + [RST_BUS_I2C3] = RESET(0x91c, BIT(19)), > + [RST_BUS_I2C4] = RESET(0x91c, BIT(20)), > + > [RST_BUS_SPI0] = RESET(0x96c, BIT(16)), > [RST_BUS_SPI1] = RESET(0x96c, BIT(17)), > > diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c > index ee1e86d22eb..b509bc2de62 100644 > --- a/drivers/clk/sunxi/clk_r40.c > +++ b/drivers/clk/sunxi/clk_r40.c > @@ -32,6 +32,11 @@ static struct ccu_clk_gate r40_gates[] = { > > [CLK_BUS_GMAC] = GATE(0x064, BIT(17)), > > + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), > + [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), > + [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)), > + [CLK_BUS_I2C3] = GATE(0x06c, BIT(3)), > + [CLK_BUS_I2C4] = GATE(0x06c, BIT(15)), > [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), > [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), > [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), > @@ -77,6 +82,11 @@ static struct ccu_reset r40_resets[] = { > > [RST_BUS_GMAC] = RESET(0x2c4, BIT(17)), > > + [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), > + [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), > + [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)), > + [RST_BUS_I2C3] = RESET(0x2d8, BIT(3)), > + [RST_BUS_I2C4] = RESET(0x2d8, BIT(15)), > [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), > [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), > [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), > diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c > index 29622199fdc..ba58dce5d8d 100644 > --- a/drivers/clk/sunxi/clk_v3s.c > +++ b/drivers/clk/sunxi/clk_v3s.c > @@ -20,6 +20,8 @@ static struct ccu_clk_gate v3s_gates[] = { > [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), > [CLK_BUS_OTG] = GATE(0x060, BIT(24)), > > + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), > + [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), > [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), > [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), > [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), > @@ -38,6 +40,8 @@ static struct ccu_reset v3s_resets[] = { > [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)), > [RST_BUS_OTG] = RESET(0x2c0, BIT(24)), > > + [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), > + [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), > [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), > [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), > [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),