* [Intel-gfx] [PATCH v2 0/5] drm/i915: Improve DP link training further
@ 2021-10-04 17:05 Ville Syrjala
2021-10-04 17:05 ` [Intel-gfx] [PATCH v2 1/5] drm/i915: Tweak the DP "max vswing reached?" condition Ville Syrjala
` (11 more replies)
0 siblings, 12 replies; 21+ messages in thread
From: Ville Syrjala @ 2021-10-04 17:05 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
A little bit more generic DP link training improvements before
we finally get to the actual per-lane drive settings PHY
programming stuff.
v2: CI is confused about sha1s for some reason
Ville Syrjälä (5):
drm/i915: Tweak the DP "max vswing reached?" condition
drm/i915: Show LTTPR in the TPS debug print
drm/i915: Print the DP vswing adjustment request
drm/i915: Pimp link training debug prints
drm/i915: Call intel_dp_dump_link_status() for CR failures
drivers/gpu/drm/i915/display/g4x_dp.c | 2 +-
.../drm/i915/display/intel_dp_link_training.c | 217 +++++++++++++-----
.../drm/i915/display/intel_dp_link_training.h | 1 +
3 files changed, 157 insertions(+), 63 deletions(-)
--
2.32.0
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH v2 1/5] drm/i915: Tweak the DP "max vswing reached?" condition
2021-10-04 17:05 [Intel-gfx] [PATCH v2 0/5] drm/i915: Improve DP link training further Ville Syrjala
@ 2021-10-04 17:05 ` Ville Syrjala
2021-10-06 15:44 ` Imre Deak
2021-10-04 17:05 ` [Intel-gfx] [PATCH v2 2/5] drm/i915: Show LTTPR in the TPS debug print Ville Syrjala
` (10 subsequent siblings)
11 siblings, 1 reply; 21+ messages in thread
From: Ville Syrjala @ 2021-10-04 17:05 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Currently we consider the max vswing reached when we transmit a
the max voltage level, but we don't consider pre-emphasis at all.
This kinda matches older DP specs that only had some vague text
about transmitting the maximum voltage swing. Latest versions
now say something vague about consider the sum of the vswing
and pre-emphasis fields in the ADJUST_REQUEST_LANE registers.
Very vague, and super confusing especially the fact that it
talks about transmitted voltgage swing in the same sentence
as it say to look at the requested values.
Also glanced at the link CTS spec, and that one seems to have
tests that assume contradicting behaviour. Some say to consider
just the vswing level we transmit, others say to check for
sum of transmitted vswing+preemph being 3.
So let's try to take some kind of sane middle ground here.
I think what could make sense is only consider max vswing
reached if MAX_SWING_REACHED==1 _and_ vswing+preemph==3.
That will allow things to go all the way up to vswing 3 +
pre-emph 0 or vswing 2 + pre-emph 1, depending on what
the maximum supported vswing is. Only considering the sum
of vswing+pre-emph doesn't make much sense to me since
we could terminate too early if the sink requests eg.
vswing 0 + pre-emph 3. And if we'd stick to the current
code we could terminate too early of the sink asks for
vswing 2 + pre-emph 0 when vswing level 3 is not supported.
Side note: I don't really understand why any of this stuff is
"specified" at all. There is already a limit of 5 attempts at
the same vswing+pre-emph level, and a total limit of 10
attempts. So might as well stick to the same max 5 attempts
across the board IMO.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/intel_dp_link_training.c | 22 ++++++++++++++++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index c052ce14894d..a45569b8c959 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -492,11 +492,27 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
{
int lane;
- for (lane = 0; lane < crtc_state->lane_count; lane++)
- if ((intel_dp->train_set[lane] &
- DP_TRAIN_MAX_SWING_REACHED) == 0)
+ /*
+ * FIXME: The DP spec is very confusing here, also the Link CTS
+ * spec seems to have self contradicting tests around this area.
+ *
+ * In lieu of better ideas let's just stop when we've reached the
+ * max supported vswing with its max pre-emphasis, which is either
+ * 2+1 or 3+0 depending on whether vswing level 3 is supported or not.
+ */
+ for (lane = 0; lane < crtc_state->lane_count; lane++) {
+ u8 v = (intel_dp->train_set[lane] & DP_TRAIN_VOLTAGE_SWING_MASK) >>
+ DP_TRAIN_VOLTAGE_SWING_SHIFT;
+ u8 p = (intel_dp->train_set[lane] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
+ DP_TRAIN_PRE_EMPHASIS_SHIFT;
+
+ if ((intel_dp->train_set[lane] & DP_TRAIN_MAX_SWING_REACHED) == 0)
return false;
+ if (v + p != 3)
+ return false;
+ }
+
return true;
}
--
2.32.0
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH v2 2/5] drm/i915: Show LTTPR in the TPS debug print
2021-10-04 17:05 [Intel-gfx] [PATCH v2 0/5] drm/i915: Improve DP link training further Ville Syrjala
2021-10-04 17:05 ` [Intel-gfx] [PATCH v2 1/5] drm/i915: Tweak the DP "max vswing reached?" condition Ville Syrjala
@ 2021-10-04 17:05 ` Ville Syrjala
2021-10-06 15:47 ` Imre Deak
2021-10-04 17:05 ` [Intel-gfx] [PATCH v2 3/5] drm/i915: Print the DP vswing adjustment request Ville Syrjala
` (9 subsequent siblings)
11 siblings, 1 reply; 21+ messages in thread
From: Ville Syrjala @ 2021-10-04 17:05 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Indicate which LTTPR we're currently attempting to train when
we print which training pattern we're using.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/g4x_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 11 +++++++----
drivers/gpu/drm/i915/display/intel_dp_link_training.h | 1 +
3 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index 60ae2ba52006..85a09c3e09e8 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -637,7 +637,7 @@ static void intel_dp_enable_port(struct intel_dp *intel_dp,
/* enable with pattern 1 (as per spec) */
intel_dp_program_link_training_pattern(intel_dp, crtc_state,
- DP_TRAINING_PATTERN_1);
+ DP_PHY_DPRX, DP_TRAINING_PATTERN_1);
/*
* Magic for VLV/CHV. We _must_ first set up the register
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index a45569b8c959..6bab097cafd2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -376,7 +376,7 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
int len;
intel_dp_program_link_training_pattern(intel_dp, crtc_state,
- dp_train_pat);
+ dp_phy, dp_train_pat);
buf[0] = dp_train_pat;
/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
@@ -404,17 +404,20 @@ static char dp_training_pattern_name(u8 train_pat)
void
intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
+ enum drm_dp_phy dp_phy,
u8 dp_train_pat)
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat);
+ char phy_name[10];
if (train_pat != DP_TRAINING_PATTERN_DISABLE)
drm_dbg_kms(&dev_priv->drm,
- "[ENCODER:%d:%s] Using DP training pattern TPS%c\n",
+ "[ENCODER:%d:%s] Using DP training pattern TPS%c, at %s\n",
encoder->base.base.id, encoder->base.name,
- dp_training_pattern_name(train_pat));
+ dp_training_pattern_name(train_pat),
+ intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
}
@@ -855,7 +858,7 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp,
intel_dp->link_trained = true;
intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
- intel_dp_program_link_training_pattern(intel_dp, crtc_state,
+ intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX,
DP_TRAINING_PATTERN_DISABLE);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
index 9d24d594368c..6a3a7b37349a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
@@ -19,6 +19,7 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
const u8 link_status[DP_LINK_STATUS_SIZE]);
void intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
+ enum drm_dp_phy dp_phy,
u8 dp_train_pat);
void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
--
2.32.0
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH v2 3/5] drm/i915: Print the DP vswing adjustment request
2021-10-04 17:05 [Intel-gfx] [PATCH v2 0/5] drm/i915: Improve DP link training further Ville Syrjala
2021-10-04 17:05 ` [Intel-gfx] [PATCH v2 1/5] drm/i915: Tweak the DP "max vswing reached?" condition Ville Syrjala
2021-10-04 17:05 ` [Intel-gfx] [PATCH v2 2/5] drm/i915: Show LTTPR in the TPS debug print Ville Syrjala
@ 2021-10-04 17:05 ` Ville Syrjala
2021-10-06 15:50 ` Imre Deak
2021-10-04 17:05 ` [Intel-gfx] [PATCH v2 4/5] drm/i915: Pimp link training debug prints Ville Syrjala
` (8 subsequent siblings)
11 siblings, 1 reply; 21+ messages in thread
From: Ville Syrjala @ 2021-10-04 17:05 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Print out each DP vswing adjustment request we got from the RX.
Could help in diagnosing what's going on during link training.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/intel_dp_link_training.c | 27 +++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 6bab097cafd2..5657be1461ec 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -343,14 +343,41 @@ static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp,
return v | p;
}
+#define TRAIN_REQ_FMT "%d/%d/%d/%d"
+#define _TRAIN_REQ_VSWING_ARGS(link_status, lane) \
+ (drm_dp_get_adjust_request_voltage((link_status), (lane)) >> DP_TRAIN_VOLTAGE_SWING_SHIFT)
+#define TRAIN_REQ_VSWING_ARGS(link_status) \
+ _TRAIN_REQ_VSWING_ARGS(link_status, 0), \
+ _TRAIN_REQ_VSWING_ARGS(link_status, 1), \
+ _TRAIN_REQ_VSWING_ARGS(link_status, 2), \
+ _TRAIN_REQ_VSWING_ARGS(link_status, 3)
+#define _TRAIN_REQ_PREEMPH_ARGS(link_status, lane) \
+ (drm_dp_get_adjust_request_pre_emphasis((link_status), (lane)) >> DP_TRAIN_PRE_EMPHASIS_SHIFT)
+#define TRAIN_REQ_PREEMPH_ARGS(link_status) \
+ _TRAIN_REQ_PREEMPH_ARGS(link_status, 0), \
+ _TRAIN_REQ_PREEMPH_ARGS(link_status, 1), \
+ _TRAIN_REQ_PREEMPH_ARGS(link_status, 2), \
+ _TRAIN_REQ_PREEMPH_ARGS(link_status, 3)
+
void
intel_dp_get_adjust_train(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
enum drm_dp_phy dp_phy,
const u8 link_status[DP_LINK_STATUS_SIZE])
{
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+ char phy_name[10];
int lane;
+ drm_dbg_kms(encoder->base.dev, "[ENCODER:%d:%s] lanes: %d, "
+ "vswing request: " TRAIN_REQ_FMT ", "
+ "pre-emphasis request: " TRAIN_REQ_FMT ", at %s\n",
+ encoder->base.base.id, encoder->base.name,
+ crtc_state->lane_count,
+ TRAIN_REQ_VSWING_ARGS(link_status),
+ TRAIN_REQ_PREEMPH_ARGS(link_status),
+ intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
+
for (lane = 0; lane < 4; lane++)
intel_dp->train_set[lane] =
intel_dp_get_lane_adjust_train(intel_dp, crtc_state,
--
2.32.0
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH v2 4/5] drm/i915: Pimp link training debug prints
2021-10-04 17:05 [Intel-gfx] [PATCH v2 0/5] drm/i915: Improve DP link training further Ville Syrjala
` (2 preceding siblings ...)
2021-10-04 17:05 ` [Intel-gfx] [PATCH v2 3/5] drm/i915: Print the DP vswing adjustment request Ville Syrjala
@ 2021-10-04 17:05 ` Ville Syrjala
2021-10-06 16:09 ` Imre Deak
2021-10-04 17:05 ` [Intel-gfx] [PATCH v2 5/5] drm/i915: Call intel_dp_dump_link_status() for CR failures Ville Syrjala
` (7 subsequent siblings)
11 siblings, 1 reply; 21+ messages in thread
From: Ville Syrjala @ 2021-10-04 17:05 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Unify all debug prints during link training to include information
on both the encoder and the LTTPR. We unify the format to something
like "[ENCODER:1:FOO][LTTPR 1] Something something". Though not
sure if those brackets around the dp_phy just make it look like
line noise? I'll accept suggestions on better formatting.
I'm slightly on the fence about also including the connector,
but technically only the DPRX is the SST connector (ie.
intel_dp->attached_connector). I suppose you could think of it
as the branch device/whatever in the topology, and we're training
the link leading to it. So that could argue for its inclusion.
But it's all getting a bit long alrady, so not going to do it
I think.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/intel_dp_link_training.c | 167 +++++++++++-------
1 file changed, 106 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 5657be1461ec..18f4b469766e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -25,15 +25,6 @@
#include "intel_dp.h"
#include "intel_dp_link_training.h"
-static void
-intel_dp_dump_link_status(struct drm_device *drm,
- const u8 link_status[DP_LINK_STATUS_SIZE])
-{
- drm_dbg_kms(drm,
- "ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x\n",
- link_status[0], link_status[1], link_status[2],
- link_status[3], link_status[4], link_status[5]);
-}
static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp)
{
@@ -66,6 +57,7 @@ static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp,
static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
enum drm_dp_phy dp_phy)
{
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
char phy_name[10];
@@ -73,21 +65,22 @@ static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dp_phy, phy_caps) < 0) {
drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
- "failed to read the PHY caps for %s\n",
- phy_name);
+ "[ENCODER:%d:%s][%s] failed to read the PHY caps\n",
+ encoder->base.base.id, encoder->base.name, phy_name);
return;
}
drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
- "%s PHY capabilities: %*ph\n",
- phy_name,
+ "[ENCODER:%d:%s][%s] PHY capabilities: %*ph\n",
+ encoder->base.base.id, encoder->base.name, phy_name,
(int)sizeof(intel_dp->lttpr_phy_caps[0]),
phy_caps);
}
static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp)
{
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
if (intel_dp_is_edp(intel_dp))
return false;
@@ -104,7 +97,8 @@ static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp)
goto reset_caps;
drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
- "LTTPR common capabilities: %*ph\n",
+ "[ENCODER:%d:%s] LTTPR common capabilities: %*ph\n",
+ encoder->base.base.id, encoder->base.name,
(int)sizeof(intel_dp->lttpr_common_caps),
intel_dp->lttpr_common_caps);
@@ -130,6 +124,8 @@ intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable)
static int intel_dp_init_lttpr(struct intel_dp *intel_dp)
{
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
int lttpr_count;
int i;
@@ -161,8 +157,9 @@ static int intel_dp_init_lttpr(struct intel_dp *intel_dp)
return 0;
if (!intel_dp_set_lttpr_transparent_mode(intel_dp, false)) {
- drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
- "Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n");
+ drm_dbg_kms(&i915->drm,
+ "[ENCODER:%d:%s] Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n",
+ encoder->base.base.id, encoder->base.name);
intel_dp_set_lttpr_transparent_mode(intel_dp, true);
intel_dp_reset_lttpr_count(intel_dp);
@@ -366,17 +363,18 @@ intel_dp_get_adjust_train(struct intel_dp *intel_dp,
const u8 link_status[DP_LINK_STATUS_SIZE])
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
char phy_name[10];
int lane;
- drm_dbg_kms(encoder->base.dev, "[ENCODER:%d:%s] lanes: %d, "
+ drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s][%s] lanes: %d, "
"vswing request: " TRAIN_REQ_FMT ", "
- "pre-emphasis request: " TRAIN_REQ_FMT ", at %s\n",
+ "pre-emphasis request: " TRAIN_REQ_FMT "\n",
encoder->base.base.id, encoder->base.name,
+ intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)),
crtc_state->lane_count,
TRAIN_REQ_VSWING_ARGS(link_status),
- TRAIN_REQ_PREEMPH_ARGS(link_status),
- intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
+ TRAIN_REQ_PREEMPH_ARGS(link_status));
for (lane = 0; lane < 4; lane++)
intel_dp->train_set[lane] =
@@ -435,16 +433,16 @@ intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
u8 dp_train_pat)
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat);
char phy_name[10];
if (train_pat != DP_TRAINING_PATTERN_DISABLE)
- drm_dbg_kms(&dev_priv->drm,
- "[ENCODER:%d:%s] Using DP training pattern TPS%c, at %s\n",
+ drm_dbg_kms(&i915->drm,
+ "[ENCODER:%d:%s][%s] Using DP training pattern TPS%c\n",
encoder->base.base.id, encoder->base.name,
- dp_training_pattern_name(train_pat),
- intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
+ intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)),
+ dp_training_pattern_name(train_pat));
intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
}
@@ -472,17 +470,17 @@ void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
enum drm_dp_phy dp_phy)
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
char phy_name[10];
- drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] lanes: %d, "
+ drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s][%s] lanes: %d, "
"vswing levels: " TRAIN_SET_FMT ", "
- "pre-emphasis levels: " TRAIN_SET_FMT ", at %s\n",
+ "pre-emphasis levels: " TRAIN_SET_FMT "\n",
encoder->base.base.id, encoder->base.name,
+ intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)),
crtc_state->lane_count,
TRAIN_SET_VSWING_ARGS(intel_dp->train_set),
- TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set),
- intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
+ TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set));
if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
encoder->set_signal_levels(encoder, crtc_state);
@@ -554,7 +552,8 @@ static bool
intel_dp_prepare_link_train(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
u8 link_config[2];
u8 link_bw, rate_select;
@@ -566,10 +565,12 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
if (link_bw)
drm_dbg_kms(&i915->drm,
- "Using LINK_BW_SET value %02x\n", link_bw);
+ "[ENCODER:%d:%s] Using LINK_BW_SET value %02x\n",
+ encoder->base.base.id, encoder->base.name, link_bw);
else
drm_dbg_kms(&i915->drm,
- "Using LINK_RATE_SET value %02x\n", rate_select);
+ "[ENCODER:%d:%s] Using LINK_RATE_SET value %02x\n",
+ encoder->base.base.id, encoder->base.name, rate_select);
/* Write the link configuration data */
link_config[0] = link_bw;
@@ -619,6 +620,22 @@ static bool intel_dp_adjust_request_changed(int lane_count,
return false;
}
+static void
+intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy,
+ const u8 link_status[DP_LINK_STATUS_SIZE])
+{
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ char phy_name[10];
+
+ drm_dbg_kms(&i915->drm,
+ "[ENCODER:%d:%s][%s] ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x\n",
+ encoder->base.base.id, encoder->base.name,
+ intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)),
+ link_status[0], link_status[1], link_status[2],
+ link_status[3], link_status[4], link_status[5]);
+}
+
/*
* Perform the link training clock recovery phase on the given DP PHY using
* training pattern 1.
@@ -628,16 +645,21 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
enum drm_dp_phy dp_phy)
{
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
u8 old_link_status[DP_LINK_STATUS_SIZE] = {};
int voltage_tries, cr_tries, max_cr_tries;
bool max_vswing_reached = false;
+ char phy_name[10];
+
+ intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name));
/* clock recovery */
if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy,
DP_TRAINING_PATTERN_1 |
DP_LINK_SCRAMBLING_DISABLE)) {
- drm_err(&i915->drm, "failed to enable link training\n");
+ drm_err(&i915->drm, "[ENCODER:%d:%s][%s] Failed to enable link training\n",
+ encoder->base.base.id, encoder->base.name, phy_name);
return false;
}
@@ -662,23 +684,29 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
link_status) < 0) {
- drm_err(&i915->drm, "failed to get link status\n");
+ drm_err(&i915->drm, "[ENCODER:%d:%s][%s] Failed to get link status\n",
+ encoder->base.base.id, encoder->base.name, phy_name);
return false;
}
if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) {
- drm_dbg_kms(&i915->drm, "clock recovery OK\n");
+ drm_dbg_kms(&i915->drm,
+ "[ENCODER:%d:%s][%s] Clock recovery OK\n",
+ encoder->base.base.id, encoder->base.name, phy_name);
return true;
}
if (voltage_tries == 5) {
drm_dbg_kms(&i915->drm,
- "Same voltage tried 5 times\n");
+ "[ENCODER:%d:%s][%s] Same voltage tried 5 times\n",
+ encoder->base.base.id, encoder->base.name, phy_name);
return false;
}
if (max_vswing_reached) {
- drm_dbg_kms(&i915->drm, "Max Voltage Swing reached\n");
+ drm_dbg_kms(&i915->drm,
+ "[ENCODER:%d:%s][%s] Max Voltage Swing reached\n",
+ encoder->base.base.id, encoder->base.name, phy_name);
return false;
}
@@ -687,7 +715,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
link_status);
if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
drm_err(&i915->drm,
- "failed to update link training\n");
+ "[ENCODER:%d:%s][%s] Failed to update link training\n",
+ encoder->base.base.id, encoder->base.name, phy_name);
return false;
}
@@ -701,10 +730,12 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state))
max_vswing_reached = true;
-
}
+
drm_err(&i915->drm,
- "Failed clock recovery %d times, giving up!\n", max_cr_tries);
+ "[ENCODER:%d:%s][%s] Failed clock recovery %d times, giving up!\n",
+ encoder->base.base.id, encoder->base.name, phy_name, max_cr_tries);
+
return false;
}
@@ -788,11 +819,15 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
enum drm_dp_phy dp_phy)
{
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
int tries;
u32 training_pattern;
u8 link_status[DP_LINK_STATUS_SIZE];
bool channel_eq = false;
+ char phy_name[10];
+
+ intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name));
training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy);
/* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
@@ -802,7 +837,10 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
/* channel equalization */
if (!intel_dp_set_link_train(intel_dp, crtc_state, dp_phy,
training_pattern)) {
- drm_err(&i915->drm, "failed to start channel equalization\n");
+ drm_err(&i915->drm,
+ "[ENCODER:%d:%s][%s] Failed to start channel equalization\n",
+ encoder->base.base.id, encoder->base.name,
+ phy_name);
return false;
}
@@ -812,25 +850,28 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
link_status) < 0) {
drm_err(&i915->drm,
- "failed to get link status\n");
+ "[ENCODER:%d:%s][%s] Failed to get link status\n",
+ encoder->base.base.id, encoder->base.name, phy_name);
break;
}
/* Make sure clock is still ok */
if (!drm_dp_clock_recovery_ok(link_status,
crtc_state->lane_count)) {
- intel_dp_dump_link_status(&i915->drm, link_status);
+ intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
drm_dbg_kms(&i915->drm,
- "Clock recovery check failed, cannot "
- "continue channel equalization\n");
+ "[ENCODER:%d:%s][%s] Clock recovery check failed, cannot "
+ "continue channel equalization\n",
+ encoder->base.base.id, encoder->base.name, phy_name);
break;
}
if (drm_dp_channel_eq_ok(link_status,
crtc_state->lane_count)) {
channel_eq = true;
- drm_dbg_kms(&i915->drm, "Channel EQ done. DP Training "
- "successful\n");
+ drm_dbg_kms(&i915->drm,
+ "[ENCODER:%d:%s][%s] Channel EQ done. DP Training successful\n",
+ encoder->base.base.id, encoder->base.name, phy_name);
break;
}
@@ -839,16 +880,18 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
link_status);
if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
drm_err(&i915->drm,
- "failed to update link training\n");
+ "[ENCODER:%d:%s][%s] Failed to update link training\n",
+ encoder->base.base.id, encoder->base.name, phy_name);
break;
}
}
/* Try 5 times, else fail and try at lower BW */
if (tries == 5) {
- intel_dp_dump_link_status(&i915->drm, link_status);
+ intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
drm_dbg_kms(&i915->drm,
- "Channel equalization failed 5 times\n");
+ "[ENCODER:%d:%s][%s] Channel equalization failed 5 times\n",
+ encoder->base.base.id, encoder->base.name, phy_name);
}
return channel_eq;
@@ -894,7 +937,7 @@ intel_dp_link_train_phy(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
enum drm_dp_phy dp_phy)
{
- struct intel_connector *intel_connector = intel_dp->attached_connector;
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
char phy_name[10];
bool ret = false;
@@ -908,12 +951,11 @@ intel_dp_link_train_phy(struct intel_dp *intel_dp,
out:
drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
- "[CONNECTOR:%d:%s] Link Training %s at link rate = %d, lane count = %d, at %s\n",
- intel_connector->base.base.id,
- intel_connector->base.name,
+ "[ENCODER:%d:%s][%s] Link Training %s at link rate = %d, lane count = %d\n",
+ encoder->base.base.id, encoder->base.name,
+ intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)),
ret ? "passed" : "failed",
- crtc_state->port_clock, crtc_state->lane_count,
- intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
+ crtc_state->port_clock, crtc_state->lane_count);
return ret;
}
@@ -922,10 +964,13 @@ static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
struct intel_connector *intel_connector = intel_dp->attached_connector;
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
if (intel_dp->hobl_active) {
drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
- "Link Training failed with HOBL active, not enabling it from now on");
+ "[ENCODER:%d:%s] Link Training failed with HOBL active, "
+ "not enabling it from now on",
+ encoder->base.base.id, encoder->base.name);
intel_dp->hobl_failed = true;
} else if (intel_dp_get_link_train_fallback_values(intel_dp,
crtc_state->port_clock,
--
2.32.0
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH v2 5/5] drm/i915: Call intel_dp_dump_link_status() for CR failures
2021-10-04 17:05 [Intel-gfx] [PATCH v2 0/5] drm/i915: Improve DP link training further Ville Syrjala
` (3 preceding siblings ...)
2021-10-04 17:05 ` [Intel-gfx] [PATCH v2 4/5] drm/i915: Pimp link training debug prints Ville Syrjala
@ 2021-10-04 17:05 ` Ville Syrjala
2021-10-06 16:12 ` Imre Deak
2021-10-04 18:55 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Improve DP link training further (rev2) Patchwork
` (6 subsequent siblings)
11 siblings, 1 reply; 21+ messages in thread
From: Ville Syrjala @ 2021-10-04 17:05 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
I suppose intel_dp_dump_link_status() might be useful for diagnosing
link training failures. Hoever we only call from the channel EQ phase
currently. Let's call it from the CR phase as well.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 18f4b469766e..c92044710012 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -649,6 +649,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
u8 old_link_status[DP_LINK_STATUS_SIZE] = {};
int voltage_tries, cr_tries, max_cr_tries;
+ u8 link_status[DP_LINK_STATUS_SIZE];
bool max_vswing_reached = false;
char phy_name[10];
@@ -678,8 +679,6 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
voltage_tries = 1;
for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
- u8 link_status[DP_LINK_STATUS_SIZE];
-
intel_dp_link_training_clock_recovery_delay(intel_dp, dp_phy);
if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
@@ -697,6 +696,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
}
if (voltage_tries == 5) {
+ intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
drm_dbg_kms(&i915->drm,
"[ENCODER:%d:%s][%s] Same voltage tried 5 times\n",
encoder->base.base.id, encoder->base.name, phy_name);
@@ -704,6 +704,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
}
if (max_vswing_reached) {
+ intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
drm_dbg_kms(&i915->drm,
"[ENCODER:%d:%s][%s] Max Voltage Swing reached\n",
encoder->base.base.id, encoder->base.name, phy_name);
@@ -732,6 +733,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
max_vswing_reached = true;
}
+ intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
drm_err(&i915->drm,
"[ENCODER:%d:%s][%s] Failed clock recovery %d times, giving up!\n",
encoder->base.base.id, encoder->base.name, phy_name, max_cr_tries);
--
2.32.0
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Improve DP link training further (rev2)
2021-10-04 17:05 [Intel-gfx] [PATCH v2 0/5] drm/i915: Improve DP link training further Ville Syrjala
` (4 preceding siblings ...)
2021-10-04 17:05 ` [Intel-gfx] [PATCH v2 5/5] drm/i915: Call intel_dp_dump_link_status() for CR failures Ville Syrjala
@ 2021-10-04 18:55 ` Patchwork
2021-10-04 23:46 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Improve DP link training further (rev3) Patchwork
` (5 subsequent siblings)
11 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2021-10-04 18:55 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Improve DP link training further (rev2)
URL : https://patchwork.freedesktop.org/series/95405/
State : failure
== Summary ==
Applying: drm/i915: Tweak the DP "max vswing reached?" condition
Applying: drm/i915: Show LTTPR in the TPS debug print
Applying: drm/i915: Print the DP vswing adjustment request
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/display/intel_dp_link_training.c).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0003 drm/i915: Print the DP vswing adjustment request
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Improve DP link training further (rev3)
2021-10-04 17:05 [Intel-gfx] [PATCH v2 0/5] drm/i915: Improve DP link training further Ville Syrjala
` (5 preceding siblings ...)
2021-10-04 18:55 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Improve DP link training further (rev2) Patchwork
@ 2021-10-04 23:46 ` Patchwork
2021-10-05 12:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve DP link training further (rev4) Patchwork
` (4 subsequent siblings)
11 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2021-10-04 23:46 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Improve DP link training further (rev3)
URL : https://patchwork.freedesktop.org/series/95405/
State : failure
== Summary ==
Applying: drm/i915: Tweak the DP "max vswing reached?" condition
Applying: drm/i915: Show LTTPR in the TPS debug print
Applying: drm/i915: Print the DP vswing adjustment request
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/display/intel_dp_link_training.c).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0003 drm/i915: Print the DP vswing adjustment request
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve DP link training further (rev4)
2021-10-04 17:05 [Intel-gfx] [PATCH v2 0/5] drm/i915: Improve DP link training further Ville Syrjala
` (6 preceding siblings ...)
2021-10-04 23:46 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Improve DP link training further (rev3) Patchwork
@ 2021-10-05 12:18 ` Patchwork
2021-10-05 12:49 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
` (3 subsequent siblings)
11 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2021-10-05 12:18 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Improve DP link training further (rev4)
URL : https://patchwork.freedesktop.org/series/95405/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
abef31c7b13c drm/i915: Tweak the DP "max vswing reached?" condition
b54d2483d9e1 drm/i915: Show LTTPR in the TPS debug print
5799665e91f9 drm/i915: Print the DP vswing adjustment request
-:25: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#25: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:349:
+#define TRAIN_REQ_VSWING_ARGS(link_status) \
+ _TRAIN_REQ_VSWING_ARGS(link_status, 0), \
+ _TRAIN_REQ_VSWING_ARGS(link_status, 1), \
+ _TRAIN_REQ_VSWING_ARGS(link_status, 2), \
+ _TRAIN_REQ_VSWING_ARGS(link_status, 3)
-:25: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'link_status' - possible side-effects?
#25: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:349:
+#define TRAIN_REQ_VSWING_ARGS(link_status) \
+ _TRAIN_REQ_VSWING_ARGS(link_status, 0), \
+ _TRAIN_REQ_VSWING_ARGS(link_status, 1), \
+ _TRAIN_REQ_VSWING_ARGS(link_status, 2), \
+ _TRAIN_REQ_VSWING_ARGS(link_status, 3)
-:31: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#31: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:355:
+ (drm_dp_get_adjust_request_pre_emphasis((link_status), (lane)) >> DP_TRAIN_PRE_EMPHASIS_SHIFT)
-:32: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#32: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:356:
+#define TRAIN_REQ_PREEMPH_ARGS(link_status) \
+ _TRAIN_REQ_PREEMPH_ARGS(link_status, 0), \
+ _TRAIN_REQ_PREEMPH_ARGS(link_status, 1), \
+ _TRAIN_REQ_PREEMPH_ARGS(link_status, 2), \
+ _TRAIN_REQ_PREEMPH_ARGS(link_status, 3)
-:32: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'link_status' - possible side-effects?
#32: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:356:
+#define TRAIN_REQ_PREEMPH_ARGS(link_status) \
+ _TRAIN_REQ_PREEMPH_ARGS(link_status, 0), \
+ _TRAIN_REQ_PREEMPH_ARGS(link_status, 1), \
+ _TRAIN_REQ_PREEMPH_ARGS(link_status, 2), \
+ _TRAIN_REQ_PREEMPH_ARGS(link_status, 3)
total: 2 errors, 1 warnings, 2 checks, 41 lines checked
189e1f80ff45 drm/i915: Pimp link training debug prints
2581f8d15990 drm/i915: Call intel_dp_dump_link_status() for CR failures
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Improve DP link training further (rev4)
2021-10-04 17:05 [Intel-gfx] [PATCH v2 0/5] drm/i915: Improve DP link training further Ville Syrjala
` (7 preceding siblings ...)
2021-10-05 12:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve DP link training further (rev4) Patchwork
@ 2021-10-05 12:49 ` Patchwork
2021-10-05 13:42 ` Ville Syrjälä
2021-10-05 14:02 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve DP link training further (rev5) Patchwork
` (2 subsequent siblings)
11 siblings, 1 reply; 21+ messages in thread
From: Patchwork @ 2021-10-05 12:49 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 8707 bytes --]
== Series Details ==
Series: drm/i915: Improve DP link training further (rev4)
URL : https://patchwork.freedesktop.org/series/95405/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10683 -> Patchwork_21247
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21247 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21247, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21247/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21247:
### IGT changes ###
#### Possible regressions ####
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21247/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html
Known issues
------------
Here are the changes found in Patchwork_21247 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21247/fi-bsw-kefka/igt@amdgpu/amd_basic@query-info.html
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600: NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21247/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html
* igt@amdgpu/amd_prime@amd-to-i915:
- fi-kbl-x1275: NOTRUN -> [SKIP][4] ([fdo#109271]) +28 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21247/fi-kbl-x1275/igt@amdgpu/amd_prime@amd-to-i915.html
* igt@amdgpu/amd_prime@i915-to-amd:
- fi-snb-2520m: NOTRUN -> [SKIP][5] ([fdo#109271]) +37 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21247/fi-snb-2520m/igt@amdgpu/amd_prime@i915-to-amd.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-u2: NOTRUN -> [SKIP][6] ([i915#2190])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21247/fi-tgl-u2/igt@gem_huc_copy@huc-copy.html
- fi-kbl-x1275: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21247/fi-kbl-x1275/igt@gem_huc_copy@huc-copy.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-tgl-u2: NOTRUN -> [SKIP][8] ([fdo#109284] / [fdo#111827]) +8 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21247/fi-tgl-u2/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-kbl-x1275: NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21247/fi-kbl-x1275/igt@kms_chamelium@hdmi-crc-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-snb-2520m: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21247/fi-snb-2520m/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-u2: NOTRUN -> [SKIP][11] ([i915#4103]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21247/fi-tgl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-u2: NOTRUN -> [SKIP][12] ([fdo#109285])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21247/fi-tgl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-x1275: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#533])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21247/fi-kbl-x1275/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-u2: NOTRUN -> [SKIP][14] ([i915#3301])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21247/fi-tgl-u2/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-tgl-u2: NOTRUN -> [FAIL][15] ([i915#1602] / [i915#2722])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21247/fi-tgl-u2/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: [INCOMPLETE][16] ([i915#2940]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21247/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [INCOMPLETE][18] ([i915#3921]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21247/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@kms_flip@basic-flip-vs-wf_vblank@c-dp1:
- fi-cfl-8109u: [FAIL][20] ([i915#4165]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-wf_vblank@c-dp1.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21247/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-wf_vblank@c-dp1.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [DMESG-WARN][22] ([i915#295]) -> [PASS][23] +17 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21247/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
#### Warnings ####
* igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u: [DMESG-WARN][24] ([i915#295]) -> [FAIL][25] ([i915#2546])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21247/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4165]: https://gitlab.freedesktop.org/drm/intel/issues/4165
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Participating hosts (38 -> 35)
------------------------------
Additional (3): fi-kbl-x1275 fi-snb-2520m fi-tgl-u2
Missing (6): bat-dg1-6 fi-bsw-cyan bat-adlp-4 fi-bdw-samus bat-jsl-2 bat-jsl-1
Build changes
-------------
* Linux: CI_DRM_10683 -> Patchwork_21247
CI-20190529: 20190529
CI_DRM_10683: 2db2331e0b19308750c3b921c2779c4c2da9b04b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6230: a079f2e00693facf4cf6512f0ddb69b30826c80f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21247: 2581f8d15990379f0cf43e88bf8f5dc590e7274c @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
2581f8d15990 drm/i915: Call intel_dp_dump_link_status() for CR failures
189e1f80ff45 drm/i915: Pimp link training debug prints
5799665e91f9 drm/i915: Print the DP vswing adjustment request
b54d2483d9e1 drm/i915: Show LTTPR in the TPS debug print
abef31c7b13c drm/i915: Tweak the DP "max vswing reached?" condition
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21247/index.html
[-- Attachment #2: Type: text/html, Size: 10508 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Improve DP link training further (rev4)
2021-10-05 12:49 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2021-10-05 13:42 ` Ville Syrjälä
0 siblings, 0 replies; 21+ messages in thread
From: Ville Syrjälä @ 2021-10-05 13:42 UTC (permalink / raw)
To: intel-gfx
On Tue, Oct 05, 2021 at 12:49:53PM -0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Improve DP link training further (rev4)
> URL : https://patchwork.freedesktop.org/series/95405/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_10683 -> Patchwork_21247
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_21247 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_21247, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21247/index.html
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_21247:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@core_hotunplug@unbind-rebind:
> - fi-tgl-u2: NOTRUN -> [INCOMPLETE][1]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21247/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html
That looks like a straight up race during unbind. We turn off
interrupts first, only then we cancel the hpd stuff (including the
modeset_retry work) which presuambly was already running and told
fb_helper that stuff happened, then the fb_helper proceeds to do
a modeset while interrupts are already off and we're in the middle
of tearing down the driver, and all hell breaks loose as a result.
Unrelated to these patches, I *think*. I'll hit retest anyway to
make sure.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve DP link training further (rev5)
2021-10-04 17:05 [Intel-gfx] [PATCH v2 0/5] drm/i915: Improve DP link training further Ville Syrjala
` (8 preceding siblings ...)
2021-10-05 12:49 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2021-10-05 14:02 ` Patchwork
2021-10-05 14:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-05 18:25 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
11 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2021-10-05 14:02 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Improve DP link training further (rev5)
URL : https://patchwork.freedesktop.org/series/95405/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
dee501a3511e drm/i915: Tweak the DP "max vswing reached?" condition
94bb4313c0df drm/i915: Show LTTPR in the TPS debug print
ddfa1864e7d7 drm/i915: Print the DP vswing adjustment request
-:25: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#25: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:349:
+#define TRAIN_REQ_VSWING_ARGS(link_status) \
+ _TRAIN_REQ_VSWING_ARGS(link_status, 0), \
+ _TRAIN_REQ_VSWING_ARGS(link_status, 1), \
+ _TRAIN_REQ_VSWING_ARGS(link_status, 2), \
+ _TRAIN_REQ_VSWING_ARGS(link_status, 3)
-:25: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'link_status' - possible side-effects?
#25: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:349:
+#define TRAIN_REQ_VSWING_ARGS(link_status) \
+ _TRAIN_REQ_VSWING_ARGS(link_status, 0), \
+ _TRAIN_REQ_VSWING_ARGS(link_status, 1), \
+ _TRAIN_REQ_VSWING_ARGS(link_status, 2), \
+ _TRAIN_REQ_VSWING_ARGS(link_status, 3)
-:31: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#31: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:355:
+ (drm_dp_get_adjust_request_pre_emphasis((link_status), (lane)) >> DP_TRAIN_PRE_EMPHASIS_SHIFT)
-:32: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#32: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:356:
+#define TRAIN_REQ_PREEMPH_ARGS(link_status) \
+ _TRAIN_REQ_PREEMPH_ARGS(link_status, 0), \
+ _TRAIN_REQ_PREEMPH_ARGS(link_status, 1), \
+ _TRAIN_REQ_PREEMPH_ARGS(link_status, 2), \
+ _TRAIN_REQ_PREEMPH_ARGS(link_status, 3)
-:32: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'link_status' - possible side-effects?
#32: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:356:
+#define TRAIN_REQ_PREEMPH_ARGS(link_status) \
+ _TRAIN_REQ_PREEMPH_ARGS(link_status, 0), \
+ _TRAIN_REQ_PREEMPH_ARGS(link_status, 1), \
+ _TRAIN_REQ_PREEMPH_ARGS(link_status, 2), \
+ _TRAIN_REQ_PREEMPH_ARGS(link_status, 3)
total: 2 errors, 1 warnings, 2 checks, 41 lines checked
15ce918cc135 drm/i915: Pimp link training debug prints
dbbc7aeca18a drm/i915: Call intel_dp_dump_link_status() for CR failures
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Improve DP link training further (rev5)
2021-10-04 17:05 [Intel-gfx] [PATCH v2 0/5] drm/i915: Improve DP link training further Ville Syrjala
` (9 preceding siblings ...)
2021-10-05 14:02 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve DP link training further (rev5) Patchwork
@ 2021-10-05 14:35 ` Patchwork
2021-10-05 18:25 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
11 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2021-10-05 14:35 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4942 bytes --]
== Series Details ==
Series: drm/i915: Improve DP link training further (rev5)
URL : https://patchwork.freedesktop.org/series/95405/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10683 -> Patchwork_21250
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/index.html
Known issues
------------
Here are the changes found in Patchwork_21250 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/fi-bsw-kefka/igt@amdgpu/amd_basic@query-info.html
* igt@amdgpu/amd_prime@amd-to-i915:
- fi-kbl-x1275: NOTRUN -> [SKIP][2] ([fdo#109271]) +28 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/fi-kbl-x1275/igt@amdgpu/amd_prime@amd-to-i915.html
* igt@amdgpu/amd_prime@i915-to-amd:
- fi-snb-2520m: NOTRUN -> [SKIP][3] ([fdo#109271]) +37 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/fi-snb-2520m/igt@amdgpu/amd_prime@i915-to-amd.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-x1275: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/fi-kbl-x1275/igt@gem_huc_copy@huc-copy.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-kbl-x1275: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/fi-kbl-x1275/igt@kms_chamelium@hdmi-crc-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-snb-2520m: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/fi-snb-2520m/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-x1275: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#533])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/fi-kbl-x1275/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
#### Possible fixes ####
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: [INCOMPLETE][8] ([i915#2940]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
* igt@kms_flip@basic-flip-vs-modeset@c-dp1:
- fi-cfl-8109u: [FAIL][10] ([i915#4165]) -> [PASS][11] +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-modeset@c-dp1.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-modeset@c-dp1.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [DMESG-WARN][12] ([i915#295]) -> [PASS][13] +18 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#4165]: https://gitlab.freedesktop.org/drm/intel/issues/4165
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Participating hosts (38 -> 34)
------------------------------
Additional (2): fi-kbl-x1275 fi-snb-2520m
Missing (6): bat-dg1-6 fi-bsw-cyan bat-adlp-4 fi-bdw-samus bat-jsl-2 bat-jsl-1
Build changes
-------------
* Linux: CI_DRM_10683 -> Patchwork_21250
CI-20190529: 20190529
CI_DRM_10683: 2db2331e0b19308750c3b921c2779c4c2da9b04b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6230: a079f2e00693facf4cf6512f0ddb69b30826c80f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21250: dbbc7aeca18af7e73feebf885dd1c105c585370f @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
dbbc7aeca18a drm/i915: Call intel_dp_dump_link_status() for CR failures
15ce918cc135 drm/i915: Pimp link training debug prints
ddfa1864e7d7 drm/i915: Print the DP vswing adjustment request
94bb4313c0df drm/i915: Show LTTPR in the TPS debug print
dee501a3511e drm/i915: Tweak the DP "max vswing reached?" condition
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/index.html
[-- Attachment #2: Type: text/html, Size: 6282 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Improve DP link training further (rev5)
2021-10-04 17:05 [Intel-gfx] [PATCH v2 0/5] drm/i915: Improve DP link training further Ville Syrjala
` (10 preceding siblings ...)
2021-10-05 14:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-10-05 18:25 ` Patchwork
11 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2021-10-05 18:25 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30272 bytes --]
== Series Details ==
Series: drm/i915: Improve DP link training further (rev5)
URL : https://patchwork.freedesktop.org/series/95405/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10683_full -> Patchwork_21250_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_21250_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-apl: NOTRUN -> [DMESG-WARN][1] ([i915#3002])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-apl8/igt@gem_create@create-massive.html
* igt@gem_ctx_persistence@process:
- shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +3 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-snb7/igt@gem_ctx_persistence@process.html
* igt@gem_ctx_sseu@invalid-args:
- shard-tglb: NOTRUN -> [SKIP][3] ([i915#280])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-tglb3/igt@gem_ctx_sseu@invalid-args.html
* igt@gem_exec_fair@basic-deadline:
- shard-skl: NOTRUN -> [FAIL][4] ([i915#2846])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-skl2/igt@gem_exec_fair@basic-deadline.html
- shard-apl: NOTRUN -> [FAIL][5] ([i915#2846])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-apl2/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-apl: [PASS][6] -> [FAIL][7] ([i915#2842] / [i915#3468])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-apl3/igt@gem_exec_fair@basic-none@vecs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-apl8/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][8] -> [FAIL][9] ([i915#2842])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][10] ([i915#2842])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-iclb2/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][11] -> [FAIL][12] ([i915#2849])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_whisper@basic-fds-all:
- shard-glk: [PASS][13] -> [DMESG-WARN][14] ([i915#118] / [i915#95])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-glk8/igt@gem_exec_whisper@basic-fds-all.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-glk7/igt@gem_exec_whisper@basic-fds-all.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#2190])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-apl1/igt@gem_huc_copy@huc-copy.html
* igt@gem_render_copy@linear-to-vebox-y-tiled:
- shard-apl: NOTRUN -> [SKIP][16] ([fdo#109271]) +229 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-apl3/igt@gem_render_copy@linear-to-vebox-y-tiled.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#3323])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-apl2/igt@gem_userptr_blits@dmabuf-sync.html
- shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#3323])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-skl2/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@input-checking:
- shard-snb: NOTRUN -> [DMESG-WARN][19] ([i915#3002])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-snb5/igt@gem_userptr_blits@input-checking.html
* igt@gen9_exec_parse@batch-invalid-length:
- shard-snb: NOTRUN -> [SKIP][20] ([fdo#109271]) +319 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-snb7/igt@gen9_exec_parse@batch-invalid-length.html
* igt@i915_pm_backlight@fade_with_suspend:
- shard-tglb: [PASS][21] -> [INCOMPLETE][22] ([i915#456]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-tglb5/igt@i915_pm_backlight@fade_with_suspend.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-tglb7/igt@i915_pm_backlight@fade_with_suspend.html
* igt@i915_pm_dc@dc6-dpms:
- shard-kbl: NOTRUN -> [FAIL][23] ([i915#454])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-kbl2/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_dc@dc6-psr:
- shard-skl: NOTRUN -> [FAIL][24] ([i915#454])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-skl2/igt@i915_pm_dc@dc6-psr.html
* igt@i915_query@query-topology-known-pci-ids:
- shard-tglb: NOTRUN -> [SKIP][25] ([fdo#109303])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-tglb3/igt@i915_query@query-topology-known-pci-ids.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [PASS][26] -> [INCOMPLETE][27] ([i915#3921])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-snb2/igt@i915_selftest@live@hangcheck.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-snb6/igt@i915_selftest@live@hangcheck.html
* igt@i915_suspend@sysfs-reader:
- shard-kbl: NOTRUN -> [DMESG-WARN][28] ([i915#180])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-kbl1/igt@i915_suspend@sysfs-reader.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-skl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#3777])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-skl2/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-kbl: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#3777]) +2 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-kbl2/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][31] ([fdo#111614])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-tglb2/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][32] ([i915#3722])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-skl2/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-apl: NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3777]) +2 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-apl1/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-tglb: NOTRUN -> [SKIP][34] ([fdo#111615]) +1 similar issue
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-tglb3/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][35] ([i915#3689] / [i915#3886])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-tglb2/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#3886]) +4 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-kbl7/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#3886]) +4 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-skl2/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3886]) +11 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-apl3/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs:
- shard-iclb: NOTRUN -> [SKIP][39] ([fdo#109278])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-iclb6/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-d-missing-ccs-buffer-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][40] ([i915#3689]) +5 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-tglb3/igt@kms_ccs@pipe-d-missing-ccs-buffer-yf_tiled_ccs.html
* igt@kms_chamelium@hdmi-edid-read:
- shard-tglb: NOTRUN -> [SKIP][41] ([fdo#109284] / [fdo#111827]) +6 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-tglb3/igt@kms_chamelium@hdmi-edid-read.html
* igt@kms_chamelium@hdmi-mode-timings:
- shard-snb: NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +15 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-snb7/igt@kms_chamelium@hdmi-mode-timings.html
* igt@kms_chamelium@vga-edid-read:
- shard-apl: NOTRUN -> [SKIP][43] ([fdo#109271] / [fdo#111827]) +17 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-apl8/igt@kms_chamelium@vga-edid-read.html
* igt@kms_color@pipe-a-ctm-green-to-red:
- shard-skl: [PASS][44] -> [DMESG-WARN][45] ([i915#1982])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-skl3/igt@kms_color@pipe-a-ctm-green-to-red.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-skl4/igt@kms_color@pipe-a-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-a-degamma:
- shard-kbl: NOTRUN -> [SKIP][46] ([fdo#109271] / [fdo#111827]) +6 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-kbl2/igt@kms_color_chamelium@pipe-a-degamma.html
* igt@kms_color_chamelium@pipe-b-ctm-max:
- shard-skl: NOTRUN -> [SKIP][47] ([fdo#109271] / [fdo#111827]) +5 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-skl2/igt@kms_color_chamelium@pipe-b-ctm-max.html
* igt@kms_content_protection@atomic:
- shard-kbl: NOTRUN -> [TIMEOUT][48] ([i915#1319]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-kbl2/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@atomic-dpms:
- shard-apl: NOTRUN -> [TIMEOUT][49] ([i915#1319])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-apl2/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-tglb: NOTRUN -> [SKIP][50] ([i915#3116])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-tglb3/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_content_protection@legacy:
- shard-iclb: NOTRUN -> [SKIP][51] ([fdo#109300] / [fdo#111066])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-iclb6/igt@kms_content_protection@legacy.html
* igt@kms_cursor_crc@pipe-c-cursor-32x32-sliding:
- shard-tglb: NOTRUN -> [SKIP][52] ([i915#3319])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-tglb3/igt@kms_cursor_crc@pipe-c-cursor-32x32-sliding.html
* igt@kms_cursor_crc@pipe-c-cursor-512x512-random:
- shard-skl: NOTRUN -> [SKIP][53] ([fdo#109271]) +62 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-512x512-random.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [PASS][54] -> [DMESG-WARN][55] ([i915#180])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-apl8/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-apl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding:
- shard-tglb: NOTRUN -> [SKIP][56] ([fdo#109279] / [i915#3359]) +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-tglb3/igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding.html
* igt@kms_cursor_crc@pipe-d-cursor-max-size-rapid-movement:
- shard-tglb: NOTRUN -> [SKIP][57] ([i915#3359]) +3 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-tglb3/igt@kms_cursor_crc@pipe-d-cursor-max-size-rapid-movement.html
* igt@kms_cursor_crc@pipe-d-cursor-suspend:
- shard-tglb: [PASS][58] -> [INCOMPLETE][59] ([i915#4211])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-tglb8/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-tglb7/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
* igt@kms_fbcon_fbt@fbc:
- shard-glk: [PASS][60] -> [FAIL][61] ([i915#64])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-glk1/igt@kms_fbcon_fbt@fbc.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-glk5/igt@kms_fbcon_fbt@fbc.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [PASS][62] -> [FAIL][63] ([i915#79]) +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1:
- shard-glk: [PASS][64] -> [FAIL][65] ([i915#79])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-glk5/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile:
- shard-iclb: [PASS][66] -> [SKIP][67] ([i915#3701])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbcpsr-suspend:
- shard-tglb: [PASS][68] -> [INCOMPLETE][69] ([i915#2411] / [i915#456])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-move:
- shard-tglb: NOTRUN -> [SKIP][70] ([fdo#111825]) +18 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-tglb3/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-move.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: NOTRUN -> [FAIL][71] ([i915#1188])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#533])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-apl3/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
- shard-kbl: [PASS][73] -> [DMESG-WARN][74] ([i915#180]) +4 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][75] ([fdo#108145] / [i915#265]) +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
- shard-kbl: NOTRUN -> [FAIL][76] ([fdo#108145] / [i915#265])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-kbl7/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][77] ([i915#265])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-kbl2/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: NOTRUN -> [FAIL][78] ([fdo#108145] / [i915#265])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][79] -> [FAIL][80] ([fdo#108145] / [i915#265]) +1 similar issue
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_plane_lowres@pipe-d-tiling-x:
- shard-tglb: NOTRUN -> [SKIP][81] ([i915#3536])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-tglb3/igt@kms_plane_lowres@pipe-d-tiling-x.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1:
- shard-tglb: NOTRUN -> [SKIP][82] ([i915#2920])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-tglb3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-0:
- shard-kbl: NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#658])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-kbl7/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-2:
- shard-apl: NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#658]) +4 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-apl3/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html
* igt@kms_psr@cursor_plane_onoff:
- shard-kbl: NOTRUN -> [SKIP][85] ([fdo#109271]) +96 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-kbl7/igt@kms_psr@cursor_plane_onoff.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [PASS][86] -> [SKIP][87] ([fdo#109441]) +2 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-iclb1/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_psr@psr2_dpms:
- shard-tglb: NOTRUN -> [FAIL][88] ([i915#132] / [i915#3467])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-tglb3/igt@kms_psr@psr2_dpms.html
* igt@kms_setmode@basic:
- shard-snb: NOTRUN -> [FAIL][89] ([i915#31])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-snb5/igt@kms_setmode@basic.html
* igt@kms_writeback@writeback-check-output:
- shard-apl: NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#2437]) +1 similar issue
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-apl6/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-fb-id:
- shard-kbl: NOTRUN -> [SKIP][91] ([fdo#109271] / [i915#2437]) +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-kbl2/igt@kms_writeback@writeback-fb-id.html
* igt@nouveau_crc@pipe-a-source-outp-inactive:
- shard-tglb: NOTRUN -> [SKIP][92] ([i915#2530])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-tglb3/igt@nouveau_crc@pipe-a-source-outp-inactive.html
* igt@perf@polling:
- shard-skl: [PASS][93] -> [FAIL][94] ([i915#1542])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-skl7/igt@perf@polling.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-skl5/igt@perf@polling.html
* igt@perf_pmu@rc6-suspend:
- shard-skl: [PASS][95] -> [INCOMPLETE][96] ([i915#198]) +1 similar issue
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-skl10/igt@perf_pmu@rc6-suspend.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-skl3/igt@perf_pmu@rc6-suspend.html
* igt@prime_nv_api@i915_self_import:
- shard-tglb: NOTRUN -> [SKIP][97] ([fdo#109291])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-tglb3/igt@prime_nv_api@i915_self_import.html
* igt@sysfs_clients@sema-50:
- shard-kbl: NOTRUN -> [SKIP][98] ([fdo#109271] / [i915#2994]) +2 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-kbl7/igt@sysfs_clients@sema-50.html
- shard-apl: NOTRUN -> [SKIP][99] ([fdo#109271] / [i915#2994]) +2 similar issues
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-apl6/igt@sysfs_clients@sema-50.html
- shard-skl: NOTRUN -> [SKIP][100] ([fdo#109271] / [i915#2994])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-skl8/igt@sysfs_clients@sema-50.html
#### Possible fixes ####
* igt@gem_eio@in-flight-contexts-10ms:
- shard-tglb: [TIMEOUT][101] ([i915#3063]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-tglb8/igt@gem_eio@in-flight-contexts-10ms.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-tglb5/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_eio@in-flight-suspend:
- shard-kbl: [DMESG-WARN][103] ([i915#180]) -> [PASS][104] +3 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-kbl4/igt@gem_eio@in-flight-suspend.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-kbl3/igt@gem_eio@in-flight-suspend.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [TIMEOUT][105] ([i915#2369] / [i915#3063] / [i915#3648]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-tglb8/igt@gem_eio@unwedge-stress.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-tglb1/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][107] ([i915#2842]) -> [PASS][108] +1 similar issue
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-tglb3/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: [FAIL][109] ([i915#2842]) -> [PASS][110] +1 similar issue
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-glk2/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-glk6/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [FAIL][111] ([i915#2842]) -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-iclb5/igt@gem_exec_fair@basic-none-share@rcs0.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-iclb1/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: [FAIL][113] ([i915#2842]) -> [PASS][114] +2 similar issues
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-kbl1/igt@gem_exec_fair@basic-none-solo@rcs0.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-kbl2/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [DMESG-WARN][115] ([i915#1436] / [i915#716]) -> [PASS][116]
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-skl1/igt@gen9_exec_parse@allowed-single.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-skl1/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_rpm@system-suspend-modeset:
- shard-tglb: [INCOMPLETE][117] ([i915#2411] / [i915#456]) -> [PASS][118] +1 similar issue
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-tglb7/igt@i915_pm_rpm@system-suspend-modeset.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-tglb2/igt@i915_pm_rpm@system-suspend-modeset.html
* igt@i915_selftest@live@late_gt_pm:
- shard-skl: [INCOMPLETE][119] ([i915#198]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-skl8/igt@i915_selftest@live@late_gt_pm.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-skl6/igt@i915_selftest@live@late_gt_pm.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [INCOMPLETE][121] ([i915#155]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [FAIL][123] ([i915#2346]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [INCOMPLETE][125] ([i915#155] / [i915#180] / [i915#636]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-kbl3/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs:
- shard-iclb: [SKIP][127] ([i915#3701]) -> [PASS][128]
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-iclb1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-tglb: [INCOMPLETE][129] ([i915#1373] / [i915#2828]) -> [PASS][130]
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-tglb7/igt@kms_hdr@bpc-switch-suspend.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-tglb3/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-apl: [DMESG-WARN][131] ([i915#180]) -> [PASS][132]
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-apl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-apl8/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [SKIP][133] ([fdo#109441]) -> [PASS][134] +3 similar issues
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-iclb5/igt@kms_psr@psr2_cursor_render.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
* igt@perf@polling-parameterized:
- shard-skl: [FAIL][135] ([i915#1542]) -> [PASS][136]
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-skl6/igt@perf@polling-parameterized.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-skl7/igt@perf@polling-parameterized.html
- shard-tglb: [FAIL][137] ([i915#1542]) -> [PASS][138]
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-tglb5/igt@perf@polling-parameterized.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-tglb6/igt@perf@polling-parameterized.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][139] ([i915#1804] / [i915#2684]) -> [WARN][140] ([i915#2684])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-iclb3/igt@i915_pm_rc6_residency@rc6-idle.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5:
- shard-iclb: [SKIP][141] ([i915#2920]) -> [SKIP][142] ([i915#658]) +2 similar issues
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10683/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/shard-iclb1/igt@kms_psr2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21250/index.html
[-- Attachment #2: Type: text/html, Size: 33630 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH v2 1/5] drm/i915: Tweak the DP "max vswing reached?" condition
2021-10-04 17:05 ` [Intel-gfx] [PATCH v2 1/5] drm/i915: Tweak the DP "max vswing reached?" condition Ville Syrjala
@ 2021-10-06 15:44 ` Imre Deak
0 siblings, 0 replies; 21+ messages in thread
From: Imre Deak @ 2021-10-06 15:44 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Mon, Oct 04, 2021 at 08:05:31PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Currently we consider the max vswing reached when we transmit a
> the max voltage level, but we don't consider pre-emphasis at all.
> This kinda matches older DP specs that only had some vague text
> about transmitting the maximum voltage swing. Latest versions
> now say something vague about consider the sum of the vswing
> and pre-emphasis fields in the ADJUST_REQUEST_LANE registers.
> Very vague, and super confusing especially the fact that it
> talks about transmitted voltgage swing in the same sentence
> as it say to look at the requested values.
>
> Also glanced at the link CTS spec, and that one seems to have
> tests that assume contradicting behaviour. Some say to consider
> just the vswing level we transmit, others say to check for
> sum of transmitted vswing+preemph being 3.
>
> So let's try to take some kind of sane middle ground here.
> I think what could make sense is only consider max vswing
> reached if MAX_SWING_REACHED==1 _and_ vswing+preemph==3.
> That will allow things to go all the way up to vswing 3 +
> pre-emph 0 or vswing 2 + pre-emph 1, depending on what
> the maximum supported vswing is. Only considering the sum
> of vswing+pre-emph doesn't make much sense to me since
> we could terminate too early if the sink requests eg.
> vswing 0 + pre-emph 3. And if we'd stick to the current
> code we could terminate too early of the sink asks for
> vswing 2 + pre-emph 0 when vswing level 3 is not supported.
>
> Side note: I don't really understand why any of this stuff is
> "specified" at all. There is already a limit of 5 attempts at
> the same vswing+pre-emph level, and a total limit of 10
> attempts. So might as well stick to the same max 5 attempts
> across the board IMO.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> .../drm/i915/display/intel_dp_link_training.c | 22 ++++++++++++++++---
> 1 file changed, 19 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index c052ce14894d..a45569b8c959 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -492,11 +492,27 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
> {
> int lane;
>
> - for (lane = 0; lane < crtc_state->lane_count; lane++)
> - if ((intel_dp->train_set[lane] &
> - DP_TRAIN_MAX_SWING_REACHED) == 0)
> + /*
> + * FIXME: The DP spec is very confusing here, also the Link CTS
> + * spec seems to have self contradicting tests around this area.
> + *
> + * In lieu of better ideas let's just stop when we've reached the
> + * max supported vswing with its max pre-emphasis, which is either
> + * 2+1 or 3+0 depending on whether vswing level 3 is supported or not.
> + */
> + for (lane = 0; lane < crtc_state->lane_count; lane++) {
> + u8 v = (intel_dp->train_set[lane] & DP_TRAIN_VOLTAGE_SWING_MASK) >>
> + DP_TRAIN_VOLTAGE_SWING_SHIFT;
> + u8 p = (intel_dp->train_set[lane] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
> + DP_TRAIN_PRE_EMPHASIS_SHIFT;
> +
> + if ((intel_dp->train_set[lane] & DP_TRAIN_MAX_SWING_REACHED) == 0)
> return false;
>
> + if (v + p != 3)
> + return false;
> + }
> +
> return true;
> }
>
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/5] drm/i915: Show LTTPR in the TPS debug print
2021-10-04 17:05 ` [Intel-gfx] [PATCH v2 2/5] drm/i915: Show LTTPR in the TPS debug print Ville Syrjala
@ 2021-10-06 15:47 ` Imre Deak
0 siblings, 0 replies; 21+ messages in thread
From: Imre Deak @ 2021-10-06 15:47 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Mon, Oct 04, 2021 at 08:05:32PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Indicate which LTTPR we're currently attempting to train when
> we print which training pattern we're using.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/g4x_dp.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dp_link_training.c | 11 +++++++----
> drivers/gpu/drm/i915/display/intel_dp_link_training.h | 1 +
> 3 files changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
> index 60ae2ba52006..85a09c3e09e8 100644
> --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> @@ -637,7 +637,7 @@ static void intel_dp_enable_port(struct intel_dp *intel_dp,
> /* enable with pattern 1 (as per spec) */
>
> intel_dp_program_link_training_pattern(intel_dp, crtc_state,
> - DP_TRAINING_PATTERN_1);
> + DP_PHY_DPRX, DP_TRAINING_PATTERN_1);
>
> /*
> * Magic for VLV/CHV. We _must_ first set up the register
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index a45569b8c959..6bab097cafd2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -376,7 +376,7 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
> int len;
>
> intel_dp_program_link_training_pattern(intel_dp, crtc_state,
> - dp_train_pat);
> + dp_phy, dp_train_pat);
>
> buf[0] = dp_train_pat;
> /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
> @@ -404,17 +404,20 @@ static char dp_training_pattern_name(u8 train_pat)
> void
> intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state,
> + enum drm_dp_phy dp_phy,
> u8 dp_train_pat)
> {
> struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat);
> + char phy_name[10];
>
> if (train_pat != DP_TRAINING_PATTERN_DISABLE)
> drm_dbg_kms(&dev_priv->drm,
> - "[ENCODER:%d:%s] Using DP training pattern TPS%c\n",
> + "[ENCODER:%d:%s] Using DP training pattern TPS%c, at %s\n",
> encoder->base.base.id, encoder->base.name,
> - dp_training_pattern_name(train_pat));
> + dp_training_pattern_name(train_pat),
> + intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
>
> intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
> }
> @@ -855,7 +858,7 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp,
> intel_dp->link_trained = true;
>
> intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
> - intel_dp_program_link_training_pattern(intel_dp, crtc_state,
> + intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX,
> DP_TRAINING_PATTERN_DISABLE);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> index 9d24d594368c..6a3a7b37349a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> @@ -19,6 +19,7 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
> const u8 link_status[DP_LINK_STATUS_SIZE]);
> void intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state,
> + enum drm_dp_phy dp_phy,
> u8 dp_train_pat);
> void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state,
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH v2 3/5] drm/i915: Print the DP vswing adjustment request
2021-10-04 17:05 ` [Intel-gfx] [PATCH v2 3/5] drm/i915: Print the DP vswing adjustment request Ville Syrjala
@ 2021-10-06 15:50 ` Imre Deak
0 siblings, 0 replies; 21+ messages in thread
From: Imre Deak @ 2021-10-06 15:50 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Mon, Oct 04, 2021 at 08:05:33PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Print out each DP vswing adjustment request we got from the RX.
> Could help in diagnosing what's going on during link training.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> .../drm/i915/display/intel_dp_link_training.c | 27 +++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 6bab097cafd2..5657be1461ec 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -343,14 +343,41 @@ static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp,
> return v | p;
> }
>
> +#define TRAIN_REQ_FMT "%d/%d/%d/%d"
> +#define _TRAIN_REQ_VSWING_ARGS(link_status, lane) \
> + (drm_dp_get_adjust_request_voltage((link_status), (lane)) >> DP_TRAIN_VOLTAGE_SWING_SHIFT)
> +#define TRAIN_REQ_VSWING_ARGS(link_status) \
> + _TRAIN_REQ_VSWING_ARGS(link_status, 0), \
> + _TRAIN_REQ_VSWING_ARGS(link_status, 1), \
> + _TRAIN_REQ_VSWING_ARGS(link_status, 2), \
> + _TRAIN_REQ_VSWING_ARGS(link_status, 3)
> +#define _TRAIN_REQ_PREEMPH_ARGS(link_status, lane) \
> + (drm_dp_get_adjust_request_pre_emphasis((link_status), (lane)) >> DP_TRAIN_PRE_EMPHASIS_SHIFT)
> +#define TRAIN_REQ_PREEMPH_ARGS(link_status) \
> + _TRAIN_REQ_PREEMPH_ARGS(link_status, 0), \
> + _TRAIN_REQ_PREEMPH_ARGS(link_status, 1), \
> + _TRAIN_REQ_PREEMPH_ARGS(link_status, 2), \
> + _TRAIN_REQ_PREEMPH_ARGS(link_status, 3)
> +
> void
> intel_dp_get_adjust_train(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state,
> enum drm_dp_phy dp_phy,
> const u8 link_status[DP_LINK_STATUS_SIZE])
> {
> + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> + char phy_name[10];
> int lane;
>
> + drm_dbg_kms(encoder->base.dev, "[ENCODER:%d:%s] lanes: %d, "
> + "vswing request: " TRAIN_REQ_FMT ", "
> + "pre-emphasis request: " TRAIN_REQ_FMT ", at %s\n",
> + encoder->base.base.id, encoder->base.name,
> + crtc_state->lane_count,
> + TRAIN_REQ_VSWING_ARGS(link_status),
> + TRAIN_REQ_PREEMPH_ARGS(link_status),
> + intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
> +
> for (lane = 0; lane < 4; lane++)
> intel_dp->train_set[lane] =
> intel_dp_get_lane_adjust_train(intel_dp, crtc_state,
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/5] drm/i915: Pimp link training debug prints
2021-10-04 17:05 ` [Intel-gfx] [PATCH v2 4/5] drm/i915: Pimp link training debug prints Ville Syrjala
@ 2021-10-06 16:09 ` Imre Deak
2021-10-06 16:48 ` Ville Syrjälä
0 siblings, 1 reply; 21+ messages in thread
From: Imre Deak @ 2021-10-06 16:09 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Mon, Oct 04, 2021 at 08:05:34PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Unify all debug prints during link training to include information
> on both the encoder and the LTTPR. We unify the format to something
> like "[ENCODER:1:FOO][LTTPR 1] Something something". Though not
> sure if those brackets around the dp_phy just make it look like
> line noise? I'll accept suggestions on better formatting.
>
> I'm slightly on the fence about also including the connector,
> but technically only the DPRX is the SST connector (ie.
> intel_dp->attached_connector). I suppose you could think of it
> as the branch device/whatever in the topology, and we're training
> the link leading to it. So that could argue for its inclusion.
> But it's all getting a bit long alrady, so not going to do it
> I think.
Imo including the connector info eventually would be good to be able to
match these lines with those only showing the connector, or connectors
in i915_display_info etc.
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> .../drm/i915/display/intel_dp_link_training.c | 167 +++++++++++-------
> 1 file changed, 106 insertions(+), 61 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 5657be1461ec..18f4b469766e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -25,15 +25,6 @@
> #include "intel_dp.h"
> #include "intel_dp_link_training.h"
>
> -static void
> -intel_dp_dump_link_status(struct drm_device *drm,
> - const u8 link_status[DP_LINK_STATUS_SIZE])
> -{
> - drm_dbg_kms(drm,
> - "ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x\n",
> - link_status[0], link_status[1], link_status[2],
> - link_status[3], link_status[4], link_status[5]);
> -}
>
> static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp)
> {
> @@ -66,6 +57,7 @@ static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp,
> static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
> enum drm_dp_phy dp_phy)
> {
> + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
> char phy_name[10];
>
> @@ -73,21 +65,22 @@ static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
>
> if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dp_phy, phy_caps) < 0) {
> drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
> - "failed to read the PHY caps for %s\n",
> - phy_name);
> + "[ENCODER:%d:%s][%s] failed to read the PHY caps\n",
> + encoder->base.base.id, encoder->base.name, phy_name);
> return;
> }
>
> drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
> - "%s PHY capabilities: %*ph\n",
> - phy_name,
> + "[ENCODER:%d:%s][%s] PHY capabilities: %*ph\n",
> + encoder->base.base.id, encoder->base.name, phy_name,
> (int)sizeof(intel_dp->lttpr_phy_caps[0]),
> phy_caps);
> }
>
> static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp)
> {
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>
> if (intel_dp_is_edp(intel_dp))
> return false;
> @@ -104,7 +97,8 @@ static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp)
> goto reset_caps;
>
> drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
> - "LTTPR common capabilities: %*ph\n",
> + "[ENCODER:%d:%s] LTTPR common capabilities: %*ph\n",
> + encoder->base.base.id, encoder->base.name,
> (int)sizeof(intel_dp->lttpr_common_caps),
> intel_dp->lttpr_common_caps);
>
> @@ -130,6 +124,8 @@ intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable)
>
> static int intel_dp_init_lttpr(struct intel_dp *intel_dp)
> {
> + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> int lttpr_count;
> int i;
>
> @@ -161,8 +157,9 @@ static int intel_dp_init_lttpr(struct intel_dp *intel_dp)
> return 0;
>
> if (!intel_dp_set_lttpr_transparent_mode(intel_dp, false)) {
> - drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
> - "Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n");
> + drm_dbg_kms(&i915->drm,
> + "[ENCODER:%d:%s] Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n",
> + encoder->base.base.id, encoder->base.name);
>
> intel_dp_set_lttpr_transparent_mode(intel_dp, true);
> intel_dp_reset_lttpr_count(intel_dp);
> @@ -366,17 +363,18 @@ intel_dp_get_adjust_train(struct intel_dp *intel_dp,
> const u8 link_status[DP_LINK_STATUS_SIZE])
> {
> struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> char phy_name[10];
> int lane;
>
> - drm_dbg_kms(encoder->base.dev, "[ENCODER:%d:%s] lanes: %d, "
> + drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s][%s] lanes: %d, "
> "vswing request: " TRAIN_REQ_FMT ", "
> - "pre-emphasis request: " TRAIN_REQ_FMT ", at %s\n",
> + "pre-emphasis request: " TRAIN_REQ_FMT "\n",
> encoder->base.base.id, encoder->base.name,
> + intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)),
> crtc_state->lane_count,
> TRAIN_REQ_VSWING_ARGS(link_status),
> - TRAIN_REQ_PREEMPH_ARGS(link_status),
> - intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
> + TRAIN_REQ_PREEMPH_ARGS(link_status));
>
> for (lane = 0; lane < 4; lane++)
> intel_dp->train_set[lane] =
> @@ -435,16 +433,16 @@ intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
> u8 dp_train_pat)
> {
> struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat);
> char phy_name[10];
>
> if (train_pat != DP_TRAINING_PATTERN_DISABLE)
> - drm_dbg_kms(&dev_priv->drm,
> - "[ENCODER:%d:%s] Using DP training pattern TPS%c, at %s\n",
> + drm_dbg_kms(&i915->drm,
> + "[ENCODER:%d:%s][%s] Using DP training pattern TPS%c\n",
> encoder->base.base.id, encoder->base.name,
> - dp_training_pattern_name(train_pat),
> - intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
> + intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)),
> + dp_training_pattern_name(train_pat));
>
> intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
> }
> @@ -472,17 +470,17 @@ void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
> enum drm_dp_phy dp_phy)
> {
> struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> char phy_name[10];
>
> - drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] lanes: %d, "
> + drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s][%s] lanes: %d, "
> "vswing levels: " TRAIN_SET_FMT ", "
> - "pre-emphasis levels: " TRAIN_SET_FMT ", at %s\n",
> + "pre-emphasis levels: " TRAIN_SET_FMT "\n",
> encoder->base.base.id, encoder->base.name,
> + intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)),
> crtc_state->lane_count,
> TRAIN_SET_VSWING_ARGS(intel_dp->train_set),
> - TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set),
> - intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
> + TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set));
>
> if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
> encoder->set_signal_levels(encoder, crtc_state);
> @@ -554,7 +552,8 @@ static bool
> intel_dp_prepare_link_train(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> u8 link_config[2];
> u8 link_bw, rate_select;
>
> @@ -566,10 +565,12 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
>
> if (link_bw)
> drm_dbg_kms(&i915->drm,
> - "Using LINK_BW_SET value %02x\n", link_bw);
> + "[ENCODER:%d:%s] Using LINK_BW_SET value %02x\n",
> + encoder->base.base.id, encoder->base.name, link_bw);
> else
> drm_dbg_kms(&i915->drm,
> - "Using LINK_RATE_SET value %02x\n", rate_select);
> + "[ENCODER:%d:%s] Using LINK_RATE_SET value %02x\n",
> + encoder->base.base.id, encoder->base.name, rate_select);
>
> /* Write the link configuration data */
> link_config[0] = link_bw;
> @@ -619,6 +620,22 @@ static bool intel_dp_adjust_request_changed(int lane_count,
> return false;
> }
>
> +static void
> +intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy,
> + const u8 link_status[DP_LINK_STATUS_SIZE])
> +{
> + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + char phy_name[10];
> +
> + drm_dbg_kms(&i915->drm,
> + "[ENCODER:%d:%s][%s] ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x\n",
> + encoder->base.base.id, encoder->base.name,
> + intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)),
> + link_status[0], link_status[1], link_status[2],
> + link_status[3], link_status[4], link_status[5]);
> +}
> +
> /*
> * Perform the link training clock recovery phase on the given DP PHY using
> * training pattern 1.
> @@ -628,16 +645,21 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state,
> enum drm_dp_phy dp_phy)
> {
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> u8 old_link_status[DP_LINK_STATUS_SIZE] = {};
> int voltage_tries, cr_tries, max_cr_tries;
> bool max_vswing_reached = false;
> + char phy_name[10];
> +
> + intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name));
>
> /* clock recovery */
> if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy,
> DP_TRAINING_PATTERN_1 |
> DP_LINK_SCRAMBLING_DISABLE)) {
> - drm_err(&i915->drm, "failed to enable link training\n");
> + drm_err(&i915->drm, "[ENCODER:%d:%s][%s] Failed to enable link training\n",
> + encoder->base.base.id, encoder->base.name, phy_name);
> return false;
> }
>
> @@ -662,23 +684,29 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
>
> if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
> link_status) < 0) {
> - drm_err(&i915->drm, "failed to get link status\n");
> + drm_err(&i915->drm, "[ENCODER:%d:%s][%s] Failed to get link status\n",
> + encoder->base.base.id, encoder->base.name, phy_name);
> return false;
> }
>
> if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) {
> - drm_dbg_kms(&i915->drm, "clock recovery OK\n");
> + drm_dbg_kms(&i915->drm,
> + "[ENCODER:%d:%s][%s] Clock recovery OK\n",
> + encoder->base.base.id, encoder->base.name, phy_name);
> return true;
> }
>
> if (voltage_tries == 5) {
> drm_dbg_kms(&i915->drm,
> - "Same voltage tried 5 times\n");
> + "[ENCODER:%d:%s][%s] Same voltage tried 5 times\n",
> + encoder->base.base.id, encoder->base.name, phy_name);
> return false;
> }
>
> if (max_vswing_reached) {
> - drm_dbg_kms(&i915->drm, "Max Voltage Swing reached\n");
> + drm_dbg_kms(&i915->drm,
> + "[ENCODER:%d:%s][%s] Max Voltage Swing reached\n",
> + encoder->base.base.id, encoder->base.name, phy_name);
> return false;
> }
>
> @@ -687,7 +715,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
> link_status);
> if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
> drm_err(&i915->drm,
> - "failed to update link training\n");
> + "[ENCODER:%d:%s][%s] Failed to update link training\n",
> + encoder->base.base.id, encoder->base.name, phy_name);
> return false;
> }
>
> @@ -701,10 +730,12 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
>
> if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state))
> max_vswing_reached = true;
> -
> }
> +
> drm_err(&i915->drm,
> - "Failed clock recovery %d times, giving up!\n", max_cr_tries);
> + "[ENCODER:%d:%s][%s] Failed clock recovery %d times, giving up!\n",
> + encoder->base.base.id, encoder->base.name, phy_name, max_cr_tries);
> +
> return false;
> }
>
> @@ -788,11 +819,15 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state,
> enum drm_dp_phy dp_phy)
> {
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> int tries;
> u32 training_pattern;
> u8 link_status[DP_LINK_STATUS_SIZE];
> bool channel_eq = false;
> + char phy_name[10];
> +
> + intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name));
>
> training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy);
> /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
> @@ -802,7 +837,10 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
> /* channel equalization */
> if (!intel_dp_set_link_train(intel_dp, crtc_state, dp_phy,
> training_pattern)) {
> - drm_err(&i915->drm, "failed to start channel equalization\n");
> + drm_err(&i915->drm,
> + "[ENCODER:%d:%s][%s] Failed to start channel equalization\n",
> + encoder->base.base.id, encoder->base.name,
> + phy_name);
> return false;
> }
>
> @@ -812,25 +850,28 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
> if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
> link_status) < 0) {
> drm_err(&i915->drm,
> - "failed to get link status\n");
> + "[ENCODER:%d:%s][%s] Failed to get link status\n",
> + encoder->base.base.id, encoder->base.name, phy_name);
> break;
> }
>
> /* Make sure clock is still ok */
> if (!drm_dp_clock_recovery_ok(link_status,
> crtc_state->lane_count)) {
> - intel_dp_dump_link_status(&i915->drm, link_status);
> + intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
> drm_dbg_kms(&i915->drm,
> - "Clock recovery check failed, cannot "
> - "continue channel equalization\n");
> + "[ENCODER:%d:%s][%s] Clock recovery check failed, cannot "
> + "continue channel equalization\n",
> + encoder->base.base.id, encoder->base.name, phy_name);
> break;
> }
>
> if (drm_dp_channel_eq_ok(link_status,
> crtc_state->lane_count)) {
> channel_eq = true;
> - drm_dbg_kms(&i915->drm, "Channel EQ done. DP Training "
> - "successful\n");
> + drm_dbg_kms(&i915->drm,
> + "[ENCODER:%d:%s][%s] Channel EQ done. DP Training successful\n",
> + encoder->base.base.id, encoder->base.name, phy_name);
> break;
> }
>
> @@ -839,16 +880,18 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
> link_status);
> if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
> drm_err(&i915->drm,
> - "failed to update link training\n");
> + "[ENCODER:%d:%s][%s] Failed to update link training\n",
> + encoder->base.base.id, encoder->base.name, phy_name);
> break;
> }
> }
>
> /* Try 5 times, else fail and try at lower BW */
> if (tries == 5) {
> - intel_dp_dump_link_status(&i915->drm, link_status);
> + intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
> drm_dbg_kms(&i915->drm,
> - "Channel equalization failed 5 times\n");
> + "[ENCODER:%d:%s][%s] Channel equalization failed 5 times\n",
> + encoder->base.base.id, encoder->base.name, phy_name);
> }
>
> return channel_eq;
> @@ -894,7 +937,7 @@ intel_dp_link_train_phy(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state,
> enum drm_dp_phy dp_phy)
> {
> - struct intel_connector *intel_connector = intel_dp->attached_connector;
> + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> char phy_name[10];
> bool ret = false;
>
> @@ -908,12 +951,11 @@ intel_dp_link_train_phy(struct intel_dp *intel_dp,
>
> out:
> drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
> - "[CONNECTOR:%d:%s] Link Training %s at link rate = %d, lane count = %d, at %s\n",
> - intel_connector->base.base.id,
> - intel_connector->base.name,
> + "[ENCODER:%d:%s][%s] Link Training %s at link rate = %d, lane count = %d\n",
> + encoder->base.base.id, encoder->base.name,
> + intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)),
> ret ? "passed" : "failed",
> - crtc_state->port_clock, crtc_state->lane_count,
> - intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
> + crtc_state->port_clock, crtc_state->lane_count);
>
> return ret;
> }
> @@ -922,10 +964,13 @@ static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state)
> {
> struct intel_connector *intel_connector = intel_dp->attached_connector;
> + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>
> if (intel_dp->hobl_active) {
> drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
> - "Link Training failed with HOBL active, not enabling it from now on");
> + "[ENCODER:%d:%s] Link Training failed with HOBL active, "
> + "not enabling it from now on",
> + encoder->base.base.id, encoder->base.name);
> intel_dp->hobl_failed = true;
> } else if (intel_dp_get_link_train_fallback_values(intel_dp,
> crtc_state->port_clock,
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH v2 5/5] drm/i915: Call intel_dp_dump_link_status() for CR failures
2021-10-04 17:05 ` [Intel-gfx] [PATCH v2 5/5] drm/i915: Call intel_dp_dump_link_status() for CR failures Ville Syrjala
@ 2021-10-06 16:12 ` Imre Deak
0 siblings, 0 replies; 21+ messages in thread
From: Imre Deak @ 2021-10-06 16:12 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Mon, Oct 04, 2021 at 08:05:35PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> I suppose intel_dp_dump_link_status() might be useful for diagnosing
> link training failures. Hoever we only call from the channel EQ phase
> currently. Let's call it from the CR phase as well.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp_link_training.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 18f4b469766e..c92044710012 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -649,6 +649,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> u8 old_link_status[DP_LINK_STATUS_SIZE] = {};
> int voltage_tries, cr_tries, max_cr_tries;
> + u8 link_status[DP_LINK_STATUS_SIZE];
> bool max_vswing_reached = false;
> char phy_name[10];
>
> @@ -678,8 +679,6 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
>
> voltage_tries = 1;
> for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
> - u8 link_status[DP_LINK_STATUS_SIZE];
> -
> intel_dp_link_training_clock_recovery_delay(intel_dp, dp_phy);
>
> if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
> @@ -697,6 +696,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
> }
>
> if (voltage_tries == 5) {
> + intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
> drm_dbg_kms(&i915->drm,
> "[ENCODER:%d:%s][%s] Same voltage tried 5 times\n",
> encoder->base.base.id, encoder->base.name, phy_name);
> @@ -704,6 +704,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
> }
>
> if (max_vswing_reached) {
> + intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
> drm_dbg_kms(&i915->drm,
> "[ENCODER:%d:%s][%s] Max Voltage Swing reached\n",
> encoder->base.base.id, encoder->base.name, phy_name);
> @@ -732,6 +733,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
> max_vswing_reached = true;
> }
>
> + intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
> drm_err(&i915->drm,
> "[ENCODER:%d:%s][%s] Failed clock recovery %d times, giving up!\n",
> encoder->base.base.id, encoder->base.name, phy_name, max_cr_tries);
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/5] drm/i915: Pimp link training debug prints
2021-10-06 16:09 ` Imre Deak
@ 2021-10-06 16:48 ` Ville Syrjälä
2021-10-06 19:28 ` Ville Syrjälä
0 siblings, 1 reply; 21+ messages in thread
From: Ville Syrjälä @ 2021-10-06 16:48 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Wed, Oct 06, 2021 at 07:09:02PM +0300, Imre Deak wrote:
> On Mon, Oct 04, 2021 at 08:05:34PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Unify all debug prints during link training to include information
> > on both the encoder and the LTTPR. We unify the format to something
> > like "[ENCODER:1:FOO][LTTPR 1] Something something". Though not
> > sure if those brackets around the dp_phy just make it look like
> > line noise? I'll accept suggestions on better formatting.
> >
> > I'm slightly on the fence about also including the connector,
> > but technically only the DPRX is the SST connector (ie.
> > intel_dp->attached_connector). I suppose you could think of it
> > as the branch device/whatever in the topology, and we're training
> > the link leading to it. So that could argue for its inclusion.
> > But it's all getting a bit long alrady, so not going to do it
> > I think.
>
> Imo including the connector info eventually would be good to be able to
> match these lines with those only showing the connector, or connectors
> in i915_display_info etc.
You're probably right. I was just looking at a dmesg wondering which
connector it's training there...
Although with MST it of course doesn't match up with anything
that the user thinks as a connected connector. So a bit annoying.
And using a single MST connector wouldn't really lead to a
coherent debug message either since there could be many MST
connectors active on the same link :/
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/5] drm/i915: Pimp link training debug prints
2021-10-06 16:48 ` Ville Syrjälä
@ 2021-10-06 19:28 ` Ville Syrjälä
0 siblings, 0 replies; 21+ messages in thread
From: Ville Syrjälä @ 2021-10-06 19:28 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Wed, Oct 06, 2021 at 07:48:18PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 06, 2021 at 07:09:02PM +0300, Imre Deak wrote:
> > On Mon, Oct 04, 2021 at 08:05:34PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Unify all debug prints during link training to include information
> > > on both the encoder and the LTTPR. We unify the format to something
> > > like "[ENCODER:1:FOO][LTTPR 1] Something something". Though not
> > > sure if those brackets around the dp_phy just make it look like
> > > line noise? I'll accept suggestions on better formatting.
> > >
> > > I'm slightly on the fence about also including the connector,
> > > but technically only the DPRX is the SST connector (ie.
> > > intel_dp->attached_connector). I suppose you could think of it
> > > as the branch device/whatever in the topology, and we're training
> > > the link leading to it. So that could argue for its inclusion.
> > > But it's all getting a bit long alrady, so not going to do it
> > > I think.
> >
> > Imo including the connector info eventually would be good to be able to
> > match these lines with those only showing the connector, or connectors
> > in i915_display_info etc.
>
> You're probably right. I was just looking at a dmesg wondering which
> connector it's training there...
>
> Although with MST it of course doesn't match up with anything
> that the user thinks as a connected connector. So a bit annoying.
> And using a single MST connector wouldn't really lead to a
> coherent debug message either since there could be many MST
> connectors active on the same link :/
As a compromise I kept the SST connector name in the final passed/failed
debug print. That was the only place where we printed it previously as
well. Not ideal perhaps but at least it's something.
Series pushed. Thanks for the review.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2021-10-06 19:29 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-04 17:05 [Intel-gfx] [PATCH v2 0/5] drm/i915: Improve DP link training further Ville Syrjala
2021-10-04 17:05 ` [Intel-gfx] [PATCH v2 1/5] drm/i915: Tweak the DP "max vswing reached?" condition Ville Syrjala
2021-10-06 15:44 ` Imre Deak
2021-10-04 17:05 ` [Intel-gfx] [PATCH v2 2/5] drm/i915: Show LTTPR in the TPS debug print Ville Syrjala
2021-10-06 15:47 ` Imre Deak
2021-10-04 17:05 ` [Intel-gfx] [PATCH v2 3/5] drm/i915: Print the DP vswing adjustment request Ville Syrjala
2021-10-06 15:50 ` Imre Deak
2021-10-04 17:05 ` [Intel-gfx] [PATCH v2 4/5] drm/i915: Pimp link training debug prints Ville Syrjala
2021-10-06 16:09 ` Imre Deak
2021-10-06 16:48 ` Ville Syrjälä
2021-10-06 19:28 ` Ville Syrjälä
2021-10-04 17:05 ` [Intel-gfx] [PATCH v2 5/5] drm/i915: Call intel_dp_dump_link_status() for CR failures Ville Syrjala
2021-10-06 16:12 ` Imre Deak
2021-10-04 18:55 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Improve DP link training further (rev2) Patchwork
2021-10-04 23:46 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Improve DP link training further (rev3) Patchwork
2021-10-05 12:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve DP link training further (rev4) Patchwork
2021-10-05 12:49 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-10-05 13:42 ` Ville Syrjälä
2021-10-05 14:02 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve DP link training further (rev5) Patchwork
2021-10-05 14:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-05 18:25 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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