From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-tegra@vger.kernel.org
Subject: [PATCH v5 3/9] dt-bindings: memory: lpddr2: Add revision-id properties
Date: Thu, 7 Oct 2021 01:46:53 +0300 [thread overview]
Message-ID: <20211006224659.21434-4-digetx@gmail.com> (raw)
In-Reply-To: <20211006224659.21434-1-digetx@gmail.com>
Add optional revision-id standard LPDDR2 properties which will help to
identify memory chip.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
.../memory-controllers/ddr/jedec,lpddr2.yaml | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml
index f931fe910ce5..fe573750577e 100644
--- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml
@@ -24,6 +24,18 @@ properties:
- enum:
- jedec,lpddr2-nvm
+ revision-id1:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 255
+ description: |
+ Revision 1 value of SDRAM chip. Obtained from device datasheet.
+
+ revision-id2:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 255
+ description: |
+ Revision 2 value of SDRAM chip. Obtained from device datasheet.
+
density:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
@@ -151,6 +163,8 @@ examples:
compatible = "elpida,ECB240ABACN", "jedec,lpddr2-s4";
density = <2048>;
io-width = <32>;
+ revision-id1 = <1>;
+ revision-id2 = <0>;
tRPab-min-tck = <3>;
tRCD-min-tck = <3>;
--
2.32.0
next prev parent reply other threads:[~2021-10-06 22:49 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-06 22:46 [PATCH v5 0/9] tegra20-emc: Identify memory chip by LPDDR configuration Dmitry Osipenko
2021-10-06 22:46 ` [PATCH v5 1/9] dt-bindings: Relocate DDR bindings Dmitry Osipenko
2021-10-14 21:22 ` Rob Herring
2021-10-06 22:46 ` [PATCH v5 2/9] dt-bindings: memory: lpddr2: Convert to schema Dmitry Osipenko
2021-10-14 21:50 ` Rob Herring
2021-10-06 22:46 ` Dmitry Osipenko [this message]
2021-10-14 21:51 ` [PATCH v5 3/9] dt-bindings: memory: lpddr2: Add revision-id properties Rob Herring
2022-02-08 2:06 ` Julius Werner
2022-02-08 8:10 ` Krzysztof Kozlowski
2022-02-08 23:46 ` Julius Werner
2022-02-09 8:58 ` Krzysztof Kozlowski
2022-02-09 11:49 ` Dmitry Osipenko
2022-02-10 0:32 ` Julius Werner
2022-02-10 23:17 ` Dmitry Osipenko
2022-02-11 7:55 ` Krzysztof Kozlowski
2021-10-06 22:46 ` [PATCH v5 4/9] dt-bindings: memory: lpddr2: Document Elpida B8132B2PB-6D-F Dmitry Osipenko
2021-10-14 21:51 ` Rob Herring
2021-10-06 22:46 ` [PATCH v5 5/9] dt-bindings: Add vendor prefix for Elpida Memory Dmitry Osipenko
2021-10-14 21:51 ` Rob Herring
2021-10-06 22:46 ` [PATCH v5 6/9] ARM: dts: elpida_ecb240abacn: Change Elpida compatible Dmitry Osipenko
2021-10-06 22:46 ` [PATCH v5 7/9] dt-bindings: memory: tegra20: emc: Document new LPDDR2 sub-node Dmitry Osipenko
2021-10-14 21:52 ` Rob Herring
2021-10-06 22:46 ` [PATCH v5 8/9] memory: Add LPDDR2-info helpers Dmitry Osipenko
2021-10-06 22:46 ` [PATCH v5 9/9] memory: tegra20-emc: Support matching timings by LPDDR2 configuration Dmitry Osipenko
2021-10-15 7:20 ` [PATCH v5 0/9] tegra20-emc: Identify memory chip by LPDDR configuration Krzysztof Kozlowski
2021-10-18 18:10 ` Dmitry Osipenko
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