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From: akpm@linux-foundation.org
To: andreyknvl@gmail.com, aryabinin@virtuozzo.com,
	branislav.rankov@arm.com, catalin.marinas@arm.com,
	dvyukov@google.com, elver@google.com, eugenis@google.com,
	glider@google.com, lorenzo.pieralisi@arm.com,
	mm-commits@vger.kernel.org, suzuki.poulose@arm.com,
	vincenzo.frascino@arm.com, will@kernel.org
Subject: [alternative-merged] arm64-mte-bitfield-definitions-for-asymm-mte.patch removed from -mm tree
Date: Wed, 06 Oct 2021 18:14:15 -0700	[thread overview]
Message-ID: <20211007011415.-f8S5jUtY%akpm@linux-foundation.org> (raw)


The patch titled
     Subject: arm64: mte: bitfield definitions for Asymm MTE
has been removed from the -mm tree.  Its filename was
     arm64-mte-bitfield-definitions-for-asymm-mte.patch

This patch was dropped because an alternative patch was merged

------------------------------------------------------
From: Vincenzo Frascino <vincenzo.frascino@arm.com>
Subject: arm64: mte: bitfield definitions for Asymm MTE

Add Asymmetric Memory Tagging Extension bitfield definitions.

Link: https://lkml.kernel.org/r/20211004202253.27857-3-vincenzo.frascino@arm.com
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Alexander Potapenko <glider@google.com>
Cc: Andrey Konovalov <andreyknvl@gmail.com>
Cc: Andrey Ryabinin <aryabinin@virtuozzo.com>
Cc: Branislav Rankov <branislav.rankov@arm.com>
Cc: Dmitry Vyukov <dvyukov@google.com>
Cc: Evgenii Stepanov <eugenis@google.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Marco Elver <elver@google.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---

 arch/arm64/include/asm/sysreg.h |    3 +++
 1 file changed, 3 insertions(+)

--- a/arch/arm64/include/asm/sysreg.h~arm64-mte-bitfield-definitions-for-asymm-mte
+++ a/arch/arm64/include/asm/sysreg.h
@@ -621,6 +621,7 @@
 #define SCTLR_ELx_TCF_NONE	(UL(0x0) << SCTLR_ELx_TCF_SHIFT)
 #define SCTLR_ELx_TCF_SYNC	(UL(0x1) << SCTLR_ELx_TCF_SHIFT)
 #define SCTLR_ELx_TCF_ASYNC	(UL(0x2) << SCTLR_ELx_TCF_SHIFT)
+#define SCTLR_ELx_TCF_ASYMM	(UL(0x3) << SCTLR_ELx_TCF_SHIFT)
 #define SCTLR_ELx_TCF_MASK	(UL(0x3) << SCTLR_ELx_TCF_SHIFT)
 
 #define SCTLR_ELx_ENIA_SHIFT	31
@@ -666,6 +667,7 @@
 #define SCTLR_EL1_TCF0_NONE	(UL(0x0) << SCTLR_EL1_TCF0_SHIFT)
 #define SCTLR_EL1_TCF0_SYNC	(UL(0x1) << SCTLR_EL1_TCF0_SHIFT)
 #define SCTLR_EL1_TCF0_ASYNC	(UL(0x2) << SCTLR_EL1_TCF0_SHIFT)
+#define SCTLR_EL1_TCF0_ASYMM	(UL(0x3) << SCTLR_EL1_TCF0_SHIFT)
 #define SCTLR_EL1_TCF0_MASK	(UL(0x3) << SCTLR_EL1_TCF0_SHIFT)
 
 #define SCTLR_EL1_BT1		(BIT(36))
@@ -807,6 +809,7 @@
 #define ID_AA64PFR1_MTE_NI		0x0
 #define ID_AA64PFR1_MTE_EL0		0x1
 #define ID_AA64PFR1_MTE			0x2
+#define ID_AA64PFR1_MTE_ASYMM		0x3
 
 /* id_aa64zfr0 */
 #define ID_AA64ZFR0_F64MM_SHIFT		56
_

Patches currently in -mm which might be from vincenzo.frascino@arm.com are

arm64-mte-cpu-feature-detection-for-asymm-mte.patch
arm64-mte-add-asymmetric-mode-support.patch
kasan-extend-kasan-mode-kernel-parameter.patch


                 reply	other threads:[~2021-10-07  1:14 UTC|newest]

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