* [RFC PATCH 00/10] Macronix ECC engine
@ 2021-10-08 16:22 ` Miquel Raynal
0 siblings, 0 replies; 39+ messages in thread
From: Miquel Raynal @ 2021-10-08 16:22 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus, linux-mtd
Cc: Rob Herring, Mark Brown, Xiangsheng Hou, Boris Brezillon,
devicetree, linux-spi, linux-kernel, jaimeliao, juliensu,
Thomas Petazzoni, Miquel Raynal
Hello all,
This series is not 100% stable yet but I believe it should be
sent out in order to help other people trying to use the ECC framework
with a SPI controller. Basically, Macronix ECC engine can be used as an
external engine (takes the data, proceeds to the calculations, writes
back the ECC bytes) or as a pipelined engine doing on-the-fly
calculations (which is very common in the raw NAND world).
In the device tree, the ECC engine should be described as a separated DT
node. Then:
* external case: the flash node should provide a nand-ecc-engine
property pointing to the ECC engine node.
* pipelined case: the flash node should provide a nand-ecc-engine
property pointing to the SPI controller, itself with another
nand-ecc-engine property pointing at the ECC engine node.
I will resubmit this later when I will be done validating the hardware
and the driver.
Cheers,
Miquèl
Mason Yang (1):
mtd: spinand: macronix: Use random program load
Miquel Raynal (9):
mtd: spinand: Fix comment
dt-bindings: vendor-prefixes: Update Macronix prefix
dt-bindings: mtd: Describe Macronix NAND ECC engine
mtd: nand: ecc: Add infrastructure to support hardware engines
mtd: nand: mxic-ecc: Add Macronix external ECC engine support
mtd: nand: mxic-ecc: Support SPI pipelined mode
spi: mxic: Fix the transmit path
spi: mxic: Add support for direct mapping
spi: mxic: Add support for pipelined ECC operations
.../bindings/mtd/mxic,nand-ecc-engine.yaml | 78 ++
.../devicetree/bindings/vendor-prefixes.yaml | 3 +
drivers/mtd/nand/Kconfig | 6 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/core.c | 10 +-
drivers/mtd/nand/ecc-mxic.c | 797 ++++++++++++++++++
drivers/mtd/nand/ecc.c | 89 ++
drivers/mtd/nand/spi/core.c | 2 +-
drivers/mtd/nand/spi/macronix.c | 2 +-
drivers/spi/spi-mxic.c | 309 ++++++-
include/linux/mtd/nand-ecc-mxic.h | 36 +
include/linux/mtd/nand.h | 11 +
12 files changed, 1296 insertions(+), 48 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mtd/mxic,nand-ecc-engine.yaml
create mode 100644 drivers/mtd/nand/ecc-mxic.c
create mode 100644 include/linux/mtd/nand-ecc-mxic.h
--
2.27.0
^ permalink raw reply [flat|nested] 39+ messages in thread
* [RFC PATCH 00/10] Macronix ECC engine
@ 2021-10-08 16:22 ` Miquel Raynal
0 siblings, 0 replies; 39+ messages in thread
From: Miquel Raynal @ 2021-10-08 16:22 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus, linux-mtd
Cc: Rob Herring, Mark Brown, Xiangsheng Hou, Boris Brezillon,
devicetree, linux-spi, linux-kernel, jaimeliao, juliensu,
Thomas Petazzoni, Miquel Raynal
Hello all,
This series is not 100% stable yet but I believe it should be
sent out in order to help other people trying to use the ECC framework
with a SPI controller. Basically, Macronix ECC engine can be used as an
external engine (takes the data, proceeds to the calculations, writes
back the ECC bytes) or as a pipelined engine doing on-the-fly
calculations (which is very common in the raw NAND world).
In the device tree, the ECC engine should be described as a separated DT
node. Then:
* external case: the flash node should provide a nand-ecc-engine
property pointing to the ECC engine node.
* pipelined case: the flash node should provide a nand-ecc-engine
property pointing to the SPI controller, itself with another
nand-ecc-engine property pointing at the ECC engine node.
I will resubmit this later when I will be done validating the hardware
and the driver.
Cheers,
Miquèl
Mason Yang (1):
mtd: spinand: macronix: Use random program load
Miquel Raynal (9):
mtd: spinand: Fix comment
dt-bindings: vendor-prefixes: Update Macronix prefix
dt-bindings: mtd: Describe Macronix NAND ECC engine
mtd: nand: ecc: Add infrastructure to support hardware engines
mtd: nand: mxic-ecc: Add Macronix external ECC engine support
mtd: nand: mxic-ecc: Support SPI pipelined mode
spi: mxic: Fix the transmit path
spi: mxic: Add support for direct mapping
spi: mxic: Add support for pipelined ECC operations
.../bindings/mtd/mxic,nand-ecc-engine.yaml | 78 ++
.../devicetree/bindings/vendor-prefixes.yaml | 3 +
drivers/mtd/nand/Kconfig | 6 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/core.c | 10 +-
drivers/mtd/nand/ecc-mxic.c | 797 ++++++++++++++++++
drivers/mtd/nand/ecc.c | 89 ++
drivers/mtd/nand/spi/core.c | 2 +-
drivers/mtd/nand/spi/macronix.c | 2 +-
drivers/spi/spi-mxic.c | 309 ++++++-
include/linux/mtd/nand-ecc-mxic.h | 36 +
include/linux/mtd/nand.h | 11 +
12 files changed, 1296 insertions(+), 48 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mtd/mxic,nand-ecc-engine.yaml
create mode 100644 drivers/mtd/nand/ecc-mxic.c
create mode 100644 include/linux/mtd/nand-ecc-mxic.h
--
2.27.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 39+ messages in thread
* [RFC PATCH 01/10] mtd: spinand: Fix comment
2021-10-08 16:22 ` Miquel Raynal
@ 2021-10-08 16:22 ` Miquel Raynal
-1 siblings, 0 replies; 39+ messages in thread
From: Miquel Raynal @ 2021-10-08 16:22 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus, linux-mtd
Cc: Rob Herring, Mark Brown, Xiangsheng Hou, Boris Brezillon,
devicetree, linux-spi, linux-kernel, jaimeliao, juliensu,
Thomas Petazzoni, Miquel Raynal
This is a copy paste error, checking the ECC status finishes a page read
here, not a page write.
Fixes: 945845b54c9c ("mtd: spinand: Instantiate a SPI-NAND on-die ECC engine")
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/nand/spi/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index dd903d61c7c0..9655b3ef7cc2 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -307,7 +307,7 @@ static int spinand_ondie_ecc_finish_io_req(struct nand_device *nand,
if (req->type == NAND_PAGE_WRITE)
return 0;
- /* Finish a page write: check the status, report errors/bitflips */
+ /* Finish a page read: check the status, report errors/bitflips */
ret = spinand_check_ecc_status(spinand, engine_conf->status);
if (ret == -EBADMSG)
mtd->ecc_stats.failed++;
--
2.27.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [RFC PATCH 01/10] mtd: spinand: Fix comment
@ 2021-10-08 16:22 ` Miquel Raynal
0 siblings, 0 replies; 39+ messages in thread
From: Miquel Raynal @ 2021-10-08 16:22 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus, linux-mtd
Cc: Rob Herring, Mark Brown, Xiangsheng Hou, Boris Brezillon,
devicetree, linux-spi, linux-kernel, jaimeliao, juliensu,
Thomas Petazzoni, Miquel Raynal
This is a copy paste error, checking the ECC status finishes a page read
here, not a page write.
Fixes: 945845b54c9c ("mtd: spinand: Instantiate a SPI-NAND on-die ECC engine")
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/nand/spi/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index dd903d61c7c0..9655b3ef7cc2 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -307,7 +307,7 @@ static int spinand_ondie_ecc_finish_io_req(struct nand_device *nand,
if (req->type == NAND_PAGE_WRITE)
return 0;
- /* Finish a page write: check the status, report errors/bitflips */
+ /* Finish a page read: check the status, report errors/bitflips */
ret = spinand_check_ecc_status(spinand, engine_conf->status);
if (ret == -EBADMSG)
mtd->ecc_stats.failed++;
--
2.27.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [RFC PATCH 02/10] mtd: spinand: macronix: Use random program load
2021-10-08 16:22 ` Miquel Raynal
@ 2021-10-08 16:22 ` Miquel Raynal
-1 siblings, 0 replies; 39+ messages in thread
From: Miquel Raynal @ 2021-10-08 16:22 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus, linux-mtd
Cc: Rob Herring, Mark Brown, Xiangsheng Hou, Boris Brezillon,
devicetree, linux-spi, linux-kernel, jaimeliao, juliensu,
Thomas Petazzoni, Mason Yang, Miquel Raynal
From: Mason Yang <masonccyang@mxic.com.tw>
Macronix SPI-NAND chips might benefit from an external ECC
engine. Such an engine might need to access random columns, thus needing
to use random commands (0x84 instead of 0x02).
Signed-off-by: Mason Yang <masonccyang@mxic.com.tw>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/nand/spi/macronix.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macronix.c
index a9890350db02..a97e027bcaad 100644
--- a/drivers/mtd/nand/spi/macronix.c
+++ b/drivers/mtd/nand/spi/macronix.c
@@ -20,7 +20,7 @@ static SPINAND_OP_VARIANTS(read_cache_variants,
static SPINAND_OP_VARIANTS(write_cache_variants,
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
- SPINAND_PROG_LOAD(true, 0, NULL, 0));
+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
static SPINAND_OP_VARIANTS(update_cache_variants,
SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
--
2.27.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [RFC PATCH 02/10] mtd: spinand: macronix: Use random program load
@ 2021-10-08 16:22 ` Miquel Raynal
0 siblings, 0 replies; 39+ messages in thread
From: Miquel Raynal @ 2021-10-08 16:22 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus, linux-mtd
Cc: Rob Herring, Mark Brown, Xiangsheng Hou, Boris Brezillon,
devicetree, linux-spi, linux-kernel, jaimeliao, juliensu,
Thomas Petazzoni, Mason Yang, Miquel Raynal
From: Mason Yang <masonccyang@mxic.com.tw>
Macronix SPI-NAND chips might benefit from an external ECC
engine. Such an engine might need to access random columns, thus needing
to use random commands (0x84 instead of 0x02).
Signed-off-by: Mason Yang <masonccyang@mxic.com.tw>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/nand/spi/macronix.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macronix.c
index a9890350db02..a97e027bcaad 100644
--- a/drivers/mtd/nand/spi/macronix.c
+++ b/drivers/mtd/nand/spi/macronix.c
@@ -20,7 +20,7 @@ static SPINAND_OP_VARIANTS(read_cache_variants,
static SPINAND_OP_VARIANTS(write_cache_variants,
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
- SPINAND_PROG_LOAD(true, 0, NULL, 0));
+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
static SPINAND_OP_VARIANTS(update_cache_variants,
SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
--
2.27.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [RFC PATCH 03/10] dt-bindings: vendor-prefixes: Update Macronix prefix
2021-10-08 16:22 ` Miquel Raynal
@ 2021-10-08 16:22 ` Miquel Raynal
-1 siblings, 0 replies; 39+ messages in thread
From: Miquel Raynal @ 2021-10-08 16:22 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus, linux-mtd
Cc: Rob Herring, Mark Brown, Xiangsheng Hou, Boris Brezillon,
devicetree, linux-spi, linux-kernel, jaimeliao, juliensu,
Thomas Petazzoni, Miquel Raynal
When looking at compatible prefixes, Macronix is sometimes referred as
mxicy:
- mxicy,mx25r1635f
- mxicy,mx25u6435f
- mxicy,mx25v8035f
- mxicy,mx25f0a-spi
and sometimes as mxic:
- mxic,multi-itfc-v009-nand-controller
- mxic,enable-randomizer-otp
It looks like the more up-to-date way is mxic so declare this prefix and
mark the other one as deprecated.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index b868cefc7c55..013a87850cd5 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -758,8 +758,11 @@ patternProperties:
description: Mundo Reader S.L.
"^murata,.*":
description: Murata Manufacturing Co., Ltd.
+ "^mxic,.*":
+ description: Macronix International Co., Ltd.
"^mxicy,.*":
description: Macronix International Co., Ltd.
+ deprecated: true
"^myir,.*":
description: MYIR Tech Limited
"^national,.*":
--
2.27.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [RFC PATCH 03/10] dt-bindings: vendor-prefixes: Update Macronix prefix
@ 2021-10-08 16:22 ` Miquel Raynal
0 siblings, 0 replies; 39+ messages in thread
From: Miquel Raynal @ 2021-10-08 16:22 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus, linux-mtd
Cc: Rob Herring, Mark Brown, Xiangsheng Hou, Boris Brezillon,
devicetree, linux-spi, linux-kernel, jaimeliao, juliensu,
Thomas Petazzoni, Miquel Raynal
When looking at compatible prefixes, Macronix is sometimes referred as
mxicy:
- mxicy,mx25r1635f
- mxicy,mx25u6435f
- mxicy,mx25v8035f
- mxicy,mx25f0a-spi
and sometimes as mxic:
- mxic,multi-itfc-v009-nand-controller
- mxic,enable-randomizer-otp
It looks like the more up-to-date way is mxic so declare this prefix and
mark the other one as deprecated.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index b868cefc7c55..013a87850cd5 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -758,8 +758,11 @@ patternProperties:
description: Mundo Reader S.L.
"^murata,.*":
description: Murata Manufacturing Co., Ltd.
+ "^mxic,.*":
+ description: Macronix International Co., Ltd.
"^mxicy,.*":
description: Macronix International Co., Ltd.
+ deprecated: true
"^myir,.*":
description: MYIR Tech Limited
"^national,.*":
--
2.27.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [RFC PATCH 04/10] dt-bindings: mtd: Describe Macronix NAND ECC engine
2021-10-08 16:22 ` Miquel Raynal
@ 2021-10-08 16:22 ` Miquel Raynal
-1 siblings, 0 replies; 39+ messages in thread
From: Miquel Raynal @ 2021-10-08 16:22 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus, linux-mtd
Cc: Rob Herring, Mark Brown, Xiangsheng Hou, Boris Brezillon,
devicetree, linux-spi, linux-kernel, jaimeliao, juliensu,
Thomas Petazzoni, Miquel Raynal
Describe Macronix NAND ECC engine. This engine may be used as an
external engine or pipelined, both ways are shown in the examples.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
.../bindings/mtd/mxic,nand-ecc-engine.yaml | 78 +++++++++++++++++++
1 file changed, 78 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/mxic,nand-ecc-engine.yaml
diff --git a/Documentation/devicetree/bindings/mtd/mxic,nand-ecc-engine.yaml b/Documentation/devicetree/bindings/mtd/mxic,nand-ecc-engine.yaml
new file mode 100644
index 000000000000..2f5cf1a4e826
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/mxic,nand-ecc-engine.yaml
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/mxic,nand-ecc-engine.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Macronix NAND ECC engine device tree bindings
+
+maintainers:
+ - Miquel Raynal <miquel.raynal@bootlin.com>
+
+properties:
+ compatible:
+ items:
+ - const: mxic,nand-ecc-engine-rev3
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ /* External configuration */
+ spi_controller0: spi@43c30000 {
+ compatible = "mxicy,mx25f0a-spi";
+ reg = <0x43c30000 0x10000>, <0xa0000000 0x4000000>;
+ reg-names = "regs", "dirmap";
+ clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>;
+ clock-names = "send_clk", "send_dly_clk", "ps_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ nand-ecc-engine = <&ecc_engine0>;
+ };
+ };
+
+ ecc_engine0: ecc@43c40000 {
+ compatible = "mxic,nand-ecc-engine-rev3";
+ reg = <0x43c40000 0x10000>;
+ };
+
+ - |
+ /* Pipelined configuration */
+ spi_controller1: spi@43c30000 {
+ compatible = "mxicy,mx25f0a-spi";
+ reg = <0x43c30000 0x10000>, <0xa0000000 0x4000000>;
+ reg-names = "regs", "dirmap";
+ clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>;
+ clock-names = "send_clk", "send_dly_clk", "ps_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nand-ecc-engine = <&ecc_engine1>;
+
+ flash@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ nand-ecc-engine = <&spi_controller1>;
+ };
+ };
+
+ ecc_engine1: ecc@43c40000 {
+ compatible = "mxic,nand-ecc-engine-rev3";
+ reg = <0x43c40000 0x10000>;
+ };
--
2.27.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [RFC PATCH 04/10] dt-bindings: mtd: Describe Macronix NAND ECC engine
@ 2021-10-08 16:22 ` Miquel Raynal
0 siblings, 0 replies; 39+ messages in thread
From: Miquel Raynal @ 2021-10-08 16:22 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus, linux-mtd
Cc: Rob Herring, Mark Brown, Xiangsheng Hou, Boris Brezillon,
devicetree, linux-spi, linux-kernel, jaimeliao, juliensu,
Thomas Petazzoni, Miquel Raynal
Describe Macronix NAND ECC engine. This engine may be used as an
external engine or pipelined, both ways are shown in the examples.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
.../bindings/mtd/mxic,nand-ecc-engine.yaml | 78 +++++++++++++++++++
1 file changed, 78 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/mxic,nand-ecc-engine.yaml
diff --git a/Documentation/devicetree/bindings/mtd/mxic,nand-ecc-engine.yaml b/Documentation/devicetree/bindings/mtd/mxic,nand-ecc-engine.yaml
new file mode 100644
index 000000000000..2f5cf1a4e826
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/mxic,nand-ecc-engine.yaml
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/mxic,nand-ecc-engine.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Macronix NAND ECC engine device tree bindings
+
+maintainers:
+ - Miquel Raynal <miquel.raynal@bootlin.com>
+
+properties:
+ compatible:
+ items:
+ - const: mxic,nand-ecc-engine-rev3
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ /* External configuration */
+ spi_controller0: spi@43c30000 {
+ compatible = "mxicy,mx25f0a-spi";
+ reg = <0x43c30000 0x10000>, <0xa0000000 0x4000000>;
+ reg-names = "regs", "dirmap";
+ clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>;
+ clock-names = "send_clk", "send_dly_clk", "ps_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ nand-ecc-engine = <&ecc_engine0>;
+ };
+ };
+
+ ecc_engine0: ecc@43c40000 {
+ compatible = "mxic,nand-ecc-engine-rev3";
+ reg = <0x43c40000 0x10000>;
+ };
+
+ - |
+ /* Pipelined configuration */
+ spi_controller1: spi@43c30000 {
+ compatible = "mxicy,mx25f0a-spi";
+ reg = <0x43c30000 0x10000>, <0xa0000000 0x4000000>;
+ reg-names = "regs", "dirmap";
+ clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>;
+ clock-names = "send_clk", "send_dly_clk", "ps_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nand-ecc-engine = <&ecc_engine1>;
+
+ flash@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ nand-ecc-engine = <&spi_controller1>;
+ };
+ };
+
+ ecc_engine1: ecc@43c40000 {
+ compatible = "mxic,nand-ecc-engine-rev3";
+ reg = <0x43c40000 0x10000>;
+ };
--
2.27.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [RFC PATCH 05/10] mtd: nand: ecc: Add infrastructure to support hardware engines
2021-10-08 16:22 ` Miquel Raynal
@ 2021-10-08 16:22 ` Miquel Raynal
-1 siblings, 0 replies; 39+ messages in thread
From: Miquel Raynal @ 2021-10-08 16:22 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus, linux-mtd
Cc: Rob Herring, Mark Brown, Xiangsheng Hou, Boris Brezillon,
devicetree, linux-spi, linux-kernel, jaimeliao, juliensu,
Thomas Petazzoni, Miquel Raynal
Add the necessary helpers to register/unregister hardware ECC engines
that will be called from ECC engine drivers.
Also add helpers to get the right engine from the user
perspective. Keep a reference of the in use ECC engine in order to
prevent modules to be unloaded. Put the reference when the engine gets
retired.
A static list of hardware (only) ECC engines is setup to keep track of
the registered engines.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/nand/core.c | 10 +++--
drivers/mtd/nand/ecc.c | 89 ++++++++++++++++++++++++++++++++++++++++
include/linux/mtd/nand.h | 11 +++++
3 files changed, 107 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c
index df9646685c91..5628bd410f7e 100644
--- a/drivers/mtd/nand/core.c
+++ b/drivers/mtd/nand/core.c
@@ -232,7 +232,9 @@ static int nanddev_get_ecc_engine(struct nand_device *nand)
nand->ecc.engine = nand_ecc_get_on_die_hw_engine(nand);
break;
case NAND_ECC_ENGINE_TYPE_ON_HOST:
- pr_err("On-host hardware ECC engines not supported yet\n");
+ nand->ecc.engine = nand_ecc_get_on_host_hw_engine(nand);
+ if (PTR_ERR(nand->ecc.engine) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
break;
default:
pr_err("Missing ECC engine type\n");
@@ -252,7 +254,7 @@ static int nanddev_put_ecc_engine(struct nand_device *nand)
{
switch (nand->ecc.ctx.conf.engine_type) {
case NAND_ECC_ENGINE_TYPE_ON_HOST:
- pr_err("On-host hardware ECC engines not supported yet\n");
+ nand_ecc_put_on_host_hw_engine(nand);
break;
case NAND_ECC_ENGINE_TYPE_NONE:
case NAND_ECC_ENGINE_TYPE_SOFT:
@@ -297,7 +299,9 @@ int nanddev_ecc_engine_init(struct nand_device *nand)
/* Look for the ECC engine to use */
ret = nanddev_get_ecc_engine(nand);
if (ret) {
- pr_err("No ECC engine found\n");
+ if (ret != -EPROBE_DEFER)
+ pr_err("No ECC engine found\n");
+
return ret;
}
diff --git a/drivers/mtd/nand/ecc.c b/drivers/mtd/nand/ecc.c
index 6c43dfda01d4..3aa56c990d11 100644
--- a/drivers/mtd/nand/ecc.c
+++ b/drivers/mtd/nand/ecc.c
@@ -96,6 +96,12 @@
#include <linux/module.h>
#include <linux/mtd/nand.h>
#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+
+static LIST_HEAD(on_host_hw_engines);
+static DEFINE_MUTEX(on_host_hw_engines_mutex);
/**
* nand_ecc_init_ctx - Init the ECC engine context
@@ -611,6 +617,89 @@ struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand)
}
EXPORT_SYMBOL(nand_ecc_get_on_die_hw_engine);
+int nand_ecc_register_on_host_hw_engine(struct nand_ecc_engine *engine)
+{
+ struct nand_ecc_engine *item;
+
+ if (!engine)
+ return -ENOTSUPP;
+
+ /* Prevent multiple registrations of one engine */
+ list_for_each_entry(item, &on_host_hw_engines, node)
+ if (item == engine)
+ return 0;
+
+ mutex_lock(&on_host_hw_engines_mutex);
+ list_add_tail(&engine->node, &on_host_hw_engines);
+ mutex_unlock(&on_host_hw_engines_mutex);
+
+ return 0;
+}
+EXPORT_SYMBOL(nand_ecc_register_on_host_hw_engine);
+
+int nand_ecc_unregister_on_host_hw_engine(struct nand_ecc_engine *engine)
+{
+ if (!engine)
+ return -ENOTSUPP;
+
+ mutex_lock(&on_host_hw_engines_mutex);
+ list_del(&engine->node);
+ mutex_unlock(&on_host_hw_engines_mutex);
+
+ return 0;
+}
+EXPORT_SYMBOL(nand_ecc_unregister_on_host_hw_engine);
+
+struct nand_ecc_engine *nand_ecc_match_on_host_hw_engine(struct device *dev)
+{
+ struct nand_ecc_engine *item;
+
+ list_for_each_entry(item, &on_host_hw_engines, node)
+ if (item->dev == dev)
+ return item;
+
+ return NULL;
+}
+EXPORT_SYMBOL(nand_ecc_match_on_host_hw_engine);
+
+struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand)
+{
+ struct nand_ecc_engine *engine = NULL;
+ struct device *dev = &nand->mtd.dev;
+ struct platform_device *pdev;
+ struct device_node *np;
+
+ if (list_empty(&on_host_hw_engines))
+ return NULL;
+
+ /* Check for an explicit nand-ecc-engine property */
+ np = of_parse_phandle(dev->of_node, "nand-ecc-engine", 0);
+ if (np) {
+ pdev = of_find_device_by_node(np);
+ if (!pdev)
+ return ERR_PTR(-EPROBE_DEFER);
+
+ engine = nand_ecc_match_on_host_hw_engine(&pdev->dev);
+ platform_device_put(pdev);
+ of_node_put(np);
+
+ if (!engine)
+ return ERR_PTR(-EPROBE_DEFER);
+ }
+
+ if (engine)
+ get_device(engine->dev);
+
+ return engine;
+}
+EXPORT_SYMBOL(nand_ecc_get_on_host_hw_engine);
+
+void nand_ecc_put_on_host_hw_engine(struct nand_device *nand)
+{
+ put_device(nand->ecc.engine->dev);
+}
+EXPORT_SYMBOL(nand_ecc_put_on_host_hw_engine);
+
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>");
MODULE_DESCRIPTION("Generic ECC engine");
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 32fc7edf65b3..5ffd3e359515 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -265,10 +265,16 @@ struct nand_ecc_engine_ops {
/**
* struct nand_ecc_engine - ECC engine abstraction for NAND devices
+ * @dev: Host device
+ * @node: Private field for registration time
* @ops: ECC engine operations
+ * @priv: Private data
*/
struct nand_ecc_engine {
+ struct device *dev;
+ struct list_head node;
struct nand_ecc_engine_ops *ops;
+ void *priv;
};
void of_get_nand_ecc_user_config(struct nand_device *nand);
@@ -279,8 +285,13 @@ int nand_ecc_prepare_io_req(struct nand_device *nand,
int nand_ecc_finish_io_req(struct nand_device *nand,
struct nand_page_io_req *req);
bool nand_ecc_is_strong_enough(struct nand_device *nand);
+int nand_ecc_register_on_host_hw_engine(struct nand_ecc_engine *engine);
+int nand_ecc_unregister_on_host_hw_engine(struct nand_ecc_engine *engine);
struct nand_ecc_engine *nand_ecc_get_sw_engine(struct nand_device *nand);
struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand);
+struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand);
+struct nand_ecc_engine *nand_ecc_match_on_host_hw_engine(struct device *dev);
+void nand_ecc_put_on_host_hw_engine(struct nand_device *nand);
#if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING)
struct nand_ecc_engine *nand_ecc_sw_hamming_get_engine(void);
--
2.27.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [RFC PATCH 05/10] mtd: nand: ecc: Add infrastructure to support hardware engines
@ 2021-10-08 16:22 ` Miquel Raynal
0 siblings, 0 replies; 39+ messages in thread
From: Miquel Raynal @ 2021-10-08 16:22 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus, linux-mtd
Cc: Rob Herring, Mark Brown, Xiangsheng Hou, Boris Brezillon,
devicetree, linux-spi, linux-kernel, jaimeliao, juliensu,
Thomas Petazzoni, Miquel Raynal
Add the necessary helpers to register/unregister hardware ECC engines
that will be called from ECC engine drivers.
Also add helpers to get the right engine from the user
perspective. Keep a reference of the in use ECC engine in order to
prevent modules to be unloaded. Put the reference when the engine gets
retired.
A static list of hardware (only) ECC engines is setup to keep track of
the registered engines.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/nand/core.c | 10 +++--
drivers/mtd/nand/ecc.c | 89 ++++++++++++++++++++++++++++++++++++++++
include/linux/mtd/nand.h | 11 +++++
3 files changed, 107 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c
index df9646685c91..5628bd410f7e 100644
--- a/drivers/mtd/nand/core.c
+++ b/drivers/mtd/nand/core.c
@@ -232,7 +232,9 @@ static int nanddev_get_ecc_engine(struct nand_device *nand)
nand->ecc.engine = nand_ecc_get_on_die_hw_engine(nand);
break;
case NAND_ECC_ENGINE_TYPE_ON_HOST:
- pr_err("On-host hardware ECC engines not supported yet\n");
+ nand->ecc.engine = nand_ecc_get_on_host_hw_engine(nand);
+ if (PTR_ERR(nand->ecc.engine) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
break;
default:
pr_err("Missing ECC engine type\n");
@@ -252,7 +254,7 @@ static int nanddev_put_ecc_engine(struct nand_device *nand)
{
switch (nand->ecc.ctx.conf.engine_type) {
case NAND_ECC_ENGINE_TYPE_ON_HOST:
- pr_err("On-host hardware ECC engines not supported yet\n");
+ nand_ecc_put_on_host_hw_engine(nand);
break;
case NAND_ECC_ENGINE_TYPE_NONE:
case NAND_ECC_ENGINE_TYPE_SOFT:
@@ -297,7 +299,9 @@ int nanddev_ecc_engine_init(struct nand_device *nand)
/* Look for the ECC engine to use */
ret = nanddev_get_ecc_engine(nand);
if (ret) {
- pr_err("No ECC engine found\n");
+ if (ret != -EPROBE_DEFER)
+ pr_err("No ECC engine found\n");
+
return ret;
}
diff --git a/drivers/mtd/nand/ecc.c b/drivers/mtd/nand/ecc.c
index 6c43dfda01d4..3aa56c990d11 100644
--- a/drivers/mtd/nand/ecc.c
+++ b/drivers/mtd/nand/ecc.c
@@ -96,6 +96,12 @@
#include <linux/module.h>
#include <linux/mtd/nand.h>
#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+
+static LIST_HEAD(on_host_hw_engines);
+static DEFINE_MUTEX(on_host_hw_engines_mutex);
/**
* nand_ecc_init_ctx - Init the ECC engine context
@@ -611,6 +617,89 @@ struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand)
}
EXPORT_SYMBOL(nand_ecc_get_on_die_hw_engine);
+int nand_ecc_register_on_host_hw_engine(struct nand_ecc_engine *engine)
+{
+ struct nand_ecc_engine *item;
+
+ if (!engine)
+ return -ENOTSUPP;
+
+ /* Prevent multiple registrations of one engine */
+ list_for_each_entry(item, &on_host_hw_engines, node)
+ if (item == engine)
+ return 0;
+
+ mutex_lock(&on_host_hw_engines_mutex);
+ list_add_tail(&engine->node, &on_host_hw_engines);
+ mutex_unlock(&on_host_hw_engines_mutex);
+
+ return 0;
+}
+EXPORT_SYMBOL(nand_ecc_register_on_host_hw_engine);
+
+int nand_ecc_unregister_on_host_hw_engine(struct nand_ecc_engine *engine)
+{
+ if (!engine)
+ return -ENOTSUPP;
+
+ mutex_lock(&on_host_hw_engines_mutex);
+ list_del(&engine->node);
+ mutex_unlock(&on_host_hw_engines_mutex);
+
+ return 0;
+}
+EXPORT_SYMBOL(nand_ecc_unregister_on_host_hw_engine);
+
+struct nand_ecc_engine *nand_ecc_match_on_host_hw_engine(struct device *dev)
+{
+ struct nand_ecc_engine *item;
+
+ list_for_each_entry(item, &on_host_hw_engines, node)
+ if (item->dev == dev)
+ return item;
+
+ return NULL;
+}
+EXPORT_SYMBOL(nand_ecc_match_on_host_hw_engine);
+
+struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand)
+{
+ struct nand_ecc_engine *engine = NULL;
+ struct device *dev = &nand->mtd.dev;
+ struct platform_device *pdev;
+ struct device_node *np;
+
+ if (list_empty(&on_host_hw_engines))
+ return NULL;
+
+ /* Check for an explicit nand-ecc-engine property */
+ np = of_parse_phandle(dev->of_node, "nand-ecc-engine", 0);
+ if (np) {
+ pdev = of_find_device_by_node(np);
+ if (!pdev)
+ return ERR_PTR(-EPROBE_DEFER);
+
+ engine = nand_ecc_match_on_host_hw_engine(&pdev->dev);
+ platform_device_put(pdev);
+ of_node_put(np);
+
+ if (!engine)
+ return ERR_PTR(-EPROBE_DEFER);
+ }
+
+ if (engine)
+ get_device(engine->dev);
+
+ return engine;
+}
+EXPORT_SYMBOL(nand_ecc_get_on_host_hw_engine);
+
+void nand_ecc_put_on_host_hw_engine(struct nand_device *nand)
+{
+ put_device(nand->ecc.engine->dev);
+}
+EXPORT_SYMBOL(nand_ecc_put_on_host_hw_engine);
+
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>");
MODULE_DESCRIPTION("Generic ECC engine");
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 32fc7edf65b3..5ffd3e359515 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -265,10 +265,16 @@ struct nand_ecc_engine_ops {
/**
* struct nand_ecc_engine - ECC engine abstraction for NAND devices
+ * @dev: Host device
+ * @node: Private field for registration time
* @ops: ECC engine operations
+ * @priv: Private data
*/
struct nand_ecc_engine {
+ struct device *dev;
+ struct list_head node;
struct nand_ecc_engine_ops *ops;
+ void *priv;
};
void of_get_nand_ecc_user_config(struct nand_device *nand);
@@ -279,8 +285,13 @@ int nand_ecc_prepare_io_req(struct nand_device *nand,
int nand_ecc_finish_io_req(struct nand_device *nand,
struct nand_page_io_req *req);
bool nand_ecc_is_strong_enough(struct nand_device *nand);
+int nand_ecc_register_on_host_hw_engine(struct nand_ecc_engine *engine);
+int nand_ecc_unregister_on_host_hw_engine(struct nand_ecc_engine *engine);
struct nand_ecc_engine *nand_ecc_get_sw_engine(struct nand_device *nand);
struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand);
+struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand);
+struct nand_ecc_engine *nand_ecc_match_on_host_hw_engine(struct device *dev);
+void nand_ecc_put_on_host_hw_engine(struct nand_device *nand);
#if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING)
struct nand_ecc_engine *nand_ecc_sw_hamming_get_engine(void);
--
2.27.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [RFC PATCH 06/10] mtd: nand: mxic-ecc: Add Macronix external ECC engine support
2021-10-08 16:22 ` Miquel Raynal
@ 2021-10-08 16:22 ` Miquel Raynal
-1 siblings, 0 replies; 39+ messages in thread
From: Miquel Raynal @ 2021-10-08 16:22 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus, linux-mtd
Cc: Rob Herring, Mark Brown, Xiangsheng Hou, Boris Brezillon,
devicetree, linux-spi, linux-kernel, jaimeliao, juliensu,
Thomas Petazzoni, Miquel Raynal
Some SPI-NAND chips do not support on-die ECC. For these chips,
correction must apply on the SPI controller end. In order to avoid
doing all the calculations by software, Macronix provides a specific
engine that can offload the intensive work.
Add Macronix ECC engine support, this engine can work in conjunction
with a SPI controller and a raw NAND controller, it can be pipelined
or external and supports linear and syndrome layouts.
Right now the simplest configuration is supported: SPI controller
external and linear ECC engine.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/nand/Kconfig | 6 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/ecc-mxic.c | 655 ++++++++++++++++++++++++++++++++++++
3 files changed, 662 insertions(+)
create mode 100644 drivers/mtd/nand/ecc-mxic.c
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index b40455234cbd..8431292ff49d 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -46,6 +46,12 @@ config MTD_NAND_ECC_SW_BCH
ECC codes. They are used with NAND devices requiring more than 1 bit
of error correction.
+config MTD_NAND_ECC_MXIC
+ bool "Macronix external hardware ECC engine"
+ select MTD_NAND_ECC
+ help
+ This enables support for the hardware ECC engine from Macronix.
+
endmenu
endmenu
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 1c0b46960eb1..a4e6b7ae0614 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -10,3 +10,4 @@ obj-y += spi/
nandcore-$(CONFIG_MTD_NAND_ECC) += ecc.o
nandcore-$(CONFIG_MTD_NAND_ECC_SW_HAMMING) += ecc-sw-hamming.o
nandcore-$(CONFIG_MTD_NAND_ECC_SW_BCH) += ecc-sw-bch.o
+nandcore-$(CONFIG_MTD_NAND_ECC_MXIC) += ecc-mxic.o
diff --git a/drivers/mtd/nand/ecc-mxic.c b/drivers/mtd/nand/ecc-mxic.c
new file mode 100644
index 000000000000..8be816381f68
--- /dev/null
+++ b/drivers/mtd/nand/ecc-mxic.c
@@ -0,0 +1,655 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Support for Macronix external hardware ECC engine for NAND devices, also
+ * called DPE for Data Processing Engine.
+ *
+ * Copyright © 2019 Macronix
+ * Author: Miquel Raynal <miquel.raynal@bootlin.com>
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+/* DPE Configuration */
+#define DP_CONFIG 0x00
+#define ECC_EN BIT(0)
+#define ECC_TYP(idx) (((idx) << 3) & GENMASK(6, 3))
+/* DPE Interrupt Status */
+#define INTRPT_STS 0x04
+#define TRANS_CMPLT BIT(0)
+#define SDMA_MAIN BIT(1)
+#define SDMA_SPARE BIT(2)
+#define ECC_ERR BIT(3)
+#define TO_SPARE BIT(4)
+#define TO_MAIN BIT(5)
+/* DPE Interrupt Status Enable */
+#define INTRPT_STS_EN 0x08
+/* DPE Interrupt Signal Enable */
+#define INTRPT_SIG_EN 0x0C
+/* Host Controller Configuration */
+#define HC_CONFIG 0x10
+#define MEM2MEM BIT(4) /* TRANS_TYP_IO in the spec */
+#define ECC_PACKED 0 /* LAYOUT_TYP_INTEGRATED in the spec */
+#define ECC_INTERLEAVED BIT(2) /* LAYOUT_TYP_DISTRIBUTED in the spec */
+#define BURST_TYP_FIXED 0
+#define BURST_TYP_INCREASING BIT(0)
+/* Host Controller Slave Address */
+#define HC_SLV_ADDR 0x14
+/* ECC Chunk Size */
+#define CHUNK_SIZE 0x20
+/* Main Data Size */
+#define MAIN_SIZE 0x24
+/* Spare Data Size */
+#define SPARE_SIZE 0x28
+#define META_SZ(reg) ((reg) & GENMASK(7, 0))
+#define PARITY_SZ(reg) (((reg) & GENMASK(15, 8)) >> 8)
+#define RSV_SZ(reg) (((reg) & GENMASK(23, 16)) >> 16)
+#define SPARE_SZ(reg) ((reg) >> 24)
+/* ECC Chunk Count */
+#define CHUNK_CNT 0x30
+/* SDMA Control */
+#define SDMA_CTRL 0x40
+#define WRITE_NAND 0
+#define READ_NAND BIT(1)
+#define CONT_NAND BIT(29)
+#define CONT_SYSM BIT(30) /* Continue System Memory? */
+#define SDMA_STRT BIT(31)
+/* SDMA Address of Main Data */
+#define SDMA_MAIN_ADDR 0x44
+/* SDMA Address of Spare Data */
+#define SDMA_SPARE_ADDR 0x48
+/* DPE Version Number */
+#define DP_VER 0xD0
+#define DP_VER_OFFSET 16
+
+/* Status bytes between each chunk of spare data */
+#define STAT_BYTES 4
+#define NO_ERR 0x00
+#define MAX_CORR_ERR 0x28
+#define UNCORR_ERR 0xFE
+#define ERASED_CHUNK 0xFF
+
+struct mxic_ecc_engine {
+ struct device *dev;
+ void __iomem *regs;
+
+ /* ECC machinery */
+ unsigned int data_step_sz;
+ unsigned int oob_step_sz;
+ unsigned int parity_sz;
+ unsigned int meta_sz;
+ u8 *status;
+ int steps;
+
+ /* Completion boilerplate */
+ int irq;
+ struct completion complete;
+
+ /* DMA boilerplate */
+ struct nand_ecc_req_tweak_ctx req_ctx;
+ u8 *oobwithstat;
+ struct scatterlist sg[2];
+ struct nand_page_io_req *req;
+};
+
+static int mxic_ecc_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ struct nand_device *nand = mtd_to_nanddev(mtd);
+ struct mxic_ecc_engine *eng = nand->ecc.ctx.priv;
+
+ if (section < 0 || section >= eng->steps)
+ return -ERANGE;
+
+ oobregion->offset = (section * eng->oob_step_sz) + eng->meta_sz;
+ oobregion->length = eng->parity_sz;
+
+ return 0;
+}
+
+static int mxic_ecc_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ struct nand_device *nand = mtd_to_nanddev(mtd);
+ struct mxic_ecc_engine *eng = nand->ecc.ctx.priv;
+
+ if (section < 0 || section >= eng->steps)
+ return -ERANGE;
+
+ if (!section) {
+ oobregion->offset = 2;
+ oobregion->length = eng->meta_sz - 2;
+ } else {
+ oobregion->offset = section * eng->oob_step_sz;
+ oobregion->length = eng->meta_sz;
+ }
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops mxic_ecc_ooblayout_ops = {
+ .ecc = mxic_ecc_ooblayout_ecc,
+ .free = mxic_ecc_ooblayout_free,
+};
+
+static void mxic_ecc_disable_engine(struct mxic_ecc_engine *eng)
+{
+ u32 reg;
+
+ reg = readl(eng->regs + DP_CONFIG);
+ reg &= ~ECC_EN;
+ writel(reg, eng->regs + DP_CONFIG);
+}
+
+static void mxic_ecc_enable_engine(struct mxic_ecc_engine *eng)
+{
+ u32 reg;
+
+ reg = readl(eng->regs + DP_CONFIG);
+ reg |= ECC_EN;
+ writel(reg, eng->regs + DP_CONFIG);
+}
+
+static void mxic_ecc_disable_int(struct mxic_ecc_engine *eng)
+{
+ writel(0, eng->regs + INTRPT_SIG_EN);
+}
+
+static void mxic_ecc_enable_int(struct mxic_ecc_engine *eng)
+{
+ writel(TRANS_CMPLT, eng->regs + INTRPT_SIG_EN);
+}
+
+static irqreturn_t mxic_ecc_isr(int irq, void *dev_id)
+{
+ struct mxic_ecc_engine *eng = dev_id;
+ u32 sts;
+
+ sts = readl(eng->regs + INTRPT_STS);
+ if (!sts)
+ return IRQ_NONE;
+
+ if (sts & TRANS_CMPLT)
+ complete(&eng->complete);
+
+ writel(sts, eng->regs + INTRPT_STS);
+
+ return IRQ_HANDLED;
+}
+
+static int mxic_ecc_init_ctx(struct nand_device *nand, struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct nand_ecc_props *conf = &nand->ecc.ctx.conf;
+ struct nand_ecc_props *reqs = &nand->ecc.requirements;
+ struct nand_ecc_props *user = &nand->ecc.user_conf;
+ struct mtd_info *mtd = nanddev_to_mtd(nand);
+ struct mxic_ecc_engine *eng;
+ int step_size = 0, strength = 0, desired_correction = 0, steps, idx;
+ int possible_strength[] = {4, 8, 40, 48};
+ int spare_size[] = {32, 32, 96, 96};
+ u32 spare_reg;
+ int ret;
+
+ eng = devm_kzalloc(dev, sizeof(*eng), GFP_KERNEL);
+ if (!eng)
+ return -ENOMEM;
+
+ nand->ecc.ctx.priv = eng;
+ nand->ecc.engine->priv = eng;
+
+ eng->dev = dev;
+
+ /*
+ * Both memory regions for the ECC engine itself and the AXI slave
+ * address are mandatory.
+ */
+ eng->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(eng->regs)) {
+ dev_err(dev, "Missing memory region\n");
+ return PTR_ERR(eng->regs);
+ }
+
+ mxic_ecc_disable_engine(eng);
+ mxic_ecc_disable_int(eng);
+
+ /* IRQ is optional yet much more efficient */
+ eng->irq = platform_get_irq_byname(pdev, "ecc-engine");
+ if (eng->irq > 0) {
+ ret = devm_request_irq(dev, eng->irq, mxic_ecc_isr, 0,
+ "mxic-ecc", eng);
+ if (ret)
+ return ret;
+ } else {
+ dev_info(dev, "No ECC engine IRQ (%d), using polling\n",
+ eng->irq);
+ eng->irq = 0;
+ }
+
+ /* Only large page NAND chips may use BCH */
+ if (mtd->oobsize < 64) {
+ pr_err("BCH cannot be used with small page NAND chips\n");
+ return -EINVAL;
+ }
+
+ mtd_set_ooblayout(mtd, &mxic_ecc_ooblayout_ops);
+
+ /* Enable all status bits */
+ writel(TRANS_CMPLT | SDMA_MAIN | SDMA_SPARE | ECC_ERR |
+ TO_SPARE | TO_MAIN, eng->regs + INTRPT_STS_EN);
+
+ /* Configure the correction depending on the NAND device topology */
+ if (user->step_size && user->strength) {
+ step_size = user->step_size;
+ strength = user->strength;
+ } else if (reqs->step_size && reqs->strength) {
+ step_size = reqs->step_size;
+ strength = reqs->strength;
+ }
+
+ if (step_size && strength) {
+ steps = mtd->writesize / step_size;
+ desired_correction = steps * strength;
+ }
+
+ /* Step size is fixed to 1kiB, strength may vary (4 possible values) */
+ conf->step_size = SZ_1K;
+ steps = mtd->writesize / conf->step_size;
+
+ eng->status = devm_kzalloc(dev, steps * sizeof(u8), GFP_KERNEL);
+ if (!eng->status)
+ return -ENOMEM;
+
+ if (desired_correction) {
+ strength = desired_correction / steps;
+
+ for (idx = 0; idx < ARRAY_SIZE(possible_strength); idx++)
+ if (possible_strength[idx] >= strength)
+ break;
+
+ idx = min_t(unsigned int, idx,
+ ARRAY_SIZE(possible_strength) - 1);
+ } else {
+ /* Missing data, maximize the correction */
+ idx = ARRAY_SIZE(possible_strength) - 1;
+ }
+
+ /* Tune the selected strength until it fits in the OOB area */
+ for (; idx >= 0; idx--) {
+ if (spare_size[idx] * steps <= mtd->oobsize)
+ break;
+ }
+
+ /* This engine cannot be used with this NAND device */
+ if (idx < 0)
+ return -EINVAL;
+
+ /* Configure the engine for the desired strength */
+ writel(ECC_TYP(idx), eng->regs + DP_CONFIG);
+ conf->strength = possible_strength[idx];
+ spare_reg = readl(eng->regs + SPARE_SIZE);
+
+ eng->steps = steps;
+ eng->data_step_sz = mtd->writesize / steps;
+ eng->oob_step_sz = mtd->oobsize / steps;
+ eng->parity_sz = PARITY_SZ(spare_reg);
+ eng->meta_sz = META_SZ(spare_reg);
+
+ /* Ensure buffers will contain enough bytes to store the STAT_BYTES */
+ eng->req_ctx.oob_buffer_size = nanddev_per_page_oobsize(nand) +
+ (eng->steps * STAT_BYTES);
+ ret = nand_ecc_init_req_tweaking(&eng->req_ctx, nand);
+ if (ret)
+ return ret;
+
+ eng->oobwithstat = kmalloc(mtd->oobsize + (eng->steps * STAT_BYTES),
+ GFP_KERNEL);
+ if (!eng->oobwithstat) {
+ ret = -ENOMEM;
+ goto cleanup_req_tweak;
+ }
+
+ sg_init_table(eng->sg, 2);
+
+ /* Configuration dump and sanity checks */
+ dev_err(dev, "DPE version number: %d\n",
+ readl(eng->regs + DP_VER) >> DP_VER_OFFSET);
+ dev_err(dev, "Chunk size: %d\n", readl(eng->regs + CHUNK_SIZE));
+ dev_err(dev, "Main size: %d\n", readl(eng->regs + MAIN_SIZE));
+ dev_err(dev, "Spare size: %d\n", SPARE_SZ(spare_reg));
+ dev_err(dev, "Rsv size: %ld\n", RSV_SZ(spare_reg));
+ dev_err(dev, "Parity size: %d\n", eng->parity_sz);
+ dev_err(dev, "Meta size: %d\n", eng->meta_sz);
+
+ if (eng->meta_sz + eng->parity_sz + RSV_SZ(spare_reg) != SPARE_SZ(spare_reg)) {
+ dev_err(dev, "Wrong OOB configuration: %d + %d + %ld != %d\n",
+ eng->meta_sz, eng->parity_sz, RSV_SZ(spare_reg),
+ SPARE_SZ(spare_reg));
+ ret = -EINVAL;
+ goto free_oobwithstat;
+ }
+
+ if (eng->oob_step_sz != SPARE_SZ(spare_reg)) {
+ dev_err(dev, "Wrong OOB configuration: %d != %d\n",
+ eng->oob_step_sz, SPARE_SZ(spare_reg));
+ ret = -EINVAL;
+ goto free_oobwithstat;
+ }
+
+ return 0;
+
+free_oobwithstat:
+ kfree(eng->oobwithstat);
+cleanup_req_tweak:
+ nand_ecc_cleanup_req_tweaking(&eng->req_ctx);
+
+ return ret;
+}
+
+static int mxic_ecc_init_ctx_external(struct nand_device *nand)
+{
+ struct device *dev = nand->ecc.engine->dev;
+ struct mxic_ecc_engine *eng;
+ int ret;
+
+ dev_info(dev, "Macronix ECC engine in external mode\n");
+
+ ret = mxic_ecc_init_ctx(nand, dev);
+ if (ret)
+ return ret;
+
+ eng = nand->ecc.ctx.priv;
+
+ /* Trigger each step manually */
+ writel(1, eng->regs + CHUNK_CNT);
+ writel(BURST_TYP_INCREASING | ECC_PACKED | MEM2MEM,
+ eng->regs + HC_CONFIG);
+
+ return 0;
+}
+
+static void mxic_ecc_cleanup_ctx(struct nand_device *nand)
+{
+ struct mxic_ecc_engine *eng = nand->ecc.ctx.priv;
+
+ if (eng) {
+ nand_ecc_cleanup_req_tweaking(&eng->req_ctx);
+ kfree(eng->oobwithstat);
+ }
+}
+
+static int mxic_ecc_data_xfer_wait_for_completion(struct mxic_ecc_engine *eng)
+{
+ u32 val;
+ int ret;
+
+ if (eng->irq) {
+ init_completion(&eng->complete);
+ mxic_ecc_enable_int(eng);
+ ret = wait_for_completion_timeout(&eng->complete,
+ msecs_to_jiffies(1000));
+ mxic_ecc_disable_int(eng);
+ } else {
+ ret = readl_poll_timeout(eng->regs + INTRPT_STS, val,
+ val & TRANS_CMPLT, 10, USEC_PER_SEC);
+ writel(val, eng->regs + INTRPT_STS);
+ }
+
+ if (ret) {
+ dev_err(eng->dev, "Timeout on data xfer completion (sts 0x%08x)\n", val);
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static int mxic_ecc_process_data(struct mxic_ecc_engine *eng)
+{
+ /* Retrieve the direction */
+ unsigned int dir = (eng->req->type == NAND_PAGE_READ) ?
+ READ_NAND : WRITE_NAND;
+
+ /* Trigger processing */
+ writel(SDMA_STRT | dir, eng->regs + SDMA_CTRL);
+
+ /* Wait for completion */
+ return mxic_ecc_data_xfer_wait_for_completion(eng);
+}
+
+static void mxic_ecc_extract_status_bytes(struct mxic_ecc_engine *eng, u8 *buf)
+{
+ int next_stat_pos;
+ int step;
+
+ /* Extract the ECC status */
+ for (step = 0; step < eng->steps; step++) {
+ next_stat_pos = eng->oob_step_sz +
+ ((STAT_BYTES + eng->oob_step_sz) * step);
+
+ eng->status[step] = buf[next_stat_pos];
+ }
+}
+
+static void mxic_ecc_reconstruct_oobbuf(struct mxic_ecc_engine *eng,
+ u8 *dst, const u8 *src)
+{
+ int step;
+
+ /* Reconstruct the OOB buffer linearly (without the ECC status bytes) */
+ for (step = 0; step < eng->steps; step++)
+ memcpy(dst + (step * eng->oob_step_sz),
+ src + (step * (eng->oob_step_sz + STAT_BYTES)),
+ eng->oob_step_sz);
+}
+
+static void mxic_ecc_add_room_in_oobbuf(struct mxic_ecc_engine *eng,
+ u8 *dst, const u8 *src)
+{
+ int step;
+
+ /* Add some space in the OOB buffer for the status bytes */
+ for (step = 0; step < eng->steps; step++)
+ memcpy(dst + (step * (eng->oob_step_sz + STAT_BYTES)),
+ src + (step * eng->oob_step_sz),
+ eng->oob_step_sz);
+}
+
+static int mxic_ecc_count_biterrs(struct mxic_ecc_engine *eng, struct mtd_info *mtd)
+{
+ struct device *dev = eng->dev;
+ unsigned int max_bf = 0;
+ int step;
+
+ for (step = 0; step < eng->steps; step++) {
+ u8 stat = eng->status[step];
+
+ if (stat == NO_ERR) {
+ dev_dbg(dev, "ECC step %d: no error\n", step);
+ } else if (stat == ERASED_CHUNK) {
+ dev_dbg(dev, "ECC step %d: erased\n", step);
+ } else if (stat == UNCORR_ERR || stat > MAX_CORR_ERR) {
+ dev_dbg(dev, "ECC step %d: uncorrectable\n", step);
+ mtd->ecc_stats.failed++;
+ } else {
+ dev_dbg(dev, "ECC step %d: %d bits corrected\n",
+ step, stat);
+ max_bf = max_t(unsigned int, max_bf, stat);
+ mtd->ecc_stats.corrected += stat;
+ }
+ }
+
+ return max_bf;
+}
+
+/* External ECC engine helpers */
+static int mxic_ecc_prepare_io_req_external(struct nand_device *nand,
+ struct nand_page_io_req *req)
+{
+ struct mxic_ecc_engine *eng = nand->ecc.ctx.priv;
+ struct mtd_info *mtd = nanddev_to_mtd(nand);
+ int offset, nents, step, ret;
+
+ if (req->mode == MTD_OPS_RAW)
+ return 0;
+
+ nand_ecc_tweak_req(&eng->req_ctx, req);
+ eng->req = req;
+
+ if (req->type == NAND_PAGE_READ)
+ return 0;
+
+ mxic_ecc_add_room_in_oobbuf(eng, eng->oobwithstat, eng->req->oobbuf.out);
+
+ sg_set_buf(&eng->sg[0], req->databuf.out, req->datalen);
+ sg_set_buf(&eng->sg[1], eng->oobwithstat,
+ req->ooblen + (eng->steps * STAT_BYTES));
+
+ nents = dma_map_sg(eng->dev, eng->sg, 2, DMA_BIDIRECTIONAL);
+ if (!nents)
+ return -EINVAL;
+
+ mxic_ecc_enable_engine(eng);
+
+ for (step = 0; step < eng->steps; step++) {
+ writel(sg_dma_address(&eng->sg[0]) + (step * eng->data_step_sz),
+ eng->regs + SDMA_MAIN_ADDR);
+ writel(sg_dma_address(&eng->sg[1]) + (step * (eng->oob_step_sz + STAT_BYTES)),
+ eng->regs + SDMA_SPARE_ADDR);
+ ret = mxic_ecc_process_data(eng);
+ if (ret)
+ break;
+ }
+
+ mxic_ecc_disable_engine(eng);
+
+ dma_unmap_sg(eng->dev, eng->sg, 2, DMA_BIDIRECTIONAL);
+
+ /* Retrieve the calculated ECC bytes */
+ for (step = 0; step < eng->steps; step++) {
+ offset = eng->meta_sz + (step * eng->oob_step_sz);
+ mtd_ooblayout_get_eccbytes(mtd,
+ (u8 *)eng->req->oobbuf.out + offset,
+ eng->oobwithstat,
+ step * eng->parity_sz,
+ eng->parity_sz);
+ }
+
+ return ret;
+}
+
+static int mxic_ecc_finish_io_req_external(struct nand_device *nand,
+ struct nand_page_io_req *req)
+{
+ struct mxic_ecc_engine *eng = nand->ecc.ctx.priv;
+ struct mtd_info *mtd = nanddev_to_mtd(nand);
+ int nents, step, ret;
+
+ if (req->mode == MTD_OPS_RAW)
+ return 0;
+
+ if (req->type == NAND_PAGE_WRITE) {
+ nand_ecc_restore_req(&eng->req_ctx, req);
+ return 0;
+ }
+
+ /* Copy the OOB buffer and add room for the ECC engine status bytes */
+ mxic_ecc_add_room_in_oobbuf(eng, eng->oobwithstat, eng->req->oobbuf.in);
+
+ sg_set_buf(&eng->sg[0], req->databuf.in, req->datalen);
+ sg_set_buf(&eng->sg[1], eng->oobwithstat,
+ req->ooblen + (eng->steps * STAT_BYTES));
+ nents = dma_map_sg(eng->dev, eng->sg, 2, DMA_BIDIRECTIONAL);
+ if (!nents)
+ return -EINVAL;
+
+ mxic_ecc_enable_engine(eng);
+
+ for (step = 0; step < eng->steps; step++) {
+ writel(sg_dma_address(&eng->sg[0]) + (step * eng->data_step_sz),
+ eng->regs + SDMA_MAIN_ADDR);
+ writel(sg_dma_address(&eng->sg[1]) + (step * (eng->oob_step_sz + STAT_BYTES)),
+ eng->regs + SDMA_SPARE_ADDR);
+ ret = mxic_ecc_process_data(eng);
+ if (ret)
+ break;
+ }
+
+ mxic_ecc_disable_engine(eng);
+
+ dma_unmap_sg(eng->dev, eng->sg, 2, DMA_BIDIRECTIONAL);
+
+ /* Extract the status bytes and reconstruct the buffer */
+ mxic_ecc_extract_status_bytes(eng, eng->oobwithstat);
+ mxic_ecc_reconstruct_oobbuf(eng, eng->req->oobbuf.in, eng->oobwithstat);
+
+ nand_ecc_restore_req(&eng->req_ctx, req);
+
+ return mxic_ecc_count_biterrs(eng, mtd);
+}
+
+static struct nand_ecc_engine_ops mxic_ecc_engine_external_ops = {
+ .init_ctx = mxic_ecc_init_ctx_external,
+ .cleanup_ctx = mxic_ecc_cleanup_ctx,
+ .prepare_io_req = mxic_ecc_prepare_io_req_external,
+ .finish_io_req = mxic_ecc_finish_io_req_external,
+};
+
+static int mxic_ecc_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct nand_ecc_engine *ecceng;
+
+ ecceng = devm_kzalloc(dev, sizeof(*ecceng), GFP_KERNEL);
+ if (!ecceng)
+ return -ENOMEM;
+
+ ecceng->dev = dev;
+ ecceng->ops = &mxic_ecc_engine_external_ops;
+ nand_ecc_register_on_host_hw_engine(ecceng);
+
+ return 0;
+}
+
+static int mxic_ecc_remove(struct platform_device *pdev)
+{
+ struct nand_ecc_engine *ecceng;
+
+ ecceng = nand_ecc_match_on_host_hw_engine(&pdev->dev);
+ if (ecceng)
+ nand_ecc_unregister_on_host_hw_engine(ecceng);
+
+ return 0;
+}
+
+static const struct of_device_id mxic_ecc_of_ids[] = {
+ {
+ .compatible = "mxic,nand-ecc-engine-rev3",
+ },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, mxic_ecc_of_ids);
+
+static struct platform_driver mxic_ecc_driver = {
+ .driver = {
+ .name = "mxic-nand-ecc-engine",
+ .of_match_table = mxic_ecc_of_ids,
+ },
+ .probe = mxic_ecc_probe,
+ .remove = mxic_ecc_remove,
+};
+module_platform_driver(mxic_ecc_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>");
+MODULE_DESCRIPTION("Macronix NAND hardware ECC controller");
--
2.27.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [RFC PATCH 06/10] mtd: nand: mxic-ecc: Add Macronix external ECC engine support
@ 2021-10-08 16:22 ` Miquel Raynal
0 siblings, 0 replies; 39+ messages in thread
From: Miquel Raynal @ 2021-10-08 16:22 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus, linux-mtd
Cc: Rob Herring, Mark Brown, Xiangsheng Hou, Boris Brezillon,
devicetree, linux-spi, linux-kernel, jaimeliao, juliensu,
Thomas Petazzoni, Miquel Raynal
Some SPI-NAND chips do not support on-die ECC. For these chips,
correction must apply on the SPI controller end. In order to avoid
doing all the calculations by software, Macronix provides a specific
engine that can offload the intensive work.
Add Macronix ECC engine support, this engine can work in conjunction
with a SPI controller and a raw NAND controller, it can be pipelined
or external and supports linear and syndrome layouts.
Right now the simplest configuration is supported: SPI controller
external and linear ECC engine.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/nand/Kconfig | 6 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/ecc-mxic.c | 655 ++++++++++++++++++++++++++++++++++++
3 files changed, 662 insertions(+)
create mode 100644 drivers/mtd/nand/ecc-mxic.c
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index b40455234cbd..8431292ff49d 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -46,6 +46,12 @@ config MTD_NAND_ECC_SW_BCH
ECC codes. They are used with NAND devices requiring more than 1 bit
of error correction.
+config MTD_NAND_ECC_MXIC
+ bool "Macronix external hardware ECC engine"
+ select MTD_NAND_ECC
+ help
+ This enables support for the hardware ECC engine from Macronix.
+
endmenu
endmenu
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 1c0b46960eb1..a4e6b7ae0614 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -10,3 +10,4 @@ obj-y += spi/
nandcore-$(CONFIG_MTD_NAND_ECC) += ecc.o
nandcore-$(CONFIG_MTD_NAND_ECC_SW_HAMMING) += ecc-sw-hamming.o
nandcore-$(CONFIG_MTD_NAND_ECC_SW_BCH) += ecc-sw-bch.o
+nandcore-$(CONFIG_MTD_NAND_ECC_MXIC) += ecc-mxic.o
diff --git a/drivers/mtd/nand/ecc-mxic.c b/drivers/mtd/nand/ecc-mxic.c
new file mode 100644
index 000000000000..8be816381f68
--- /dev/null
+++ b/drivers/mtd/nand/ecc-mxic.c
@@ -0,0 +1,655 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Support for Macronix external hardware ECC engine for NAND devices, also
+ * called DPE for Data Processing Engine.
+ *
+ * Copyright © 2019 Macronix
+ * Author: Miquel Raynal <miquel.raynal@bootlin.com>
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+/* DPE Configuration */
+#define DP_CONFIG 0x00
+#define ECC_EN BIT(0)
+#define ECC_TYP(idx) (((idx) << 3) & GENMASK(6, 3))
+/* DPE Interrupt Status */
+#define INTRPT_STS 0x04
+#define TRANS_CMPLT BIT(0)
+#define SDMA_MAIN BIT(1)
+#define SDMA_SPARE BIT(2)
+#define ECC_ERR BIT(3)
+#define TO_SPARE BIT(4)
+#define TO_MAIN BIT(5)
+/* DPE Interrupt Status Enable */
+#define INTRPT_STS_EN 0x08
+/* DPE Interrupt Signal Enable */
+#define INTRPT_SIG_EN 0x0C
+/* Host Controller Configuration */
+#define HC_CONFIG 0x10
+#define MEM2MEM BIT(4) /* TRANS_TYP_IO in the spec */
+#define ECC_PACKED 0 /* LAYOUT_TYP_INTEGRATED in the spec */
+#define ECC_INTERLEAVED BIT(2) /* LAYOUT_TYP_DISTRIBUTED in the spec */
+#define BURST_TYP_FIXED 0
+#define BURST_TYP_INCREASING BIT(0)
+/* Host Controller Slave Address */
+#define HC_SLV_ADDR 0x14
+/* ECC Chunk Size */
+#define CHUNK_SIZE 0x20
+/* Main Data Size */
+#define MAIN_SIZE 0x24
+/* Spare Data Size */
+#define SPARE_SIZE 0x28
+#define META_SZ(reg) ((reg) & GENMASK(7, 0))
+#define PARITY_SZ(reg) (((reg) & GENMASK(15, 8)) >> 8)
+#define RSV_SZ(reg) (((reg) & GENMASK(23, 16)) >> 16)
+#define SPARE_SZ(reg) ((reg) >> 24)
+/* ECC Chunk Count */
+#define CHUNK_CNT 0x30
+/* SDMA Control */
+#define SDMA_CTRL 0x40
+#define WRITE_NAND 0
+#define READ_NAND BIT(1)
+#define CONT_NAND BIT(29)
+#define CONT_SYSM BIT(30) /* Continue System Memory? */
+#define SDMA_STRT BIT(31)
+/* SDMA Address of Main Data */
+#define SDMA_MAIN_ADDR 0x44
+/* SDMA Address of Spare Data */
+#define SDMA_SPARE_ADDR 0x48
+/* DPE Version Number */
+#define DP_VER 0xD0
+#define DP_VER_OFFSET 16
+
+/* Status bytes between each chunk of spare data */
+#define STAT_BYTES 4
+#define NO_ERR 0x00
+#define MAX_CORR_ERR 0x28
+#define UNCORR_ERR 0xFE
+#define ERASED_CHUNK 0xFF
+
+struct mxic_ecc_engine {
+ struct device *dev;
+ void __iomem *regs;
+
+ /* ECC machinery */
+ unsigned int data_step_sz;
+ unsigned int oob_step_sz;
+ unsigned int parity_sz;
+ unsigned int meta_sz;
+ u8 *status;
+ int steps;
+
+ /* Completion boilerplate */
+ int irq;
+ struct completion complete;
+
+ /* DMA boilerplate */
+ struct nand_ecc_req_tweak_ctx req_ctx;
+ u8 *oobwithstat;
+ struct scatterlist sg[2];
+ struct nand_page_io_req *req;
+};
+
+static int mxic_ecc_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ struct nand_device *nand = mtd_to_nanddev(mtd);
+ struct mxic_ecc_engine *eng = nand->ecc.ctx.priv;
+
+ if (section < 0 || section >= eng->steps)
+ return -ERANGE;
+
+ oobregion->offset = (section * eng->oob_step_sz) + eng->meta_sz;
+ oobregion->length = eng->parity_sz;
+
+ return 0;
+}
+
+static int mxic_ecc_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ struct nand_device *nand = mtd_to_nanddev(mtd);
+ struct mxic_ecc_engine *eng = nand->ecc.ctx.priv;
+
+ if (section < 0 || section >= eng->steps)
+ return -ERANGE;
+
+ if (!section) {
+ oobregion->offset = 2;
+ oobregion->length = eng->meta_sz - 2;
+ } else {
+ oobregion->offset = section * eng->oob_step_sz;
+ oobregion->length = eng->meta_sz;
+ }
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops mxic_ecc_ooblayout_ops = {
+ .ecc = mxic_ecc_ooblayout_ecc,
+ .free = mxic_ecc_ooblayout_free,
+};
+
+static void mxic_ecc_disable_engine(struct mxic_ecc_engine *eng)
+{
+ u32 reg;
+
+ reg = readl(eng->regs + DP_CONFIG);
+ reg &= ~ECC_EN;
+ writel(reg, eng->regs + DP_CONFIG);
+}
+
+static void mxic_ecc_enable_engine(struct mxic_ecc_engine *eng)
+{
+ u32 reg;
+
+ reg = readl(eng->regs + DP_CONFIG);
+ reg |= ECC_EN;
+ writel(reg, eng->regs + DP_CONFIG);
+}
+
+static void mxic_ecc_disable_int(struct mxic_ecc_engine *eng)
+{
+ writel(0, eng->regs + INTRPT_SIG_EN);
+}
+
+static void mxic_ecc_enable_int(struct mxic_ecc_engine *eng)
+{
+ writel(TRANS_CMPLT, eng->regs + INTRPT_SIG_EN);
+}
+
+static irqreturn_t mxic_ecc_isr(int irq, void *dev_id)
+{
+ struct mxic_ecc_engine *eng = dev_id;
+ u32 sts;
+
+ sts = readl(eng->regs + INTRPT_STS);
+ if (!sts)
+ return IRQ_NONE;
+
+ if (sts & TRANS_CMPLT)
+ complete(&eng->complete);
+
+ writel(sts, eng->regs + INTRPT_STS);
+
+ return IRQ_HANDLED;
+}
+
+static int mxic_ecc_init_ctx(struct nand_device *nand, struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct nand_ecc_props *conf = &nand->ecc.ctx.conf;
+ struct nand_ecc_props *reqs = &nand->ecc.requirements;
+ struct nand_ecc_props *user = &nand->ecc.user_conf;
+ struct mtd_info *mtd = nanddev_to_mtd(nand);
+ struct mxic_ecc_engine *eng;
+ int step_size = 0, strength = 0, desired_correction = 0, steps, idx;
+ int possible_strength[] = {4, 8, 40, 48};
+ int spare_size[] = {32, 32, 96, 96};
+ u32 spare_reg;
+ int ret;
+
+ eng = devm_kzalloc(dev, sizeof(*eng), GFP_KERNEL);
+ if (!eng)
+ return -ENOMEM;
+
+ nand->ecc.ctx.priv = eng;
+ nand->ecc.engine->priv = eng;
+
+ eng->dev = dev;
+
+ /*
+ * Both memory regions for the ECC engine itself and the AXI slave
+ * address are mandatory.
+ */
+ eng->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(eng->regs)) {
+ dev_err(dev, "Missing memory region\n");
+ return PTR_ERR(eng->regs);
+ }
+
+ mxic_ecc_disable_engine(eng);
+ mxic_ecc_disable_int(eng);
+
+ /* IRQ is optional yet much more efficient */
+ eng->irq = platform_get_irq_byname(pdev, "ecc-engine");
+ if (eng->irq > 0) {
+ ret = devm_request_irq(dev, eng->irq, mxic_ecc_isr, 0,
+ "mxic-ecc", eng);
+ if (ret)
+ return ret;
+ } else {
+ dev_info(dev, "No ECC engine IRQ (%d), using polling\n",
+ eng->irq);
+ eng->irq = 0;
+ }
+
+ /* Only large page NAND chips may use BCH */
+ if (mtd->oobsize < 64) {
+ pr_err("BCH cannot be used with small page NAND chips\n");
+ return -EINVAL;
+ }
+
+ mtd_set_ooblayout(mtd, &mxic_ecc_ooblayout_ops);
+
+ /* Enable all status bits */
+ writel(TRANS_CMPLT | SDMA_MAIN | SDMA_SPARE | ECC_ERR |
+ TO_SPARE | TO_MAIN, eng->regs + INTRPT_STS_EN);
+
+ /* Configure the correction depending on the NAND device topology */
+ if (user->step_size && user->strength) {
+ step_size = user->step_size;
+ strength = user->strength;
+ } else if (reqs->step_size && reqs->strength) {
+ step_size = reqs->step_size;
+ strength = reqs->strength;
+ }
+
+ if (step_size && strength) {
+ steps = mtd->writesize / step_size;
+ desired_correction = steps * strength;
+ }
+
+ /* Step size is fixed to 1kiB, strength may vary (4 possible values) */
+ conf->step_size = SZ_1K;
+ steps = mtd->writesize / conf->step_size;
+
+ eng->status = devm_kzalloc(dev, steps * sizeof(u8), GFP_KERNEL);
+ if (!eng->status)
+ return -ENOMEM;
+
+ if (desired_correction) {
+ strength = desired_correction / steps;
+
+ for (idx = 0; idx < ARRAY_SIZE(possible_strength); idx++)
+ if (possible_strength[idx] >= strength)
+ break;
+
+ idx = min_t(unsigned int, idx,
+ ARRAY_SIZE(possible_strength) - 1);
+ } else {
+ /* Missing data, maximize the correction */
+ idx = ARRAY_SIZE(possible_strength) - 1;
+ }
+
+ /* Tune the selected strength until it fits in the OOB area */
+ for (; idx >= 0; idx--) {
+ if (spare_size[idx] * steps <= mtd->oobsize)
+ break;
+ }
+
+ /* This engine cannot be used with this NAND device */
+ if (idx < 0)
+ return -EINVAL;
+
+ /* Configure the engine for the desired strength */
+ writel(ECC_TYP(idx), eng->regs + DP_CONFIG);
+ conf->strength = possible_strength[idx];
+ spare_reg = readl(eng->regs + SPARE_SIZE);
+
+ eng->steps = steps;
+ eng->data_step_sz = mtd->writesize / steps;
+ eng->oob_step_sz = mtd->oobsize / steps;
+ eng->parity_sz = PARITY_SZ(spare_reg);
+ eng->meta_sz = META_SZ(spare_reg);
+
+ /* Ensure buffers will contain enough bytes to store the STAT_BYTES */
+ eng->req_ctx.oob_buffer_size = nanddev_per_page_oobsize(nand) +
+ (eng->steps * STAT_BYTES);
+ ret = nand_ecc_init_req_tweaking(&eng->req_ctx, nand);
+ if (ret)
+ return ret;
+
+ eng->oobwithstat = kmalloc(mtd->oobsize + (eng->steps * STAT_BYTES),
+ GFP_KERNEL);
+ if (!eng->oobwithstat) {
+ ret = -ENOMEM;
+ goto cleanup_req_tweak;
+ }
+
+ sg_init_table(eng->sg, 2);
+
+ /* Configuration dump and sanity checks */
+ dev_err(dev, "DPE version number: %d\n",
+ readl(eng->regs + DP_VER) >> DP_VER_OFFSET);
+ dev_err(dev, "Chunk size: %d\n", readl(eng->regs + CHUNK_SIZE));
+ dev_err(dev, "Main size: %d\n", readl(eng->regs + MAIN_SIZE));
+ dev_err(dev, "Spare size: %d\n", SPARE_SZ(spare_reg));
+ dev_err(dev, "Rsv size: %ld\n", RSV_SZ(spare_reg));
+ dev_err(dev, "Parity size: %d\n", eng->parity_sz);
+ dev_err(dev, "Meta size: %d\n", eng->meta_sz);
+
+ if (eng->meta_sz + eng->parity_sz + RSV_SZ(spare_reg) != SPARE_SZ(spare_reg)) {
+ dev_err(dev, "Wrong OOB configuration: %d + %d + %ld != %d\n",
+ eng->meta_sz, eng->parity_sz, RSV_SZ(spare_reg),
+ SPARE_SZ(spare_reg));
+ ret = -EINVAL;
+ goto free_oobwithstat;
+ }
+
+ if (eng->oob_step_sz != SPARE_SZ(spare_reg)) {
+ dev_err(dev, "Wrong OOB configuration: %d != %d\n",
+ eng->oob_step_sz, SPARE_SZ(spare_reg));
+ ret = -EINVAL;
+ goto free_oobwithstat;
+ }
+
+ return 0;
+
+free_oobwithstat:
+ kfree(eng->oobwithstat);
+cleanup_req_tweak:
+ nand_ecc_cleanup_req_tweaking(&eng->req_ctx);
+
+ return ret;
+}
+
+static int mxic_ecc_init_ctx_external(struct nand_device *nand)
+{
+ struct device *dev = nand->ecc.engine->dev;
+ struct mxic_ecc_engine *eng;
+ int ret;
+
+ dev_info(dev, "Macronix ECC engine in external mode\n");
+
+ ret = mxic_ecc_init_ctx(nand, dev);
+ if (ret)
+ return ret;
+
+ eng = nand->ecc.ctx.priv;
+
+ /* Trigger each step manually */
+ writel(1, eng->regs + CHUNK_CNT);
+ writel(BURST_TYP_INCREASING | ECC_PACKED | MEM2MEM,
+ eng->regs + HC_CONFIG);
+
+ return 0;
+}
+
+static void mxic_ecc_cleanup_ctx(struct nand_device *nand)
+{
+ struct mxic_ecc_engine *eng = nand->ecc.ctx.priv;
+
+ if (eng) {
+ nand_ecc_cleanup_req_tweaking(&eng->req_ctx);
+ kfree(eng->oobwithstat);
+ }
+}
+
+static int mxic_ecc_data_xfer_wait_for_completion(struct mxic_ecc_engine *eng)
+{
+ u32 val;
+ int ret;
+
+ if (eng->irq) {
+ init_completion(&eng->complete);
+ mxic_ecc_enable_int(eng);
+ ret = wait_for_completion_timeout(&eng->complete,
+ msecs_to_jiffies(1000));
+ mxic_ecc_disable_int(eng);
+ } else {
+ ret = readl_poll_timeout(eng->regs + INTRPT_STS, val,
+ val & TRANS_CMPLT, 10, USEC_PER_SEC);
+ writel(val, eng->regs + INTRPT_STS);
+ }
+
+ if (ret) {
+ dev_err(eng->dev, "Timeout on data xfer completion (sts 0x%08x)\n", val);
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static int mxic_ecc_process_data(struct mxic_ecc_engine *eng)
+{
+ /* Retrieve the direction */
+ unsigned int dir = (eng->req->type == NAND_PAGE_READ) ?
+ READ_NAND : WRITE_NAND;
+
+ /* Trigger processing */
+ writel(SDMA_STRT | dir, eng->regs + SDMA_CTRL);
+
+ /* Wait for completion */
+ return mxic_ecc_data_xfer_wait_for_completion(eng);
+}
+
+static void mxic_ecc_extract_status_bytes(struct mxic_ecc_engine *eng, u8 *buf)
+{
+ int next_stat_pos;
+ int step;
+
+ /* Extract the ECC status */
+ for (step = 0; step < eng->steps; step++) {
+ next_stat_pos = eng->oob_step_sz +
+ ((STAT_BYTES + eng->oob_step_sz) * step);
+
+ eng->status[step] = buf[next_stat_pos];
+ }
+}
+
+static void mxic_ecc_reconstruct_oobbuf(struct mxic_ecc_engine *eng,
+ u8 *dst, const u8 *src)
+{
+ int step;
+
+ /* Reconstruct the OOB buffer linearly (without the ECC status bytes) */
+ for (step = 0; step < eng->steps; step++)
+ memcpy(dst + (step * eng->oob_step_sz),
+ src + (step * (eng->oob_step_sz + STAT_BYTES)),
+ eng->oob_step_sz);
+}
+
+static void mxic_ecc_add_room_in_oobbuf(struct mxic_ecc_engine *eng,
+ u8 *dst, const u8 *src)
+{
+ int step;
+
+ /* Add some space in the OOB buffer for the status bytes */
+ for (step = 0; step < eng->steps; step++)
+ memcpy(dst + (step * (eng->oob_step_sz + STAT_BYTES)),
+ src + (step * eng->oob_step_sz),
+ eng->oob_step_sz);
+}
+
+static int mxic_ecc_count_biterrs(struct mxic_ecc_engine *eng, struct mtd_info *mtd)
+{
+ struct device *dev = eng->dev;
+ unsigned int max_bf = 0;
+ int step;
+
+ for (step = 0; step < eng->steps; step++) {
+ u8 stat = eng->status[step];
+
+ if (stat == NO_ERR) {
+ dev_dbg(dev, "ECC step %d: no error\n", step);
+ } else if (stat == ERASED_CHUNK) {
+ dev_dbg(dev, "ECC step %d: erased\n", step);
+ } else if (stat == UNCORR_ERR || stat > MAX_CORR_ERR) {
+ dev_dbg(dev, "ECC step %d: uncorrectable\n", step);
+ mtd->ecc_stats.failed++;
+ } else {
+ dev_dbg(dev, "ECC step %d: %d bits corrected\n",
+ step, stat);
+ max_bf = max_t(unsigned int, max_bf, stat);
+ mtd->ecc_stats.corrected += stat;
+ }
+ }
+
+ return max_bf;
+}
+
+/* External ECC engine helpers */
+static int mxic_ecc_prepare_io_req_external(struct nand_device *nand,
+ struct nand_page_io_req *req)
+{
+ struct mxic_ecc_engine *eng = nand->ecc.ctx.priv;
+ struct mtd_info *mtd = nanddev_to_mtd(nand);
+ int offset, nents, step, ret;
+
+ if (req->mode == MTD_OPS_RAW)
+ return 0;
+
+ nand_ecc_tweak_req(&eng->req_ctx, req);
+ eng->req = req;
+
+ if (req->type == NAND_PAGE_READ)
+ return 0;
+
+ mxic_ecc_add_room_in_oobbuf(eng, eng->oobwithstat, eng->req->oobbuf.out);
+
+ sg_set_buf(&eng->sg[0], req->databuf.out, req->datalen);
+ sg_set_buf(&eng->sg[1], eng->oobwithstat,
+ req->ooblen + (eng->steps * STAT_BYTES));
+
+ nents = dma_map_sg(eng->dev, eng->sg, 2, DMA_BIDIRECTIONAL);
+ if (!nents)
+ return -EINVAL;
+
+ mxic_ecc_enable_engine(eng);
+
+ for (step = 0; step < eng->steps; step++) {
+ writel(sg_dma_address(&eng->sg[0]) + (step * eng->data_step_sz),
+ eng->regs + SDMA_MAIN_ADDR);
+ writel(sg_dma_address(&eng->sg[1]) + (step * (eng->oob_step_sz + STAT_BYTES)),
+ eng->regs + SDMA_SPARE_ADDR);
+ ret = mxic_ecc_process_data(eng);
+ if (ret)
+ break;
+ }
+
+ mxic_ecc_disable_engine(eng);
+
+ dma_unmap_sg(eng->dev, eng->sg, 2, DMA_BIDIRECTIONAL);
+
+ /* Retrieve the calculated ECC bytes */
+ for (step = 0; step < eng->steps; step++) {
+ offset = eng->meta_sz + (step * eng->oob_step_sz);
+ mtd_ooblayout_get_eccbytes(mtd,
+ (u8 *)eng->req->oobbuf.out + offset,
+ eng->oobwithstat,
+ step * eng->parity_sz,
+ eng->parity_sz);
+ }
+
+ return ret;
+}
+
+static int mxic_ecc_finish_io_req_external(struct nand_device *nand,
+ struct nand_page_io_req *req)
+{
+ struct mxic_ecc_engine *eng = nand->ecc.ctx.priv;
+ struct mtd_info *mtd = nanddev_to_mtd(nand);
+ int nents, step, ret;
+
+ if (req->mode == MTD_OPS_RAW)
+ return 0;
+
+ if (req->type == NAND_PAGE_WRITE) {
+ nand_ecc_restore_req(&eng->req_ctx, req);
+ return 0;
+ }
+
+ /* Copy the OOB buffer and add room for the ECC engine status bytes */
+ mxic_ecc_add_room_in_oobbuf(eng, eng->oobwithstat, eng->req->oobbuf.in);
+
+ sg_set_buf(&eng->sg[0], req->databuf.in, req->datalen);
+ sg_set_buf(&eng->sg[1], eng->oobwithstat,
+ req->ooblen + (eng->steps * STAT_BYTES));
+ nents = dma_map_sg(eng->dev, eng->sg, 2, DMA_BIDIRECTIONAL);
+ if (!nents)
+ return -EINVAL;
+
+ mxic_ecc_enable_engine(eng);
+
+ for (step = 0; step < eng->steps; step++) {
+ writel(sg_dma_address(&eng->sg[0]) + (step * eng->data_step_sz),
+ eng->regs + SDMA_MAIN_ADDR);
+ writel(sg_dma_address(&eng->sg[1]) + (step * (eng->oob_step_sz + STAT_BYTES)),
+ eng->regs + SDMA_SPARE_ADDR);
+ ret = mxic_ecc_process_data(eng);
+ if (ret)
+ break;
+ }
+
+ mxic_ecc_disable_engine(eng);
+
+ dma_unmap_sg(eng->dev, eng->sg, 2, DMA_BIDIRECTIONAL);
+
+ /* Extract the status bytes and reconstruct the buffer */
+ mxic_ecc_extract_status_bytes(eng, eng->oobwithstat);
+ mxic_ecc_reconstruct_oobbuf(eng, eng->req->oobbuf.in, eng->oobwithstat);
+
+ nand_ecc_restore_req(&eng->req_ctx, req);
+
+ return mxic_ecc_count_biterrs(eng, mtd);
+}
+
+static struct nand_ecc_engine_ops mxic_ecc_engine_external_ops = {
+ .init_ctx = mxic_ecc_init_ctx_external,
+ .cleanup_ctx = mxic_ecc_cleanup_ctx,
+ .prepare_io_req = mxic_ecc_prepare_io_req_external,
+ .finish_io_req = mxic_ecc_finish_io_req_external,
+};
+
+static int mxic_ecc_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct nand_ecc_engine *ecceng;
+
+ ecceng = devm_kzalloc(dev, sizeof(*ecceng), GFP_KERNEL);
+ if (!ecceng)
+ return -ENOMEM;
+
+ ecceng->dev = dev;
+ ecceng->ops = &mxic_ecc_engine_external_ops;
+ nand_ecc_register_on_host_hw_engine(ecceng);
+
+ return 0;
+}
+
+static int mxic_ecc_remove(struct platform_device *pdev)
+{
+ struct nand_ecc_engine *ecceng;
+
+ ecceng = nand_ecc_match_on_host_hw_engine(&pdev->dev);
+ if (ecceng)
+ nand_ecc_unregister_on_host_hw_engine(ecceng);
+
+ return 0;
+}
+
+static const struct of_device_id mxic_ecc_of_ids[] = {
+ {
+ .compatible = "mxic,nand-ecc-engine-rev3",
+ },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, mxic_ecc_of_ids);
+
+static struct platform_driver mxic_ecc_driver = {
+ .driver = {
+ .name = "mxic-nand-ecc-engine",
+ .of_match_table = mxic_ecc_of_ids,
+ },
+ .probe = mxic_ecc_probe,
+ .remove = mxic_ecc_remove,
+};
+module_platform_driver(mxic_ecc_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>");
+MODULE_DESCRIPTION("Macronix NAND hardware ECC controller");
--
2.27.0
______________________________________________________
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^ permalink raw reply related [flat|nested] 39+ messages in thread
* [RFC PATCH 07/10] mtd: nand: mxic-ecc: Support SPI pipelined mode
2021-10-08 16:22 ` Miquel Raynal
@ 2021-10-08 16:22 ` Miquel Raynal
-1 siblings, 0 replies; 39+ messages in thread
From: Miquel Raynal @ 2021-10-08 16:22 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus, linux-mtd
Cc: Rob Herring, Mark Brown, Xiangsheng Hou, Boris Brezillon,
devicetree, linux-spi, linux-kernel, jaimeliao, juliensu,
Thomas Petazzoni, Miquel Raynal
Introduce the support for another possible configuration: the ECC
engine may work as DMA master (pipelined) and move itself the data
to/from the NAND chip into the buffer, applying the necessary
corrections/computations on the fly.
This driver offers an ECC engine implementation that must be
instatiated from a SPI controller driver.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/nand/ecc-mxic.c | 148 +++++++++++++++++++++++++++++-
include/linux/mtd/nand-ecc-mxic.h | 36 ++++++++
2 files changed, 181 insertions(+), 3 deletions(-)
create mode 100644 include/linux/mtd/nand-ecc-mxic.h
diff --git a/drivers/mtd/nand/ecc-mxic.c b/drivers/mtd/nand/ecc-mxic.c
index 8be816381f68..509e50a9136e 100644
--- a/drivers/mtd/nand/ecc-mxic.c
+++ b/drivers/mtd/nand/ecc-mxic.c
@@ -39,7 +39,9 @@
#define INTRPT_SIG_EN 0x0C
/* Host Controller Configuration */
#define HC_CONFIG 0x10
+#define DEV2MEM 0 /* TRANS_TYP_DMA in the spec */
#define MEM2MEM BIT(4) /* TRANS_TYP_IO in the spec */
+#define MAPPING BIT(5) /* TRANS_TYP_MAPPING in the spec */
#define ECC_PACKED 0 /* LAYOUT_TYP_INTEGRATED in the spec */
#define ECC_INTERLEAVED BIT(2) /* LAYOUT_TYP_DISTRIBUTED in the spec */
#define BURST_TYP_FIXED 0
@@ -101,6 +103,7 @@ struct mxic_ecc_engine {
u8 *oobwithstat;
struct scatterlist sg[2];
struct nand_page_io_req *req;
+ unsigned int pageoffs;
};
static int mxic_ecc_ooblayout_ecc(struct mtd_info *mtd, int section,
@@ -188,6 +191,31 @@ static irqreturn_t mxic_ecc_isr(int irq, void *dev_id)
return IRQ_HANDLED;
}
+static struct device *mxic_ecc_get_engine_dev(struct device *dev)
+{
+ struct platform_device *eccpdev;
+ struct device_node *np;
+
+ /*
+ * If the device node contains this property, it means the device does
+ * not represent the actual ECC engine.
+ */
+ np = of_parse_phandle(dev->of_node, "nand-ecc-engine", 0);
+ if (!np)
+ return dev;
+
+ eccpdev = of_find_device_by_node(np);
+ if (!eccpdev) {
+ of_node_put(np);
+ return NULL;
+ }
+
+ platform_device_put(eccpdev);
+ of_node_put(np);
+
+ return &eccpdev->dev;
+}
+
static int mxic_ecc_init_ctx(struct nand_device *nand, struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
@@ -379,6 +407,41 @@ static int mxic_ecc_init_ctx_external(struct nand_device *nand)
return 0;
}
+static int mxic_ecc_init_ctx_pipelined(struct nand_device *nand)
+{
+ struct mxic_ecc_engine *eng;
+ struct device *dev;
+ int ret;
+
+ /*
+ * In the case of a pipelined engine, the device registering the ECC
+ * engine is not the actual ECC engine device but the host controller.
+ */
+ dev = mxic_ecc_get_engine_dev(nand->ecc.engine->dev);
+ if (!dev)
+ return -EINVAL;
+
+ dev_info(dev, "Macronix ECC engine in pipelined/mapping mode\n");
+
+ ret = mxic_ecc_init_ctx(nand, dev);
+ if (ret)
+ return ret;
+
+ eng = nand->ecc.ctx.priv;
+
+ /* All steps should be handled in one go directly by the internal DMA */
+ writel(eng->steps, eng->regs + CHUNK_CNT);
+
+ /*
+ * Interleaved ECC scheme cannot be used otherwise factory bad block
+ * markers would be lost. A packed layout is mandatory.
+ */
+ writel(BURST_TYP_INCREASING | ECC_PACKED | MAPPING,
+ eng->regs + HC_CONFIG);
+
+ return 0;
+}
+
static void mxic_ecc_cleanup_ctx(struct nand_device *nand)
{
struct mxic_ecc_engine *eng = nand->ecc.ctx.priv;
@@ -414,18 +477,22 @@ static int mxic_ecc_data_xfer_wait_for_completion(struct mxic_ecc_engine *eng)
return 0;
}
-static int mxic_ecc_process_data(struct mxic_ecc_engine *eng)
+int mxic_ecc_process_data(struct mxic_ecc_engine *eng, dma_addr_t dirmap)
{
/* Retrieve the direction */
unsigned int dir = (eng->req->type == NAND_PAGE_READ) ?
READ_NAND : WRITE_NAND;
+ if (dirmap)
+ writel(dirmap, eng->regs + HC_SLV_ADDR);
+
/* Trigger processing */
writel(SDMA_STRT | dir, eng->regs + SDMA_CTRL);
/* Wait for completion */
return mxic_ecc_data_xfer_wait_for_completion(eng);
}
+EXPORT_SYMBOL_GPL(mxic_ecc_process_data);
static void mxic_ecc_extract_status_bytes(struct mxic_ecc_engine *eng, u8 *buf)
{
@@ -526,7 +593,7 @@ static int mxic_ecc_prepare_io_req_external(struct nand_device *nand,
eng->regs + SDMA_MAIN_ADDR);
writel(sg_dma_address(&eng->sg[1]) + (step * (eng->oob_step_sz + STAT_BYTES)),
eng->regs + SDMA_SPARE_ADDR);
- ret = mxic_ecc_process_data(eng);
+ ret = mxic_ecc_process_data(eng, 0);
if (ret)
break;
}
@@ -580,7 +647,7 @@ static int mxic_ecc_finish_io_req_external(struct nand_device *nand,
eng->regs + SDMA_MAIN_ADDR);
writel(sg_dma_address(&eng->sg[1]) + (step * (eng->oob_step_sz + STAT_BYTES)),
eng->regs + SDMA_SPARE_ADDR);
- ret = mxic_ecc_process_data(eng);
+ ret = mxic_ecc_process_data(eng, 0);
if (ret)
break;
}
@@ -598,6 +665,64 @@ static int mxic_ecc_finish_io_req_external(struct nand_device *nand,
return mxic_ecc_count_biterrs(eng, mtd);
}
+/* Pipelined ECC engine helpers */
+static int mxic_ecc_prepare_io_req_pipelined(struct nand_device *nand,
+ struct nand_page_io_req *req)
+{
+ struct mxic_ecc_engine *eng = nand->ecc.ctx.priv;
+ int nents;
+
+ if (req->mode == MTD_OPS_RAW)
+ return 0;
+
+ nand_ecc_tweak_req(&eng->req_ctx, req);
+ eng->req = req;
+
+ /* Copy the OOB buffer and add room for the ECC engine status bytes */
+ mxic_ecc_add_room_in_oobbuf(eng, eng->oobwithstat, eng->req->oobbuf.in);
+
+ sg_set_buf(&eng->sg[0], req->databuf.in, req->datalen);
+ sg_set_buf(&eng->sg[1], eng->oobwithstat,
+ req->ooblen + (eng->steps * STAT_BYTES));
+
+ nents = dma_map_sg(eng->dev, eng->sg, 2, DMA_BIDIRECTIONAL);
+ if (!nents)
+ return -EINVAL;
+
+ writel(sg_dma_address(&eng->sg[0]), eng->regs + SDMA_MAIN_ADDR);
+ writel(sg_dma_address(&eng->sg[1]), eng->regs + SDMA_SPARE_ADDR);
+
+ mxic_ecc_enable_engine(eng);
+
+ return 0;
+}
+
+static int mxic_ecc_finish_io_req_pipelined(struct nand_device *nand,
+ struct nand_page_io_req *req)
+{
+ struct mxic_ecc_engine *eng = nand->ecc.ctx.priv;
+ struct mtd_info *mtd = nanddev_to_mtd(nand);
+ int ret = 0;
+
+ if (req->mode == MTD_OPS_RAW)
+ return 0;
+
+ mxic_ecc_disable_engine(eng);
+
+ dma_unmap_sg(eng->dev, eng->sg, 2, DMA_BIDIRECTIONAL);
+
+ if (req->type == NAND_PAGE_READ) {
+ mxic_ecc_extract_status_bytes(eng, eng->oobwithstat);
+ mxic_ecc_reconstruct_oobbuf(eng, eng->req->oobbuf.in,
+ eng->oobwithstat);
+ ret = mxic_ecc_count_biterrs(eng, mtd);
+ }
+
+ nand_ecc_restore_req(&eng->req_ctx, req);
+
+ return ret;
+}
+
static struct nand_ecc_engine_ops mxic_ecc_engine_external_ops = {
.init_ctx = mxic_ecc_init_ctx_external,
.cleanup_ctx = mxic_ecc_cleanup_ctx,
@@ -605,6 +730,23 @@ static struct nand_ecc_engine_ops mxic_ecc_engine_external_ops = {
.finish_io_req = mxic_ecc_finish_io_req_external,
};
+static struct nand_ecc_engine_ops mxic_ecc_engine_pipelined_ops = {
+ .init_ctx = mxic_ecc_init_ctx_pipelined,
+ .cleanup_ctx = mxic_ecc_cleanup_ctx,
+ .prepare_io_req = mxic_ecc_prepare_io_req_pipelined,
+ .finish_io_req = mxic_ecc_finish_io_req_pipelined,
+};
+
+struct nand_ecc_engine_ops *mxic_ecc_get_pipelined_ops(void)
+{
+ return &mxic_ecc_engine_pipelined_ops;
+}
+EXPORT_SYMBOL_GPL(mxic_ecc_get_pipelined_ops);
+
+/*
+ * Only the external ECC engine is exported as the pipelined is SoC specific, so
+ * it is registered directly by the drivers that wrap it.
+ */
static int mxic_ecc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
diff --git a/include/linux/mtd/nand-ecc-mxic.h b/include/linux/mtd/nand-ecc-mxic.h
new file mode 100644
index 000000000000..d48b7fe05644
--- /dev/null
+++ b/include/linux/mtd/nand-ecc-mxic.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright © 2019 Macronix
+ * Author: Miquèl Raynal <miquel.raynal@bootlin.com>
+ *
+ * Header for the Macronix external ECC engine.
+ */
+
+#ifndef __MTD_NAND_ECC_MXIC_H__
+#define __MTD_NAND_ECC_MXIC_H__
+
+#include <linux/device.h>
+
+struct mxic_ecc_engine;
+
+#if IS_ENABLED(CONFIG_MTD_NAND_ECC_MXIC)
+
+struct nand_ecc_engine_ops *mxic_ecc_get_pipelined_ops(void);
+int mxic_ecc_process_data(struct mxic_ecc_engine *eng, dma_addr_t dirmap);
+
+#else /* !CONFIG_MTD_NAND_ECC_MXIC */
+
+struct nand_ecc_engine_ops *mxic_ecc_get_pipelined_ops(void)
+{
+ return NULL;
+}
+
+static inline
+int mxic_ecc_process_data(struct mxic_ecc_engine *eng, dma_addr_t dirmap)
+{
+ return -ENOTSUPP;
+}
+
+#endif /* CONFIG_MTD_NAND_ECC_MXIC */
+
+#endif /* __MTD_NAND_ECC_MXIC_H__ */
--
2.27.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [RFC PATCH 07/10] mtd: nand: mxic-ecc: Support SPI pipelined mode
@ 2021-10-08 16:22 ` Miquel Raynal
0 siblings, 0 replies; 39+ messages in thread
From: Miquel Raynal @ 2021-10-08 16:22 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus, linux-mtd
Cc: Rob Herring, Mark Brown, Xiangsheng Hou, Boris Brezillon,
devicetree, linux-spi, linux-kernel, jaimeliao, juliensu,
Thomas Petazzoni, Miquel Raynal
Introduce the support for another possible configuration: the ECC
engine may work as DMA master (pipelined) and move itself the data
to/from the NAND chip into the buffer, applying the necessary
corrections/computations on the fly.
This driver offers an ECC engine implementation that must be
instatiated from a SPI controller driver.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/nand/ecc-mxic.c | 148 +++++++++++++++++++++++++++++-
include/linux/mtd/nand-ecc-mxic.h | 36 ++++++++
2 files changed, 181 insertions(+), 3 deletions(-)
create mode 100644 include/linux/mtd/nand-ecc-mxic.h
diff --git a/drivers/mtd/nand/ecc-mxic.c b/drivers/mtd/nand/ecc-mxic.c
index 8be816381f68..509e50a9136e 100644
--- a/drivers/mtd/nand/ecc-mxic.c
+++ b/drivers/mtd/nand/ecc-mxic.c
@@ -39,7 +39,9 @@
#define INTRPT_SIG_EN 0x0C
/* Host Controller Configuration */
#define HC_CONFIG 0x10
+#define DEV2MEM 0 /* TRANS_TYP_DMA in the spec */
#define MEM2MEM BIT(4) /* TRANS_TYP_IO in the spec */
+#define MAPPING BIT(5) /* TRANS_TYP_MAPPING in the spec */
#define ECC_PACKED 0 /* LAYOUT_TYP_INTEGRATED in the spec */
#define ECC_INTERLEAVED BIT(2) /* LAYOUT_TYP_DISTRIBUTED in the spec */
#define BURST_TYP_FIXED 0
@@ -101,6 +103,7 @@ struct mxic_ecc_engine {
u8 *oobwithstat;
struct scatterlist sg[2];
struct nand_page_io_req *req;
+ unsigned int pageoffs;
};
static int mxic_ecc_ooblayout_ecc(struct mtd_info *mtd, int section,
@@ -188,6 +191,31 @@ static irqreturn_t mxic_ecc_isr(int irq, void *dev_id)
return IRQ_HANDLED;
}
+static struct device *mxic_ecc_get_engine_dev(struct device *dev)
+{
+ struct platform_device *eccpdev;
+ struct device_node *np;
+
+ /*
+ * If the device node contains this property, it means the device does
+ * not represent the actual ECC engine.
+ */
+ np = of_parse_phandle(dev->of_node, "nand-ecc-engine", 0);
+ if (!np)
+ return dev;
+
+ eccpdev = of_find_device_by_node(np);
+ if (!eccpdev) {
+ of_node_put(np);
+ return NULL;
+ }
+
+ platform_device_put(eccpdev);
+ of_node_put(np);
+
+ return &eccpdev->dev;
+}
+
static int mxic_ecc_init_ctx(struct nand_device *nand, struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
@@ -379,6 +407,41 @@ static int mxic_ecc_init_ctx_external(struct nand_device *nand)
return 0;
}
+static int mxic_ecc_init_ctx_pipelined(struct nand_device *nand)
+{
+ struct mxic_ecc_engine *eng;
+ struct device *dev;
+ int ret;
+
+ /*
+ * In the case of a pipelined engine, the device registering the ECC
+ * engine is not the actual ECC engine device but the host controller.
+ */
+ dev = mxic_ecc_get_engine_dev(nand->ecc.engine->dev);
+ if (!dev)
+ return -EINVAL;
+
+ dev_info(dev, "Macronix ECC engine in pipelined/mapping mode\n");
+
+ ret = mxic_ecc_init_ctx(nand, dev);
+ if (ret)
+ return ret;
+
+ eng = nand->ecc.ctx.priv;
+
+ /* All steps should be handled in one go directly by the internal DMA */
+ writel(eng->steps, eng->regs + CHUNK_CNT);
+
+ /*
+ * Interleaved ECC scheme cannot be used otherwise factory bad block
+ * markers would be lost. A packed layout is mandatory.
+ */
+ writel(BURST_TYP_INCREASING | ECC_PACKED | MAPPING,
+ eng->regs + HC_CONFIG);
+
+ return 0;
+}
+
static void mxic_ecc_cleanup_ctx(struct nand_device *nand)
{
struct mxic_ecc_engine *eng = nand->ecc.ctx.priv;
@@ -414,18 +477,22 @@ static int mxic_ecc_data_xfer_wait_for_completion(struct mxic_ecc_engine *eng)
return 0;
}
-static int mxic_ecc_process_data(struct mxic_ecc_engine *eng)
+int mxic_ecc_process_data(struct mxic_ecc_engine *eng, dma_addr_t dirmap)
{
/* Retrieve the direction */
unsigned int dir = (eng->req->type == NAND_PAGE_READ) ?
READ_NAND : WRITE_NAND;
+ if (dirmap)
+ writel(dirmap, eng->regs + HC_SLV_ADDR);
+
/* Trigger processing */
writel(SDMA_STRT | dir, eng->regs + SDMA_CTRL);
/* Wait for completion */
return mxic_ecc_data_xfer_wait_for_completion(eng);
}
+EXPORT_SYMBOL_GPL(mxic_ecc_process_data);
static void mxic_ecc_extract_status_bytes(struct mxic_ecc_engine *eng, u8 *buf)
{
@@ -526,7 +593,7 @@ static int mxic_ecc_prepare_io_req_external(struct nand_device *nand,
eng->regs + SDMA_MAIN_ADDR);
writel(sg_dma_address(&eng->sg[1]) + (step * (eng->oob_step_sz + STAT_BYTES)),
eng->regs + SDMA_SPARE_ADDR);
- ret = mxic_ecc_process_data(eng);
+ ret = mxic_ecc_process_data(eng, 0);
if (ret)
break;
}
@@ -580,7 +647,7 @@ static int mxic_ecc_finish_io_req_external(struct nand_device *nand,
eng->regs + SDMA_MAIN_ADDR);
writel(sg_dma_address(&eng->sg[1]) + (step * (eng->oob_step_sz + STAT_BYTES)),
eng->regs + SDMA_SPARE_ADDR);
- ret = mxic_ecc_process_data(eng);
+ ret = mxic_ecc_process_data(eng, 0);
if (ret)
break;
}
@@ -598,6 +665,64 @@ static int mxic_ecc_finish_io_req_external(struct nand_device *nand,
return mxic_ecc_count_biterrs(eng, mtd);
}
+/* Pipelined ECC engine helpers */
+static int mxic_ecc_prepare_io_req_pipelined(struct nand_device *nand,
+ struct nand_page_io_req *req)
+{
+ struct mxic_ecc_engine *eng = nand->ecc.ctx.priv;
+ int nents;
+
+ if (req->mode == MTD_OPS_RAW)
+ return 0;
+
+ nand_ecc_tweak_req(&eng->req_ctx, req);
+ eng->req = req;
+
+ /* Copy the OOB buffer and add room for the ECC engine status bytes */
+ mxic_ecc_add_room_in_oobbuf(eng, eng->oobwithstat, eng->req->oobbuf.in);
+
+ sg_set_buf(&eng->sg[0], req->databuf.in, req->datalen);
+ sg_set_buf(&eng->sg[1], eng->oobwithstat,
+ req->ooblen + (eng->steps * STAT_BYTES));
+
+ nents = dma_map_sg(eng->dev, eng->sg, 2, DMA_BIDIRECTIONAL);
+ if (!nents)
+ return -EINVAL;
+
+ writel(sg_dma_address(&eng->sg[0]), eng->regs + SDMA_MAIN_ADDR);
+ writel(sg_dma_address(&eng->sg[1]), eng->regs + SDMA_SPARE_ADDR);
+
+ mxic_ecc_enable_engine(eng);
+
+ return 0;
+}
+
+static int mxic_ecc_finish_io_req_pipelined(struct nand_device *nand,
+ struct nand_page_io_req *req)
+{
+ struct mxic_ecc_engine *eng = nand->ecc.ctx.priv;
+ struct mtd_info *mtd = nanddev_to_mtd(nand);
+ int ret = 0;
+
+ if (req->mode == MTD_OPS_RAW)
+ return 0;
+
+ mxic_ecc_disable_engine(eng);
+
+ dma_unmap_sg(eng->dev, eng->sg, 2, DMA_BIDIRECTIONAL);
+
+ if (req->type == NAND_PAGE_READ) {
+ mxic_ecc_extract_status_bytes(eng, eng->oobwithstat);
+ mxic_ecc_reconstruct_oobbuf(eng, eng->req->oobbuf.in,
+ eng->oobwithstat);
+ ret = mxic_ecc_count_biterrs(eng, mtd);
+ }
+
+ nand_ecc_restore_req(&eng->req_ctx, req);
+
+ return ret;
+}
+
static struct nand_ecc_engine_ops mxic_ecc_engine_external_ops = {
.init_ctx = mxic_ecc_init_ctx_external,
.cleanup_ctx = mxic_ecc_cleanup_ctx,
@@ -605,6 +730,23 @@ static struct nand_ecc_engine_ops mxic_ecc_engine_external_ops = {
.finish_io_req = mxic_ecc_finish_io_req_external,
};
+static struct nand_ecc_engine_ops mxic_ecc_engine_pipelined_ops = {
+ .init_ctx = mxic_ecc_init_ctx_pipelined,
+ .cleanup_ctx = mxic_ecc_cleanup_ctx,
+ .prepare_io_req = mxic_ecc_prepare_io_req_pipelined,
+ .finish_io_req = mxic_ecc_finish_io_req_pipelined,
+};
+
+struct nand_ecc_engine_ops *mxic_ecc_get_pipelined_ops(void)
+{
+ return &mxic_ecc_engine_pipelined_ops;
+}
+EXPORT_SYMBOL_GPL(mxic_ecc_get_pipelined_ops);
+
+/*
+ * Only the external ECC engine is exported as the pipelined is SoC specific, so
+ * it is registered directly by the drivers that wrap it.
+ */
static int mxic_ecc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
diff --git a/include/linux/mtd/nand-ecc-mxic.h b/include/linux/mtd/nand-ecc-mxic.h
new file mode 100644
index 000000000000..d48b7fe05644
--- /dev/null
+++ b/include/linux/mtd/nand-ecc-mxic.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright © 2019 Macronix
+ * Author: Miquèl Raynal <miquel.raynal@bootlin.com>
+ *
+ * Header for the Macronix external ECC engine.
+ */
+
+#ifndef __MTD_NAND_ECC_MXIC_H__
+#define __MTD_NAND_ECC_MXIC_H__
+
+#include <linux/device.h>
+
+struct mxic_ecc_engine;
+
+#if IS_ENABLED(CONFIG_MTD_NAND_ECC_MXIC)
+
+struct nand_ecc_engine_ops *mxic_ecc_get_pipelined_ops(void);
+int mxic_ecc_process_data(struct mxic_ecc_engine *eng, dma_addr_t dirmap);
+
+#else /* !CONFIG_MTD_NAND_ECC_MXIC */
+
+struct nand_ecc_engine_ops *mxic_ecc_get_pipelined_ops(void)
+{
+ return NULL;
+}
+
+static inline
+int mxic_ecc_process_data(struct mxic_ecc_engine *eng, dma_addr_t dirmap)
+{
+ return -ENOTSUPP;
+}
+
+#endif /* CONFIG_MTD_NAND_ECC_MXIC */
+
+#endif /* __MTD_NAND_ECC_MXIC_H__ */
--
2.27.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [RFC PATCH 08/10] spi: mxic: Fix the transmit path
2021-10-08 16:22 ` Miquel Raynal
@ 2021-10-08 16:22 ` Miquel Raynal
-1 siblings, 0 replies; 39+ messages in thread
From: Miquel Raynal @ 2021-10-08 16:22 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus, linux-mtd
Cc: Rob Herring, Mark Brown, Xiangsheng Hou, Boris Brezillon,
devicetree, linux-spi, linux-kernel, jaimeliao, juliensu,
Thomas Petazzoni, Miquel Raynal, stable, Mason Yang
By working with external hardware ECC engines, we figured out that
Under certain circumstances, it is needed for the SPI controller to
check INT_TX_EMPTY and INT_RX_NOT_EMPTY in both receive and transmit
path (not only in the receive path). The delay penalty being
negligible, move this code in the common path.
Fixes: b942d80b0a39 ("spi: Add MXIC controller driver")
Cc: stable@vger.kernel.org
Suggested-by: Mason Yang <masonccyang@mxic.com.tw>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/spi/spi-mxic.c | 28 ++++++++++++----------------
1 file changed, 12 insertions(+), 16 deletions(-)
diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
index 96b418293bf2..4fb19e6f94b0 100644
--- a/drivers/spi/spi-mxic.c
+++ b/drivers/spi/spi-mxic.c
@@ -304,25 +304,21 @@ static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf,
writel(data, mxic->regs + TXD(nbytes % 4));
+ ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
+ sts & INT_TX_EMPTY, 0, USEC_PER_SEC);
+ if (ret)
+ return ret;
+
+ ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
+ sts & INT_RX_NOT_EMPTY, 0,
+ USEC_PER_SEC);
+ if (ret)
+ return ret;
+
+ data = readl(mxic->regs + RXD);
if (rxbuf) {
- ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
- sts & INT_TX_EMPTY, 0,
- USEC_PER_SEC);
- if (ret)
- return ret;
-
- ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
- sts & INT_RX_NOT_EMPTY, 0,
- USEC_PER_SEC);
- if (ret)
- return ret;
-
- data = readl(mxic->regs + RXD);
data >>= (8 * (4 - nbytes));
memcpy(rxbuf + pos, &data, nbytes);
- WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY);
- } else {
- readl(mxic->regs + RXD);
}
WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY);
--
2.27.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [RFC PATCH 08/10] spi: mxic: Fix the transmit path
@ 2021-10-08 16:22 ` Miquel Raynal
0 siblings, 0 replies; 39+ messages in thread
From: Miquel Raynal @ 2021-10-08 16:22 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus, linux-mtd
Cc: Rob Herring, Mark Brown, Xiangsheng Hou, Boris Brezillon,
devicetree, linux-spi, linux-kernel, jaimeliao, juliensu,
Thomas Petazzoni, Miquel Raynal, stable, Mason Yang
By working with external hardware ECC engines, we figured out that
Under certain circumstances, it is needed for the SPI controller to
check INT_TX_EMPTY and INT_RX_NOT_EMPTY in both receive and transmit
path (not only in the receive path). The delay penalty being
negligible, move this code in the common path.
Fixes: b942d80b0a39 ("spi: Add MXIC controller driver")
Cc: stable@vger.kernel.org
Suggested-by: Mason Yang <masonccyang@mxic.com.tw>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/spi/spi-mxic.c | 28 ++++++++++++----------------
1 file changed, 12 insertions(+), 16 deletions(-)
diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
index 96b418293bf2..4fb19e6f94b0 100644
--- a/drivers/spi/spi-mxic.c
+++ b/drivers/spi/spi-mxic.c
@@ -304,25 +304,21 @@ static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf,
writel(data, mxic->regs + TXD(nbytes % 4));
+ ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
+ sts & INT_TX_EMPTY, 0, USEC_PER_SEC);
+ if (ret)
+ return ret;
+
+ ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
+ sts & INT_RX_NOT_EMPTY, 0,
+ USEC_PER_SEC);
+ if (ret)
+ return ret;
+
+ data = readl(mxic->regs + RXD);
if (rxbuf) {
- ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
- sts & INT_TX_EMPTY, 0,
- USEC_PER_SEC);
- if (ret)
- return ret;
-
- ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
- sts & INT_RX_NOT_EMPTY, 0,
- USEC_PER_SEC);
- if (ret)
- return ret;
-
- data = readl(mxic->regs + RXD);
data >>= (8 * (4 - nbytes));
memcpy(rxbuf + pos, &data, nbytes);
- WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY);
- } else {
- readl(mxic->regs + RXD);
}
WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY);
--
2.27.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [RFC PATCH 09/10] spi: mxic: Add support for direct mapping
2021-10-08 16:22 ` Miquel Raynal
@ 2021-10-08 16:22 ` Miquel Raynal
-1 siblings, 0 replies; 39+ messages in thread
From: Miquel Raynal @ 2021-10-08 16:22 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus, linux-mtd
Cc: Rob Herring, Mark Brown, Xiangsheng Hou, Boris Brezillon,
devicetree, linux-spi, linux-kernel, jaimeliao, juliensu,
Thomas Petazzoni, Miquel Raynal
Implement the ->dirmap_create() and ->dirmap_read/write() hooks to
provide a fast path for read and write accesses.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/spi/spi-mxic.c | 171 ++++++++++++++++++++++++++++++++++-------
1 file changed, 144 insertions(+), 27 deletions(-)
diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
index 4fb19e6f94b0..e10c55ee4d06 100644
--- a/drivers/spi/spi-mxic.c
+++ b/drivers/spi/spi-mxic.c
@@ -172,6 +172,11 @@ struct mxic_spi {
struct clk *send_dly_clk;
void __iomem *regs;
u32 cur_speed_hz;
+ struct {
+ void __iomem *map;
+ dma_addr_t dma;
+ size_t size;
+ } linear;
};
static int mxic_spi_clk_enable(struct mxic_spi *mxic)
@@ -280,6 +285,42 @@ static void mxic_spi_hw_init(struct mxic_spi *mxic)
mxic->regs + HC_CFG);
}
+static u32 mxic_spi_mem_prep_op_cfg(const struct spi_mem_op *op)
+{
+ u32 cfg = OP_CMD_BYTES(1) | OP_CMD_BUSW(fls(op->cmd.buswidth) - 1);
+
+ if (op->addr.nbytes)
+ cfg |= OP_ADDR_BYTES(op->addr.nbytes) |
+ OP_ADDR_BUSW(fls(op->addr.buswidth) - 1);
+
+ if (op->dummy.nbytes)
+ cfg |= OP_DUMMY_CYC(op->dummy.nbytes);
+
+ if (op->data.dir != SPI_MEM_NO_DATA) {
+ cfg |= OP_DATA_BUSW(fls(op->data.buswidth) - 1);
+ if (op->data.dir == SPI_MEM_DATA_IN)
+ cfg |= OP_READ;
+ }
+
+ return cfg;
+}
+
+static void mxic_spi_set_hc_cfg(struct spi_device *spi, u32 flags)
+{
+ struct mxic_spi *mxic = spi_master_get_devdata(spi->master);
+ int nio = 1;
+
+ if (spi->mode & (SPI_TX_QUAD | SPI_RX_QUAD))
+ nio = 4;
+ else if (spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL))
+ nio = 2;
+
+ writel(flags | HC_CFG_NIO(nio) |
+ HC_CFG_TYPE(spi->chip_select, HC_CFG_TYPE_SPI_NOR) |
+ HC_CFG_SLV_ACT(spi->chip_select) | HC_CFG_IDLE_SIO_LVL(1),
+ mxic->regs + HC_CFG);
+}
+
static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf,
void *rxbuf, unsigned int len)
{
@@ -328,6 +369,77 @@ static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf,
return 0;
}
+static ssize_t mxic_spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc,
+ u64 offs, size_t len, void *buf)
+{
+ struct mxic_spi *mxic = spi_master_get_devdata(desc->mem->spi->master);
+ int ret;
+ u32 sts;
+
+ if (WARN_ON(offs + desc->info.offset + len > U32_MAX))
+ return -EINVAL;
+
+ mxic_spi_set_hc_cfg(desc->mem->spi, 0);
+
+ writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) |
+ LMODE_SLV_ACT(desc->mem->spi->chip_select) |
+ LMODE_EN,
+ mxic->regs + LRD_CTRL);
+ writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl),
+ mxic->regs + LRD_CFG);
+ writel(desc->info.offset + offs, mxic->regs + LRD_ADDR);
+ len = min_t(size_t, len, mxic->linear.size);
+ writel(len, mxic->regs + LRD_RANGE);
+
+ memcpy_fromio(buf, mxic->linear.map, len);
+
+ writel(INT_LRD_DIS, mxic->regs + INT_STS);
+ writel(0, mxic->regs + LRD_CTRL);
+
+ ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
+ sts & INT_LRD_DIS, 0, USEC_PER_SEC);
+ if (ret)
+ return ret;
+
+ return len;
+}
+
+static ssize_t mxic_spi_mem_dirmap_write(struct spi_mem_dirmap_desc *desc,
+ u64 offs, size_t len,
+ const void *buf)
+{
+ struct mxic_spi *mxic = spi_master_get_devdata(desc->mem->spi->master);
+ u32 sts;
+ int ret;
+
+ if (WARN_ON(offs + desc->info.offset + len > U32_MAX))
+ return -EINVAL;
+
+ mxic_spi_set_hc_cfg(desc->mem->spi, 0);
+
+ writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) |
+ LMODE_SLV_ACT(desc->mem->spi->chip_select) |
+ LMODE_EN,
+ mxic->regs + LWR_CTRL);
+ writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl),
+ mxic->regs + LWR_CFG);
+ writel(desc->info.offset + offs, mxic->regs + LWR_ADDR);
+ len = min_t(size_t, len, mxic->linear.size);
+ writel(len, mxic->regs + LWR_RANGE);
+
+ memcpy_toio(mxic->linear.map, buf, len);
+
+ writel(INT_LWR_DIS, mxic->regs + INT_STS);
+ writel(0, mxic->regs + LWR_CTRL);
+
+ ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
+ sts & INT_LWR_DIS, 0, USEC_PER_SEC);
+ if (ret)
+ return ret;
+
+ return len;
+}
+
static bool mxic_spi_mem_supports_op(struct spi_mem *mem,
const struct spi_mem_op *op)
{
@@ -345,12 +457,27 @@ static bool mxic_spi_mem_supports_op(struct spi_mem *mem,
return spi_mem_default_supports_op(mem, op);
}
+static int mxic_spi_mem_dirmap_create(struct spi_mem_dirmap_desc *desc)
+{
+ struct mxic_spi *mxic = spi_master_get_devdata(desc->mem->spi->master);
+
+ if (!mxic->linear.map)
+ return -ENOTSUPP;
+
+ if (desc->info.offset + desc->info.length > U32_MAX)
+ return -ENOTSUPP;
+
+ if (!mxic_spi_mem_supports_op(desc->mem, &desc->info.op_tmpl))
+ return -ENOTSUPP;
+
+ return 0;
+}
+
static int mxic_spi_mem_exec_op(struct spi_mem *mem,
const struct spi_mem_op *op)
{
struct mxic_spi *mxic = spi_master_get_devdata(mem->spi->master);
- int nio = 1, i, ret;
- u32 ss_ctrl;
+ int i, ret;
u8 addr[8];
u8 opcode = op->cmd.opcode;
@@ -358,34 +485,12 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,
if (ret)
return ret;
- if (mem->spi->mode & (SPI_TX_QUAD | SPI_RX_QUAD))
- nio = 4;
- else if (mem->spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL))
- nio = 2;
+ mxic_spi_set_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN);
- writel(HC_CFG_NIO(nio) |
- HC_CFG_TYPE(mem->spi->chip_select, HC_CFG_TYPE_SPI_NOR) |
- HC_CFG_SLV_ACT(mem->spi->chip_select) | HC_CFG_IDLE_SIO_LVL(1) |
- HC_CFG_MAN_CS_EN,
- mxic->regs + HC_CFG);
writel(HC_EN_BIT, mxic->regs + HC_EN);
- ss_ctrl = OP_CMD_BYTES(1) | OP_CMD_BUSW(fls(op->cmd.buswidth) - 1);
-
- if (op->addr.nbytes)
- ss_ctrl |= OP_ADDR_BYTES(op->addr.nbytes) |
- OP_ADDR_BUSW(fls(op->addr.buswidth) - 1);
-
- if (op->dummy.nbytes)
- ss_ctrl |= OP_DUMMY_CYC(op->dummy.nbytes);
-
- if (op->data.nbytes) {
- ss_ctrl |= OP_DATA_BUSW(fls(op->data.buswidth) - 1);
- if (op->data.dir == SPI_MEM_DATA_IN)
- ss_ctrl |= OP_READ;
- }
-
- writel(ss_ctrl, mxic->regs + SS_CTRL(mem->spi->chip_select));
+ writel(mxic_spi_mem_prep_op_cfg(op),
+ mxic->regs + SS_CTRL(mem->spi->chip_select));
writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
mxic->regs + HC_CFG);
@@ -423,6 +528,9 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,
static const struct spi_controller_mem_ops mxic_spi_mem_ops = {
.supports_op = mxic_spi_mem_supports_op,
.exec_op = mxic_spi_mem_exec_op,
+ .dirmap_create = mxic_spi_mem_dirmap_create,
+ .dirmap_read = mxic_spi_mem_dirmap_read,
+ .dirmap_write = mxic_spi_mem_dirmap_write,
};
static void mxic_spi_set_cs(struct spi_device *spi, bool lvl)
@@ -552,6 +660,15 @@ static int mxic_spi_probe(struct platform_device *pdev)
if (IS_ERR(mxic->regs))
return PTR_ERR(mxic->regs);
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap");
+ mxic->linear.map = devm_ioremap_resource(&pdev->dev, res);
+ if (!IS_ERR(mxic->linear.map)) {
+ mxic->linear.dma = res->start;
+ mxic->linear.size = resource_size(res);
+ } else {
+ mxic->linear.map = NULL;
+ }
+
pm_runtime_enable(&pdev->dev);
master->auto_runtime_pm = true;
--
2.27.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [RFC PATCH 09/10] spi: mxic: Add support for direct mapping
@ 2021-10-08 16:22 ` Miquel Raynal
0 siblings, 0 replies; 39+ messages in thread
From: Miquel Raynal @ 2021-10-08 16:22 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus, linux-mtd
Cc: Rob Herring, Mark Brown, Xiangsheng Hou, Boris Brezillon,
devicetree, linux-spi, linux-kernel, jaimeliao, juliensu,
Thomas Petazzoni, Miquel Raynal
Implement the ->dirmap_create() and ->dirmap_read/write() hooks to
provide a fast path for read and write accesses.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/spi/spi-mxic.c | 171 ++++++++++++++++++++++++++++++++++-------
1 file changed, 144 insertions(+), 27 deletions(-)
diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
index 4fb19e6f94b0..e10c55ee4d06 100644
--- a/drivers/spi/spi-mxic.c
+++ b/drivers/spi/spi-mxic.c
@@ -172,6 +172,11 @@ struct mxic_spi {
struct clk *send_dly_clk;
void __iomem *regs;
u32 cur_speed_hz;
+ struct {
+ void __iomem *map;
+ dma_addr_t dma;
+ size_t size;
+ } linear;
};
static int mxic_spi_clk_enable(struct mxic_spi *mxic)
@@ -280,6 +285,42 @@ static void mxic_spi_hw_init(struct mxic_spi *mxic)
mxic->regs + HC_CFG);
}
+static u32 mxic_spi_mem_prep_op_cfg(const struct spi_mem_op *op)
+{
+ u32 cfg = OP_CMD_BYTES(1) | OP_CMD_BUSW(fls(op->cmd.buswidth) - 1);
+
+ if (op->addr.nbytes)
+ cfg |= OP_ADDR_BYTES(op->addr.nbytes) |
+ OP_ADDR_BUSW(fls(op->addr.buswidth) - 1);
+
+ if (op->dummy.nbytes)
+ cfg |= OP_DUMMY_CYC(op->dummy.nbytes);
+
+ if (op->data.dir != SPI_MEM_NO_DATA) {
+ cfg |= OP_DATA_BUSW(fls(op->data.buswidth) - 1);
+ if (op->data.dir == SPI_MEM_DATA_IN)
+ cfg |= OP_READ;
+ }
+
+ return cfg;
+}
+
+static void mxic_spi_set_hc_cfg(struct spi_device *spi, u32 flags)
+{
+ struct mxic_spi *mxic = spi_master_get_devdata(spi->master);
+ int nio = 1;
+
+ if (spi->mode & (SPI_TX_QUAD | SPI_RX_QUAD))
+ nio = 4;
+ else if (spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL))
+ nio = 2;
+
+ writel(flags | HC_CFG_NIO(nio) |
+ HC_CFG_TYPE(spi->chip_select, HC_CFG_TYPE_SPI_NOR) |
+ HC_CFG_SLV_ACT(spi->chip_select) | HC_CFG_IDLE_SIO_LVL(1),
+ mxic->regs + HC_CFG);
+}
+
static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf,
void *rxbuf, unsigned int len)
{
@@ -328,6 +369,77 @@ static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf,
return 0;
}
+static ssize_t mxic_spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc,
+ u64 offs, size_t len, void *buf)
+{
+ struct mxic_spi *mxic = spi_master_get_devdata(desc->mem->spi->master);
+ int ret;
+ u32 sts;
+
+ if (WARN_ON(offs + desc->info.offset + len > U32_MAX))
+ return -EINVAL;
+
+ mxic_spi_set_hc_cfg(desc->mem->spi, 0);
+
+ writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) |
+ LMODE_SLV_ACT(desc->mem->spi->chip_select) |
+ LMODE_EN,
+ mxic->regs + LRD_CTRL);
+ writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl),
+ mxic->regs + LRD_CFG);
+ writel(desc->info.offset + offs, mxic->regs + LRD_ADDR);
+ len = min_t(size_t, len, mxic->linear.size);
+ writel(len, mxic->regs + LRD_RANGE);
+
+ memcpy_fromio(buf, mxic->linear.map, len);
+
+ writel(INT_LRD_DIS, mxic->regs + INT_STS);
+ writel(0, mxic->regs + LRD_CTRL);
+
+ ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
+ sts & INT_LRD_DIS, 0, USEC_PER_SEC);
+ if (ret)
+ return ret;
+
+ return len;
+}
+
+static ssize_t mxic_spi_mem_dirmap_write(struct spi_mem_dirmap_desc *desc,
+ u64 offs, size_t len,
+ const void *buf)
+{
+ struct mxic_spi *mxic = spi_master_get_devdata(desc->mem->spi->master);
+ u32 sts;
+ int ret;
+
+ if (WARN_ON(offs + desc->info.offset + len > U32_MAX))
+ return -EINVAL;
+
+ mxic_spi_set_hc_cfg(desc->mem->spi, 0);
+
+ writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) |
+ LMODE_SLV_ACT(desc->mem->spi->chip_select) |
+ LMODE_EN,
+ mxic->regs + LWR_CTRL);
+ writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl),
+ mxic->regs + LWR_CFG);
+ writel(desc->info.offset + offs, mxic->regs + LWR_ADDR);
+ len = min_t(size_t, len, mxic->linear.size);
+ writel(len, mxic->regs + LWR_RANGE);
+
+ memcpy_toio(mxic->linear.map, buf, len);
+
+ writel(INT_LWR_DIS, mxic->regs + INT_STS);
+ writel(0, mxic->regs + LWR_CTRL);
+
+ ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
+ sts & INT_LWR_DIS, 0, USEC_PER_SEC);
+ if (ret)
+ return ret;
+
+ return len;
+}
+
static bool mxic_spi_mem_supports_op(struct spi_mem *mem,
const struct spi_mem_op *op)
{
@@ -345,12 +457,27 @@ static bool mxic_spi_mem_supports_op(struct spi_mem *mem,
return spi_mem_default_supports_op(mem, op);
}
+static int mxic_spi_mem_dirmap_create(struct spi_mem_dirmap_desc *desc)
+{
+ struct mxic_spi *mxic = spi_master_get_devdata(desc->mem->spi->master);
+
+ if (!mxic->linear.map)
+ return -ENOTSUPP;
+
+ if (desc->info.offset + desc->info.length > U32_MAX)
+ return -ENOTSUPP;
+
+ if (!mxic_spi_mem_supports_op(desc->mem, &desc->info.op_tmpl))
+ return -ENOTSUPP;
+
+ return 0;
+}
+
static int mxic_spi_mem_exec_op(struct spi_mem *mem,
const struct spi_mem_op *op)
{
struct mxic_spi *mxic = spi_master_get_devdata(mem->spi->master);
- int nio = 1, i, ret;
- u32 ss_ctrl;
+ int i, ret;
u8 addr[8];
u8 opcode = op->cmd.opcode;
@@ -358,34 +485,12 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,
if (ret)
return ret;
- if (mem->spi->mode & (SPI_TX_QUAD | SPI_RX_QUAD))
- nio = 4;
- else if (mem->spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL))
- nio = 2;
+ mxic_spi_set_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN);
- writel(HC_CFG_NIO(nio) |
- HC_CFG_TYPE(mem->spi->chip_select, HC_CFG_TYPE_SPI_NOR) |
- HC_CFG_SLV_ACT(mem->spi->chip_select) | HC_CFG_IDLE_SIO_LVL(1) |
- HC_CFG_MAN_CS_EN,
- mxic->regs + HC_CFG);
writel(HC_EN_BIT, mxic->regs + HC_EN);
- ss_ctrl = OP_CMD_BYTES(1) | OP_CMD_BUSW(fls(op->cmd.buswidth) - 1);
-
- if (op->addr.nbytes)
- ss_ctrl |= OP_ADDR_BYTES(op->addr.nbytes) |
- OP_ADDR_BUSW(fls(op->addr.buswidth) - 1);
-
- if (op->dummy.nbytes)
- ss_ctrl |= OP_DUMMY_CYC(op->dummy.nbytes);
-
- if (op->data.nbytes) {
- ss_ctrl |= OP_DATA_BUSW(fls(op->data.buswidth) - 1);
- if (op->data.dir == SPI_MEM_DATA_IN)
- ss_ctrl |= OP_READ;
- }
-
- writel(ss_ctrl, mxic->regs + SS_CTRL(mem->spi->chip_select));
+ writel(mxic_spi_mem_prep_op_cfg(op),
+ mxic->regs + SS_CTRL(mem->spi->chip_select));
writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
mxic->regs + HC_CFG);
@@ -423,6 +528,9 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,
static const struct spi_controller_mem_ops mxic_spi_mem_ops = {
.supports_op = mxic_spi_mem_supports_op,
.exec_op = mxic_spi_mem_exec_op,
+ .dirmap_create = mxic_spi_mem_dirmap_create,
+ .dirmap_read = mxic_spi_mem_dirmap_read,
+ .dirmap_write = mxic_spi_mem_dirmap_write,
};
static void mxic_spi_set_cs(struct spi_device *spi, bool lvl)
@@ -552,6 +660,15 @@ static int mxic_spi_probe(struct platform_device *pdev)
if (IS_ERR(mxic->regs))
return PTR_ERR(mxic->regs);
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap");
+ mxic->linear.map = devm_ioremap_resource(&pdev->dev, res);
+ if (!IS_ERR(mxic->linear.map)) {
+ mxic->linear.dma = res->start;
+ mxic->linear.size = resource_size(res);
+ } else {
+ mxic->linear.map = NULL;
+ }
+
pm_runtime_enable(&pdev->dev);
master->auto_runtime_pm = true;
--
2.27.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [RFC PATCH 10/10] spi: mxic: Add support for pipelined ECC operations
2021-10-08 16:22 ` Miquel Raynal
@ 2021-10-08 16:22 ` Miquel Raynal
-1 siblings, 0 replies; 39+ messages in thread
From: Miquel Raynal @ 2021-10-08 16:22 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus, linux-mtd
Cc: Rob Herring, Mark Brown, Xiangsheng Hou, Boris Brezillon,
devicetree, linux-spi, linux-kernel, jaimeliao, juliensu,
Thomas Petazzoni, Miquel Raynal
Some SPI-NAND chips do not have a proper on-die ECC engine providing
error correction/detection. This is particularly an issue on embedded
devices with limited resources because all the computations must
happen in software, unless an external hardware engine is provided.
These external engines are new and can be of two categories: external
or pipelined. Macronix is providing both, the former being already
supported. The second, however, is very SoC implementation dependent
and must be instantiated by the SPI host controller directly.
An entire subsystem has been contributed to support these engines which
makes the insertion into another subsystem such as SPI quite
straightforward without the need for a lot of specific functions.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/spi/spi-mxic.c | 114 ++++++++++++++++++++++++++++++++++++++++-
1 file changed, 112 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
index e10c55ee4d06..9481d1685faf 100644
--- a/drivers/spi/spi-mxic.c
+++ b/drivers/spi/spi-mxic.c
@@ -12,6 +12,8 @@
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/module.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand-ecc-mxic.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/spi/spi.h>
@@ -167,6 +169,7 @@
#define HW_TEST(x) (0xe0 + ((x) * 4))
struct mxic_spi {
+ struct device *dev;
struct clk *ps_clk;
struct clk *send_clk;
struct clk *send_dly_clk;
@@ -177,6 +180,10 @@ struct mxic_spi {
dma_addr_t dma;
size_t size;
} linear;
+ struct {
+ struct nand_ecc_engine *engine;
+ bool enabled;
+ } ecc;
};
static int mxic_spi_clk_enable(struct mxic_spi *mxic)
@@ -369,6 +376,13 @@ static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf,
return 0;
}
+static struct mxic_ecc_engine *mxic_spi_to_ecc_engine(struct mxic_spi *mxic)
+{
+ struct nand_ecc_engine *ecc_engine = mxic->ecc.engine;
+
+ return ecc_engine->priv;
+}
+
static ssize_t mxic_spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc,
u64 offs, size_t len, void *buf)
{
@@ -391,7 +405,14 @@ static ssize_t mxic_spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc,
len = min_t(size_t, len, mxic->linear.size);
writel(len, mxic->regs + LRD_RANGE);
- memcpy_fromio(buf, mxic->linear.map, len);
+ if (mxic->ecc.enabled) {
+ ret = mxic_ecc_process_data(mxic_spi_to_ecc_engine(mxic),
+ mxic->linear.dma + offs);
+ if (ret)
+ return ret;
+ } else {
+ memcpy_fromio(buf, mxic->linear.map, len);
+ }
writel(INT_LRD_DIS, mxic->regs + INT_STS);
writel(0, mxic->regs + LRD_CTRL);
@@ -427,7 +448,14 @@ static ssize_t mxic_spi_mem_dirmap_write(struct spi_mem_dirmap_desc *desc,
len = min_t(size_t, len, mxic->linear.size);
writel(len, mxic->regs + LWR_RANGE);
- memcpy_toio(mxic->linear.map, buf, len);
+ if (mxic->ecc.enabled) {
+ ret = mxic_ecc_process_data(mxic_spi_to_ecc_engine(mxic),
+ mxic->linear.dma + offs);
+ if (ret)
+ return ret;
+ } else {
+ memcpy_toio(mxic->linear.map, buf, len);
+ }
writel(INT_LWR_DIS, mxic->regs + INT_STS);
writel(0, mxic->regs + LWR_CTRL);
@@ -595,6 +623,80 @@ static int mxic_spi_transfer_one(struct spi_master *master,
return 0;
}
+/* ECC wrapper */
+static int mxic_spi_mem_ecc_init_ctx(struct nand_device *nand)
+{
+ struct nand_ecc_engine_ops *ops = mxic_ecc_get_pipelined_ops();
+
+ return ops->init_ctx(nand);
+}
+
+static void mxic_spi_mem_ecc_cleanup_ctx(struct nand_device *nand)
+{
+ struct nand_ecc_engine_ops *ops = mxic_ecc_get_pipelined_ops();
+
+ ops->cleanup_ctx(nand);
+}
+
+static struct mxic_spi *mxic_nand_to_spi(struct nand_device *nand)
+{
+ struct device *dev = nand->ecc.engine->dev;
+ struct spi_master *master = dev_get_drvdata(dev);
+ struct mxic_spi *mxic = spi_master_get_devdata(master);
+
+ return mxic;
+}
+
+static int mxic_spi_mem_ecc_prepare_io_req(struct nand_device *nand,
+ struct nand_page_io_req *req)
+{
+ struct nand_ecc_engine_ops *ops = mxic_ecc_get_pipelined_ops();
+ struct mxic_spi *mxic = mxic_nand_to_spi(nand);
+
+ mxic->ecc.enabled = (req->mode != MTD_OPS_RAW);
+
+ return ops->prepare_io_req(nand, req);
+}
+
+static int mxic_spi_mem_ecc_finish_io_req(struct nand_device *nand,
+ struct nand_page_io_req *req)
+{
+ struct nand_ecc_engine_ops *ops = mxic_ecc_get_pipelined_ops();
+ struct mxic_spi *mxic = mxic_nand_to_spi(nand);
+
+ mxic->ecc.enabled = false;
+
+ return ops->finish_io_req(nand, req);
+}
+
+static struct nand_ecc_engine_ops mxic_spi_mem_ecc_engine_pipelined_ops = {
+ .init_ctx = mxic_spi_mem_ecc_init_ctx,
+ .cleanup_ctx = mxic_spi_mem_ecc_cleanup_ctx,
+ .prepare_io_req = mxic_spi_mem_ecc_prepare_io_req,
+ .finish_io_req = mxic_spi_mem_ecc_finish_io_req,
+};
+
+static int mxic_spi_mem_ecc_probe(struct platform_device *pdev,
+ struct mxic_spi *mxic)
+{
+ struct nand_ecc_engine *ecceng;
+
+ if (!mxic_ecc_get_pipelined_ops())
+ return -EOPNOTSUPP;
+
+ ecceng = devm_kzalloc(&pdev->dev, sizeof(*ecceng), GFP_KERNEL);
+ if (!ecceng)
+ return -ENOMEM;
+
+ ecceng->dev = &pdev->dev;
+ ecceng->ops = &mxic_spi_mem_ecc_engine_pipelined_ops;
+
+ nand_ecc_register_on_host_hw_engine(ecceng);
+ mxic->ecc.engine = ecceng;
+
+ return 0;
+}
+
static int __maybe_unused mxic_spi_runtime_suspend(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
@@ -640,6 +742,7 @@ static int mxic_spi_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, master);
mxic = spi_master_get_devdata(master);
+ mxic->dev = &pdev->dev;
master->dev.of_node = pdev->dev.of_node;
@@ -684,6 +787,10 @@ static int mxic_spi_probe(struct platform_device *pdev)
mxic_spi_hw_init(mxic);
+ ret = mxic_spi_mem_ecc_probe(pdev, mxic);
+ if (ret)
+ dev_warn(&pdev->dev, "SPI-mem ECC engine not available\n");
+
ret = spi_register_master(master);
if (ret) {
dev_err(&pdev->dev, "spi_register_master failed\n");
@@ -696,8 +803,11 @@ static int mxic_spi_probe(struct platform_device *pdev)
static int mxic_spi_remove(struct platform_device *pdev)
{
struct spi_master *master = platform_get_drvdata(pdev);
+ struct mxic_spi *mxic = spi_master_get_devdata(master);
+ struct nand_ecc_engine *ecc_engine = mxic->ecc.engine;
pm_runtime_disable(&pdev->dev);
+ nand_ecc_unregister_on_host_hw_engine(ecc_engine);
spi_unregister_master(master);
return 0;
--
2.27.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [RFC PATCH 10/10] spi: mxic: Add support for pipelined ECC operations
@ 2021-10-08 16:22 ` Miquel Raynal
0 siblings, 0 replies; 39+ messages in thread
From: Miquel Raynal @ 2021-10-08 16:22 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus, linux-mtd
Cc: Rob Herring, Mark Brown, Xiangsheng Hou, Boris Brezillon,
devicetree, linux-spi, linux-kernel, jaimeliao, juliensu,
Thomas Petazzoni, Miquel Raynal
Some SPI-NAND chips do not have a proper on-die ECC engine providing
error correction/detection. This is particularly an issue on embedded
devices with limited resources because all the computations must
happen in software, unless an external hardware engine is provided.
These external engines are new and can be of two categories: external
or pipelined. Macronix is providing both, the former being already
supported. The second, however, is very SoC implementation dependent
and must be instantiated by the SPI host controller directly.
An entire subsystem has been contributed to support these engines which
makes the insertion into another subsystem such as SPI quite
straightforward without the need for a lot of specific functions.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/spi/spi-mxic.c | 114 ++++++++++++++++++++++++++++++++++++++++-
1 file changed, 112 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
index e10c55ee4d06..9481d1685faf 100644
--- a/drivers/spi/spi-mxic.c
+++ b/drivers/spi/spi-mxic.c
@@ -12,6 +12,8 @@
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/module.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand-ecc-mxic.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/spi/spi.h>
@@ -167,6 +169,7 @@
#define HW_TEST(x) (0xe0 + ((x) * 4))
struct mxic_spi {
+ struct device *dev;
struct clk *ps_clk;
struct clk *send_clk;
struct clk *send_dly_clk;
@@ -177,6 +180,10 @@ struct mxic_spi {
dma_addr_t dma;
size_t size;
} linear;
+ struct {
+ struct nand_ecc_engine *engine;
+ bool enabled;
+ } ecc;
};
static int mxic_spi_clk_enable(struct mxic_spi *mxic)
@@ -369,6 +376,13 @@ static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf,
return 0;
}
+static struct mxic_ecc_engine *mxic_spi_to_ecc_engine(struct mxic_spi *mxic)
+{
+ struct nand_ecc_engine *ecc_engine = mxic->ecc.engine;
+
+ return ecc_engine->priv;
+}
+
static ssize_t mxic_spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc,
u64 offs, size_t len, void *buf)
{
@@ -391,7 +405,14 @@ static ssize_t mxic_spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc,
len = min_t(size_t, len, mxic->linear.size);
writel(len, mxic->regs + LRD_RANGE);
- memcpy_fromio(buf, mxic->linear.map, len);
+ if (mxic->ecc.enabled) {
+ ret = mxic_ecc_process_data(mxic_spi_to_ecc_engine(mxic),
+ mxic->linear.dma + offs);
+ if (ret)
+ return ret;
+ } else {
+ memcpy_fromio(buf, mxic->linear.map, len);
+ }
writel(INT_LRD_DIS, mxic->regs + INT_STS);
writel(0, mxic->regs + LRD_CTRL);
@@ -427,7 +448,14 @@ static ssize_t mxic_spi_mem_dirmap_write(struct spi_mem_dirmap_desc *desc,
len = min_t(size_t, len, mxic->linear.size);
writel(len, mxic->regs + LWR_RANGE);
- memcpy_toio(mxic->linear.map, buf, len);
+ if (mxic->ecc.enabled) {
+ ret = mxic_ecc_process_data(mxic_spi_to_ecc_engine(mxic),
+ mxic->linear.dma + offs);
+ if (ret)
+ return ret;
+ } else {
+ memcpy_toio(mxic->linear.map, buf, len);
+ }
writel(INT_LWR_DIS, mxic->regs + INT_STS);
writel(0, mxic->regs + LWR_CTRL);
@@ -595,6 +623,80 @@ static int mxic_spi_transfer_one(struct spi_master *master,
return 0;
}
+/* ECC wrapper */
+static int mxic_spi_mem_ecc_init_ctx(struct nand_device *nand)
+{
+ struct nand_ecc_engine_ops *ops = mxic_ecc_get_pipelined_ops();
+
+ return ops->init_ctx(nand);
+}
+
+static void mxic_spi_mem_ecc_cleanup_ctx(struct nand_device *nand)
+{
+ struct nand_ecc_engine_ops *ops = mxic_ecc_get_pipelined_ops();
+
+ ops->cleanup_ctx(nand);
+}
+
+static struct mxic_spi *mxic_nand_to_spi(struct nand_device *nand)
+{
+ struct device *dev = nand->ecc.engine->dev;
+ struct spi_master *master = dev_get_drvdata(dev);
+ struct mxic_spi *mxic = spi_master_get_devdata(master);
+
+ return mxic;
+}
+
+static int mxic_spi_mem_ecc_prepare_io_req(struct nand_device *nand,
+ struct nand_page_io_req *req)
+{
+ struct nand_ecc_engine_ops *ops = mxic_ecc_get_pipelined_ops();
+ struct mxic_spi *mxic = mxic_nand_to_spi(nand);
+
+ mxic->ecc.enabled = (req->mode != MTD_OPS_RAW);
+
+ return ops->prepare_io_req(nand, req);
+}
+
+static int mxic_spi_mem_ecc_finish_io_req(struct nand_device *nand,
+ struct nand_page_io_req *req)
+{
+ struct nand_ecc_engine_ops *ops = mxic_ecc_get_pipelined_ops();
+ struct mxic_spi *mxic = mxic_nand_to_spi(nand);
+
+ mxic->ecc.enabled = false;
+
+ return ops->finish_io_req(nand, req);
+}
+
+static struct nand_ecc_engine_ops mxic_spi_mem_ecc_engine_pipelined_ops = {
+ .init_ctx = mxic_spi_mem_ecc_init_ctx,
+ .cleanup_ctx = mxic_spi_mem_ecc_cleanup_ctx,
+ .prepare_io_req = mxic_spi_mem_ecc_prepare_io_req,
+ .finish_io_req = mxic_spi_mem_ecc_finish_io_req,
+};
+
+static int mxic_spi_mem_ecc_probe(struct platform_device *pdev,
+ struct mxic_spi *mxic)
+{
+ struct nand_ecc_engine *ecceng;
+
+ if (!mxic_ecc_get_pipelined_ops())
+ return -EOPNOTSUPP;
+
+ ecceng = devm_kzalloc(&pdev->dev, sizeof(*ecceng), GFP_KERNEL);
+ if (!ecceng)
+ return -ENOMEM;
+
+ ecceng->dev = &pdev->dev;
+ ecceng->ops = &mxic_spi_mem_ecc_engine_pipelined_ops;
+
+ nand_ecc_register_on_host_hw_engine(ecceng);
+ mxic->ecc.engine = ecceng;
+
+ return 0;
+}
+
static int __maybe_unused mxic_spi_runtime_suspend(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
@@ -640,6 +742,7 @@ static int mxic_spi_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, master);
mxic = spi_master_get_devdata(master);
+ mxic->dev = &pdev->dev;
master->dev.of_node = pdev->dev.of_node;
@@ -684,6 +787,10 @@ static int mxic_spi_probe(struct platform_device *pdev)
mxic_spi_hw_init(mxic);
+ ret = mxic_spi_mem_ecc_probe(pdev, mxic);
+ if (ret)
+ dev_warn(&pdev->dev, "SPI-mem ECC engine not available\n");
+
ret = spi_register_master(master);
if (ret) {
dev_err(&pdev->dev, "spi_register_master failed\n");
@@ -696,8 +803,11 @@ static int mxic_spi_probe(struct platform_device *pdev)
static int mxic_spi_remove(struct platform_device *pdev)
{
struct spi_master *master = platform_get_drvdata(pdev);
+ struct mxic_spi *mxic = spi_master_get_devdata(master);
+ struct nand_ecc_engine *ecc_engine = mxic->ecc.engine;
pm_runtime_disable(&pdev->dev);
+ nand_ecc_unregister_on_host_hw_engine(ecc_engine);
spi_unregister_master(master);
return 0;
--
2.27.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [RFC PATCH 04/10] dt-bindings: mtd: Describe Macronix NAND ECC engine
2021-10-08 16:22 ` Miquel Raynal
@ 2021-10-08 19:48 ` Rob Herring
-1 siblings, 0 replies; 39+ messages in thread
From: Rob Herring @ 2021-10-08 19:48 UTC (permalink / raw)
To: Miquel Raynal
Cc: Thomas Petazzoni, linux-spi, Vignesh Raghavendra,
Richard Weinberger, linux-mtd, devicetree, jaimeliao,
Rob Herring, juliensu, Xiangsheng Hou, linux-kernel, Mark Brown,
Tudor Ambarus, Boris Brezillon
On Fri, 08 Oct 2021 18:22:22 +0200, Miquel Raynal wrote:
> Describe Macronix NAND ECC engine. This engine may be used as an
> external engine or pipelined, both ways are shown in the examples.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
> .../bindings/mtd/mxic,nand-ecc-engine.yaml | 78 +++++++++++++++++++
> 1 file changed, 78 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mtd/mxic,nand-ecc-engine.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/mtd/mxic,nand-ecc-engine.example.dt.yaml:0:0: /example-0/spi@43c30000: failed to match any schema with compatible: ['mxicy,mx25f0a-spi']
Documentation/devicetree/bindings/mtd/mxic,nand-ecc-engine.example.dt.yaml:0:0: /example-0/spi@43c30000/flash@0: failed to match any schema with compatible: ['spi-nand']
Documentation/devicetree/bindings/mtd/mxic,nand-ecc-engine.example.dt.yaml:0:0: /example-1/spi@43c30000: failed to match any schema with compatible: ['mxicy,mx25f0a-spi']
Documentation/devicetree/bindings/mtd/mxic,nand-ecc-engine.example.dt.yaml:0:0: /example-1/spi@43c30000/flash@0: failed to match any schema with compatible: ['spi-nand']
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1538445
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC PATCH 04/10] dt-bindings: mtd: Describe Macronix NAND ECC engine
@ 2021-10-08 19:48 ` Rob Herring
0 siblings, 0 replies; 39+ messages in thread
From: Rob Herring @ 2021-10-08 19:48 UTC (permalink / raw)
To: Miquel Raynal
Cc: Thomas Petazzoni, linux-spi, Vignesh Raghavendra,
Richard Weinberger, linux-mtd, devicetree, jaimeliao,
Rob Herring, juliensu, Xiangsheng Hou, linux-kernel, Mark Brown,
Tudor Ambarus, Boris Brezillon
On Fri, 08 Oct 2021 18:22:22 +0200, Miquel Raynal wrote:
> Describe Macronix NAND ECC engine. This engine may be used as an
> external engine or pipelined, both ways are shown in the examples.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
> .../bindings/mtd/mxic,nand-ecc-engine.yaml | 78 +++++++++++++++++++
> 1 file changed, 78 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mtd/mxic,nand-ecc-engine.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/mtd/mxic,nand-ecc-engine.example.dt.yaml:0:0: /example-0/spi@43c30000: failed to match any schema with compatible: ['mxicy,mx25f0a-spi']
Documentation/devicetree/bindings/mtd/mxic,nand-ecc-engine.example.dt.yaml:0:0: /example-0/spi@43c30000/flash@0: failed to match any schema with compatible: ['spi-nand']
Documentation/devicetree/bindings/mtd/mxic,nand-ecc-engine.example.dt.yaml:0:0: /example-1/spi@43c30000: failed to match any schema with compatible: ['mxicy,mx25f0a-spi']
Documentation/devicetree/bindings/mtd/mxic,nand-ecc-engine.example.dt.yaml:0:0: /example-1/spi@43c30000/flash@0: failed to match any schema with compatible: ['spi-nand']
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1538445
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC PATCH 03/10] dt-bindings: vendor-prefixes: Update Macronix prefix
2021-10-08 16:22 ` Miquel Raynal
@ 2021-10-08 21:47 ` Rob Herring
-1 siblings, 0 replies; 39+ messages in thread
From: Rob Herring @ 2021-10-08 21:47 UTC (permalink / raw)
To: Miquel Raynal
Cc: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus,
linux-mtd, Mark Brown, Xiangsheng Hou, Boris Brezillon,
devicetree, linux-spi, linux-kernel, jaimeliao, juliensu,
Thomas Petazzoni
On Fri, Oct 08, 2021 at 06:22:21PM +0200, Miquel Raynal wrote:
> When looking at compatible prefixes, Macronix is sometimes referred as
> mxicy:
> - mxicy,mx25r1635f
> - mxicy,mx25u6435f
> - mxicy,mx25v8035f
> - mxicy,mx25f0a-spi
> and sometimes as mxic:
> - mxic,multi-itfc-v009-nand-controller
> - mxic,enable-randomizer-otp
>
> It looks like the more up-to-date way is mxic so declare this prefix and
> mark the other one as deprecated.
mxicy is more widely used with flash parts. There's not a single dts
file with 'mxic' which only seems to be some nand controller.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index b868cefc7c55..013a87850cd5 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -758,8 +758,11 @@ patternProperties:
> description: Mundo Reader S.L.
> "^murata,.*":
> description: Murata Manufacturing Co., Ltd.
> + "^mxic,.*":
> + description: Macronix International Co., Ltd.
> "^mxicy,.*":
> description: Macronix International Co., Ltd.
> + deprecated: true
> "^myir,.*":
> description: MYIR Tech Limited
> "^national,.*":
> --
> 2.27.0
>
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC PATCH 03/10] dt-bindings: vendor-prefixes: Update Macronix prefix
@ 2021-10-08 21:47 ` Rob Herring
0 siblings, 0 replies; 39+ messages in thread
From: Rob Herring @ 2021-10-08 21:47 UTC (permalink / raw)
To: Miquel Raynal
Cc: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus,
linux-mtd, Mark Brown, Xiangsheng Hou, Boris Brezillon,
devicetree, linux-spi, linux-kernel, jaimeliao, juliensu,
Thomas Petazzoni
On Fri, Oct 08, 2021 at 06:22:21PM +0200, Miquel Raynal wrote:
> When looking at compatible prefixes, Macronix is sometimes referred as
> mxicy:
> - mxicy,mx25r1635f
> - mxicy,mx25u6435f
> - mxicy,mx25v8035f
> - mxicy,mx25f0a-spi
> and sometimes as mxic:
> - mxic,multi-itfc-v009-nand-controller
> - mxic,enable-randomizer-otp
>
> It looks like the more up-to-date way is mxic so declare this prefix and
> mark the other one as deprecated.
mxicy is more widely used with flash parts. There's not a single dts
file with 'mxic' which only seems to be some nand controller.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index b868cefc7c55..013a87850cd5 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -758,8 +758,11 @@ patternProperties:
> description: Mundo Reader S.L.
> "^murata,.*":
> description: Murata Manufacturing Co., Ltd.
> + "^mxic,.*":
> + description: Macronix International Co., Ltd.
> "^mxicy,.*":
> description: Macronix International Co., Ltd.
> + deprecated: true
> "^myir,.*":
> description: MYIR Tech Limited
> "^national,.*":
> --
> 2.27.0
>
>
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 39+ messages in thread
* 回信: [RFC PATCH 09/10] spi: mxic: Add support for direct mapping
2021-10-08 16:22 ` Miquel Raynal
@ 2021-10-12 7:14 ` jaimeliao
-1 siblings, 0 replies; 39+ messages in thread
From: jaimeliao @ 2021-10-12 7:14 UTC (permalink / raw)
To: Miquel Raynal
Cc: Boris Brezillon, Mark Brown, devicetree, juliensu, linux-kernel,
linux-mtd, linux-spi, Miquel Raynal, Richard Weinberger,
Rob Herring, Thomas Petazzoni, Tudor Ambarus,
Vignesh Raghavendra, Xiangsheng Hou
Hi Miquel
ZhengxunLi have patch new mxic spi host controller before.
The patch name as below
spi: mxic: patch for octal DTR mode support
Please patch mxic ECC engine base on latest version.
Thanks
Jaime
> [RFC PATCH 09/10] spi: mxic: Add support for direct mapping
>
> Implement the ->dirmap_create() and ->dirmap_read/write() hooks to
> provide a fast path for read and write accesses.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
> drivers/spi/spi-mxic.c | 171 ++++++++++++++++++++++++++++++++++-------
> 1 file changed, 144 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
> index 4fb19e6f94b0..e10c55ee4d06 100644
> --- a/drivers/spi/spi-mxic.c
> +++ b/drivers/spi/spi-mxic.c
> @@ -172,6 +172,11 @@ struct mxic_spi {
> struct clk *send_dly_clk;
> void __iomem *regs;
> u32 cur_speed_hz;
> + struct {
> + void __iomem *map;
> + dma_addr_t dma;
> + size_t size;
> + } linear;
> };
>
> static int mxic_spi_clk_enable(struct mxic_spi *mxic)
> @@ -280,6 +285,42 @@ static void mxic_spi_hw_init(struct mxic_spi *mxic)
> mxic->regs + HC_CFG);
> }
>
> +static u32 mxic_spi_mem_prep_op_cfg(const struct spi_mem_op *op)
> +{
> + u32 cfg = OP_CMD_BYTES(1) | OP_CMD_BUSW(fls(op->cmd.buswidth) - 1);
> +
> + if (op->addr.nbytes)
> + cfg |= OP_ADDR_BYTES(op->addr.nbytes) |
> + OP_ADDR_BUSW(fls(op->addr.buswidth) - 1);
> +
> + if (op->dummy.nbytes)
> + cfg |= OP_DUMMY_CYC(op->dummy.nbytes);
> +
> + if (op->data.dir != SPI_MEM_NO_DATA) {
> + cfg |= OP_DATA_BUSW(fls(op->data.buswidth) - 1);
> + if (op->data.dir == SPI_MEM_DATA_IN)
> + cfg |= OP_READ;
> + }
> +
> + return cfg;
> +}
> +
> +static void mxic_spi_set_hc_cfg(struct spi_device *spi, u32 flags)
> +{
> + struct mxic_spi *mxic = spi_master_get_devdata(spi->master);
> + int nio = 1;
> +
> + if (spi->mode & (SPI_TX_QUAD | SPI_RX_QUAD))
> + nio = 4;
> + else if (spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL))
> + nio = 2;
> +
> + writel(flags | HC_CFG_NIO(nio) |
> + HC_CFG_TYPE(spi->chip_select, HC_CFG_TYPE_SPI_NOR) |
> + HC_CFG_SLV_ACT(spi->chip_select) | HC_CFG_IDLE_SIO_LVL(1),
> + mxic->regs + HC_CFG);
> +}
> +
> static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf,
> void *rxbuf, unsigned int len)
> {
> @@ -328,6 +369,77 @@ static int mxic_spi_data_xfer(struct mxic_spi
> *mxic, const void *txbuf,
> return 0;
> }
>
> +static ssize_t mxic_spi_mem_dirmap_read(struct spi_mem_dirmap_desc
*desc,
> + u64 offs, size_t len, void *buf)
> +{
> + struct mxic_spi *mxic =
spi_master_get_devdata(desc->mem->spi->master);
> + int ret;
> + u32 sts;
> +
> + if (WARN_ON(offs + desc->info.offset + len > U32_MAX))
> + return -EINVAL;
> +
> + mxic_spi_set_hc_cfg(desc->mem->spi, 0);
> +
> + writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) |
> + LMODE_SLV_ACT(desc->mem->spi->chip_select) |
> + LMODE_EN,
> + mxic->regs + LRD_CTRL);
> + writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl),
> + mxic->regs + LRD_CFG);
> + writel(desc->info.offset + offs, mxic->regs + LRD_ADDR);
> + len = min_t(size_t, len, mxic->linear.size);
> + writel(len, mxic->regs + LRD_RANGE);
> +
> + memcpy_fromio(buf, mxic->linear.map, len);
> +
> + writel(INT_LRD_DIS, mxic->regs + INT_STS);
> + writel(0, mxic->regs + LRD_CTRL);
> +
> + ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
> + sts & INT_LRD_DIS, 0, USEC_PER_SEC);
> + if (ret)
> + return ret;
> +
> + return len;
> +}
> +
> +static ssize_t mxic_spi_mem_dirmap_write(struct spi_mem_dirmap_desc
*desc,
> + u64 offs, size_t len,
> + const void *buf)
> +{
> + struct mxic_spi *mxic =
spi_master_get_devdata(desc->mem->spi->master);
> + u32 sts;
> + int ret;
> +
> + if (WARN_ON(offs + desc->info.offset + len > U32_MAX))
> + return -EINVAL;
> +
> + mxic_spi_set_hc_cfg(desc->mem->spi, 0);
> +
> + writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) |
> + LMODE_SLV_ACT(desc->mem->spi->chip_select) |
> + LMODE_EN,
> + mxic->regs + LWR_CTRL);
> + writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl),
> + mxic->regs + LWR_CFG);
> + writel(desc->info.offset + offs, mxic->regs + LWR_ADDR);
> + len = min_t(size_t, len, mxic->linear.size);
> + writel(len, mxic->regs + LWR_RANGE);
> +
> + memcpy_toio(mxic->linear.map, buf, len);
> +
> + writel(INT_LWR_DIS, mxic->regs + INT_STS);
> + writel(0, mxic->regs + LWR_CTRL);
> +
> + ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
> + sts & INT_LWR_DIS, 0, USEC_PER_SEC);
> + if (ret)
> + return ret;
> +
> + return len;
> +}
> +
> static bool mxic_spi_mem_supports_op(struct spi_mem *mem,
> const struct spi_mem_op *op)
> {
> @@ -345,12 +457,27 @@ static bool mxic_spi_mem_supports_op(struct
> spi_mem *mem,
> return spi_mem_default_supports_op(mem, op);
> }
>
> +static int mxic_spi_mem_dirmap_create(struct spi_mem_dirmap_desc *desc)
> +{
> + struct mxic_spi *mxic =
spi_master_get_devdata(desc->mem->spi->master);
> +
> + if (!mxic->linear.map)
> + return -ENOTSUPP;
> +
> + if (desc->info.offset + desc->info.length > U32_MAX)
> + return -ENOTSUPP;
> +
> + if (!mxic_spi_mem_supports_op(desc->mem, &desc->info.op_tmpl))
> + return -ENOTSUPP;
> +
> + return 0;
> +}
> +
> static int mxic_spi_mem_exec_op(struct spi_mem *mem,
> const struct spi_mem_op *op)
> {
> struct mxic_spi *mxic = spi_master_get_devdata(mem->spi->master);
> - int nio = 1, i, ret;
> - u32 ss_ctrl;
> + int i, ret;
> u8 addr[8];
> u8 opcode = op->cmd.opcode;
>
> @@ -358,34 +485,12 @@ static int mxic_spi_mem_exec_op(struct spi_mem
*mem,
> if (ret)
> return ret;
>
> - if (mem->spi->mode & (SPI_TX_QUAD | SPI_RX_QUAD))
> - nio = 4;
> - else if (mem->spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL))
> - nio = 2;
> + mxic_spi_set_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN);
>
> - writel(HC_CFG_NIO(nio) |
> - HC_CFG_TYPE(mem->spi->chip_select, HC_CFG_TYPE_SPI_NOR) |
> - HC_CFG_SLV_ACT(mem->spi->chip_select) |
HC_CFG_IDLE_SIO_LVL(1) |
> - HC_CFG_MAN_CS_EN,
> - mxic->regs + HC_CFG);
> writel(HC_EN_BIT, mxic->regs + HC_EN);
>
> - ss_ctrl = OP_CMD_BYTES(1) | OP_CMD_BUSW(fls(op->cmd.buswidth) - 1);
> -
> - if (op->addr.nbytes)
> - ss_ctrl |= OP_ADDR_BYTES(op->addr.nbytes) |
> - OP_ADDR_BUSW(fls(op->addr.buswidth) - 1);
> -
> - if (op->dummy.nbytes)
> - ss_ctrl |= OP_DUMMY_CYC(op->dummy.nbytes);
> -
> - if (op->data.nbytes) {
> - ss_ctrl |= OP_DATA_BUSW(fls(op->data.buswidth) - 1);
> - if (op->data.dir == SPI_MEM_DATA_IN)
> - ss_ctrl |= OP_READ;
> - }
> -
> - writel(ss_ctrl, mxic->regs + SS_CTRL(mem->spi->chip_select));
> + writel(mxic_spi_mem_prep_op_cfg(op),
> + mxic->regs + SS_CTRL(mem->spi->chip_select));
>
> writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
> mxic->regs + HC_CFG);
> @@ -423,6 +528,9 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,
> static const struct spi_controller_mem_ops mxic_spi_mem_ops = {
> .supports_op = mxic_spi_mem_supports_op,
> .exec_op = mxic_spi_mem_exec_op,
> + .dirmap_create = mxic_spi_mem_dirmap_create,
> + .dirmap_read = mxic_spi_mem_dirmap_read,
> + .dirmap_write = mxic_spi_mem_dirmap_write,
> };
>
> static void mxic_spi_set_cs(struct spi_device *spi, bool lvl)
> @@ -552,6 +660,15 @@ static int mxic_spi_probe(struct platform_device
*pdev)
> if (IS_ERR(mxic->regs))
> return PTR_ERR(mxic->regs);
>
> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap");
> + mxic->linear.map = devm_ioremap_resource(&pdev->dev, res);
> + if (!IS_ERR(mxic->linear.map)) {
> + mxic->linear.dma = res->start;
> + mxic->linear.size = resource_size(res);
> + } else {
> + mxic->linear.map = NULL;
> + }
> +
> pm_runtime_enable(&pdev->dev);
> master->auto_runtime_pm = true;
>
> --
> 2.27.0
>
CONFIDENTIALITY NOTE:
This e-mail and any attachments may contain confidential information
and/or personal data, which is protected by applicable laws. Please be
reminded that duplication, disclosure, distribution, or use of this e-mail
(and/or its attachments) or any part thereof is prohibited. If you receive
this e-mail in error, please notify us immediately and delete this mail as
well as its attachment(s) from your system. In addition, please be
informed that collection, processing, and/or use of personal data is
prohibited unless expressly permitted by personal data protection laws.
Thank you for your attention and cooperation.
Macronix International Co., Ltd.
=====================================================================
============================================================================
CONFIDENTIALITY NOTE:
This e-mail and any attachments may contain confidential information and/or personal data, which is protected by applicable laws. Please be reminded that duplication, disclosure, distribution, or use of this e-mail (and/or its attachments) or any part thereof is prohibited. If you receive this e-mail in error, please notify us immediately and delete this mail as well as its attachment(s) from your system. In addition, please be informed that collection, processing, and/or use of personal data is prohibited unless expressly permitted by personal data protection laws. Thank you for your attention and cooperation.
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=====================================================================
^ permalink raw reply [flat|nested] 39+ messages in thread
* 回信: [RFC PATCH 09/10] spi: mxic: Add support for direct mapping
@ 2021-10-12 7:14 ` jaimeliao
0 siblings, 0 replies; 39+ messages in thread
From: jaimeliao @ 2021-10-12 7:14 UTC (permalink / raw)
To: Miquel Raynal
Cc: Boris Brezillon, Mark Brown, devicetree, juliensu, linux-kernel,
linux-mtd, linux-spi, Miquel Raynal, Richard Weinberger,
Rob Herring, Thomas Petazzoni, Tudor Ambarus,
Vignesh Raghavendra, Xiangsheng Hou
Hi Miquel
ZhengxunLi have patch new mxic spi host controller before.
The patch name as below
spi: mxic: patch for octal DTR mode support
Please patch mxic ECC engine base on latest version.
Thanks
Jaime
> [RFC PATCH 09/10] spi: mxic: Add support for direct mapping
>
> Implement the ->dirmap_create() and ->dirmap_read/write() hooks to
> provide a fast path for read and write accesses.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
> drivers/spi/spi-mxic.c | 171 ++++++++++++++++++++++++++++++++++-------
> 1 file changed, 144 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
> index 4fb19e6f94b0..e10c55ee4d06 100644
> --- a/drivers/spi/spi-mxic.c
> +++ b/drivers/spi/spi-mxic.c
> @@ -172,6 +172,11 @@ struct mxic_spi {
> struct clk *send_dly_clk;
> void __iomem *regs;
> u32 cur_speed_hz;
> + struct {
> + void __iomem *map;
> + dma_addr_t dma;
> + size_t size;
> + } linear;
> };
>
> static int mxic_spi_clk_enable(struct mxic_spi *mxic)
> @@ -280,6 +285,42 @@ static void mxic_spi_hw_init(struct mxic_spi *mxic)
> mxic->regs + HC_CFG);
> }
>
> +static u32 mxic_spi_mem_prep_op_cfg(const struct spi_mem_op *op)
> +{
> + u32 cfg = OP_CMD_BYTES(1) | OP_CMD_BUSW(fls(op->cmd.buswidth) - 1);
> +
> + if (op->addr.nbytes)
> + cfg |= OP_ADDR_BYTES(op->addr.nbytes) |
> + OP_ADDR_BUSW(fls(op->addr.buswidth) - 1);
> +
> + if (op->dummy.nbytes)
> + cfg |= OP_DUMMY_CYC(op->dummy.nbytes);
> +
> + if (op->data.dir != SPI_MEM_NO_DATA) {
> + cfg |= OP_DATA_BUSW(fls(op->data.buswidth) - 1);
> + if (op->data.dir == SPI_MEM_DATA_IN)
> + cfg |= OP_READ;
> + }
> +
> + return cfg;
> +}
> +
> +static void mxic_spi_set_hc_cfg(struct spi_device *spi, u32 flags)
> +{
> + struct mxic_spi *mxic = spi_master_get_devdata(spi->master);
> + int nio = 1;
> +
> + if (spi->mode & (SPI_TX_QUAD | SPI_RX_QUAD))
> + nio = 4;
> + else if (spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL))
> + nio = 2;
> +
> + writel(flags | HC_CFG_NIO(nio) |
> + HC_CFG_TYPE(spi->chip_select, HC_CFG_TYPE_SPI_NOR) |
> + HC_CFG_SLV_ACT(spi->chip_select) | HC_CFG_IDLE_SIO_LVL(1),
> + mxic->regs + HC_CFG);
> +}
> +
> static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf,
> void *rxbuf, unsigned int len)
> {
> @@ -328,6 +369,77 @@ static int mxic_spi_data_xfer(struct mxic_spi
> *mxic, const void *txbuf,
> return 0;
> }
>
> +static ssize_t mxic_spi_mem_dirmap_read(struct spi_mem_dirmap_desc
*desc,
> + u64 offs, size_t len, void *buf)
> +{
> + struct mxic_spi *mxic =
spi_master_get_devdata(desc->mem->spi->master);
> + int ret;
> + u32 sts;
> +
> + if (WARN_ON(offs + desc->info.offset + len > U32_MAX))
> + return -EINVAL;
> +
> + mxic_spi_set_hc_cfg(desc->mem->spi, 0);
> +
> + writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) |
> + LMODE_SLV_ACT(desc->mem->spi->chip_select) |
> + LMODE_EN,
> + mxic->regs + LRD_CTRL);
> + writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl),
> + mxic->regs + LRD_CFG);
> + writel(desc->info.offset + offs, mxic->regs + LRD_ADDR);
> + len = min_t(size_t, len, mxic->linear.size);
> + writel(len, mxic->regs + LRD_RANGE);
> +
> + memcpy_fromio(buf, mxic->linear.map, len);
> +
> + writel(INT_LRD_DIS, mxic->regs + INT_STS);
> + writel(0, mxic->regs + LRD_CTRL);
> +
> + ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
> + sts & INT_LRD_DIS, 0, USEC_PER_SEC);
> + if (ret)
> + return ret;
> +
> + return len;
> +}
> +
> +static ssize_t mxic_spi_mem_dirmap_write(struct spi_mem_dirmap_desc
*desc,
> + u64 offs, size_t len,
> + const void *buf)
> +{
> + struct mxic_spi *mxic =
spi_master_get_devdata(desc->mem->spi->master);
> + u32 sts;
> + int ret;
> +
> + if (WARN_ON(offs + desc->info.offset + len > U32_MAX))
> + return -EINVAL;
> +
> + mxic_spi_set_hc_cfg(desc->mem->spi, 0);
> +
> + writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) |
> + LMODE_SLV_ACT(desc->mem->spi->chip_select) |
> + LMODE_EN,
> + mxic->regs + LWR_CTRL);
> + writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl),
> + mxic->regs + LWR_CFG);
> + writel(desc->info.offset + offs, mxic->regs + LWR_ADDR);
> + len = min_t(size_t, len, mxic->linear.size);
> + writel(len, mxic->regs + LWR_RANGE);
> +
> + memcpy_toio(mxic->linear.map, buf, len);
> +
> + writel(INT_LWR_DIS, mxic->regs + INT_STS);
> + writel(0, mxic->regs + LWR_CTRL);
> +
> + ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
> + sts & INT_LWR_DIS, 0, USEC_PER_SEC);
> + if (ret)
> + return ret;
> +
> + return len;
> +}
> +
> static bool mxic_spi_mem_supports_op(struct spi_mem *mem,
> const struct spi_mem_op *op)
> {
> @@ -345,12 +457,27 @@ static bool mxic_spi_mem_supports_op(struct
> spi_mem *mem,
> return spi_mem_default_supports_op(mem, op);
> }
>
> +static int mxic_spi_mem_dirmap_create(struct spi_mem_dirmap_desc *desc)
> +{
> + struct mxic_spi *mxic =
spi_master_get_devdata(desc->mem->spi->master);
> +
> + if (!mxic->linear.map)
> + return -ENOTSUPP;
> +
> + if (desc->info.offset + desc->info.length > U32_MAX)
> + return -ENOTSUPP;
> +
> + if (!mxic_spi_mem_supports_op(desc->mem, &desc->info.op_tmpl))
> + return -ENOTSUPP;
> +
> + return 0;
> +}
> +
> static int mxic_spi_mem_exec_op(struct spi_mem *mem,
> const struct spi_mem_op *op)
> {
> struct mxic_spi *mxic = spi_master_get_devdata(mem->spi->master);
> - int nio = 1, i, ret;
> - u32 ss_ctrl;
> + int i, ret;
> u8 addr[8];
> u8 opcode = op->cmd.opcode;
>
> @@ -358,34 +485,12 @@ static int mxic_spi_mem_exec_op(struct spi_mem
*mem,
> if (ret)
> return ret;
>
> - if (mem->spi->mode & (SPI_TX_QUAD | SPI_RX_QUAD))
> - nio = 4;
> - else if (mem->spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL))
> - nio = 2;
> + mxic_spi_set_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN);
>
> - writel(HC_CFG_NIO(nio) |
> - HC_CFG_TYPE(mem->spi->chip_select, HC_CFG_TYPE_SPI_NOR) |
> - HC_CFG_SLV_ACT(mem->spi->chip_select) |
HC_CFG_IDLE_SIO_LVL(1) |
> - HC_CFG_MAN_CS_EN,
> - mxic->regs + HC_CFG);
> writel(HC_EN_BIT, mxic->regs + HC_EN);
>
> - ss_ctrl = OP_CMD_BYTES(1) | OP_CMD_BUSW(fls(op->cmd.buswidth) - 1);
> -
> - if (op->addr.nbytes)
> - ss_ctrl |= OP_ADDR_BYTES(op->addr.nbytes) |
> - OP_ADDR_BUSW(fls(op->addr.buswidth) - 1);
> -
> - if (op->dummy.nbytes)
> - ss_ctrl |= OP_DUMMY_CYC(op->dummy.nbytes);
> -
> - if (op->data.nbytes) {
> - ss_ctrl |= OP_DATA_BUSW(fls(op->data.buswidth) - 1);
> - if (op->data.dir == SPI_MEM_DATA_IN)
> - ss_ctrl |= OP_READ;
> - }
> -
> - writel(ss_ctrl, mxic->regs + SS_CTRL(mem->spi->chip_select));
> + writel(mxic_spi_mem_prep_op_cfg(op),
> + mxic->regs + SS_CTRL(mem->spi->chip_select));
>
> writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
> mxic->regs + HC_CFG);
> @@ -423,6 +528,9 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,
> static const struct spi_controller_mem_ops mxic_spi_mem_ops = {
> .supports_op = mxic_spi_mem_supports_op,
> .exec_op = mxic_spi_mem_exec_op,
> + .dirmap_create = mxic_spi_mem_dirmap_create,
> + .dirmap_read = mxic_spi_mem_dirmap_read,
> + .dirmap_write = mxic_spi_mem_dirmap_write,
> };
>
> static void mxic_spi_set_cs(struct spi_device *spi, bool lvl)
> @@ -552,6 +660,15 @@ static int mxic_spi_probe(struct platform_device
*pdev)
> if (IS_ERR(mxic->regs))
> return PTR_ERR(mxic->regs);
>
> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap");
> + mxic->linear.map = devm_ioremap_resource(&pdev->dev, res);
> + if (!IS_ERR(mxic->linear.map)) {
> + mxic->linear.dma = res->start;
> + mxic->linear.size = resource_size(res);
> + } else {
> + mxic->linear.map = NULL;
> + }
> +
> pm_runtime_enable(&pdev->dev);
> master->auto_runtime_pm = true;
>
> --
> 2.27.0
>
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: 回信: [RFC PATCH 08/10] spi: mxic: Fix the transmit path
[not found] ` <OF11A0CCB6.4C81ABAD-ON4825876D.00256D6A-4825876D.00256F7A@LocalDomain>
@ 2021-10-13 7:04 ` zhengxunli
0 siblings, 0 replies; 39+ messages in thread
From: zhengxunli @ 2021-10-13 7:04 UTC (permalink / raw)
To: Miquel Raynal
Cc: Rob Herring, Mark Brown, Xiangsheng Hou, Boris Brezillon,
devicetree, linux-kernel, jaimeliao, juliensu, Thomas Petazzoni,
Miquel Raynal, stable, Mason Yang, Richard Weinberger,
Vignesh Raghavendra, Tudor Ambarus, linux-mtd, linux-spi
> By working with external hardware ECC engines, we figured out that
> Under certain circumstances, it is needed for the SPI controller to
> check INT_TX_EMPTY and INT_RX_NOT_EMPTY in both receive and transmit
> path (not only in the receive path). The delay penalty being
> negligible, move this code in the common path.
>
> Fixes: b942d80b0a39 ("spi: Add MXIC controller driver")
> Cc: stable@vger.kernel.org
> Suggested-by: Mason Yang <masonccyang@mxic.com.tw>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
> drivers/spi/spi-mxic.c | 28 ++++++++++++----------------
> 1 file changed, 12 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
> index 96b418293bf2..4fb19e6f94b0 100644
> --- a/drivers/spi/spi-mxic.c
> +++ b/drivers/spi/spi-mxic.c
> @@ -304,25 +304,21 @@ static int mxic_spi_data_xfer(struct mxic_spi
> *mxic, const void *txbuf,
>
> writel(data, mxic->regs + TXD(nbytes % 4));
>
> + ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
> + sts & INT_TX_EMPTY, 0, USEC_PER_SEC);
> + if (ret)
> + return ret;
> +
> + ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
> + sts & INT_RX_NOT_EMPTY, 0,
> + USEC_PER_SEC);
> + if (ret)
> + return ret;
> +
> + data = readl(mxic->regs + RXD);
> if (rxbuf) {
> - ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
> - sts & INT_TX_EMPTY, 0,
> - USEC_PER_SEC);
> - if (ret)
> - return ret;
> -
> - ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
> - sts & INT_RX_NOT_EMPTY, 0,
> - USEC_PER_SEC);
> - if (ret)
> - return ret;
> -
> - data = readl(mxic->regs + RXD);
> data >>= (8 * (4 - nbytes));
> memcpy(rxbuf + pos, &data, nbytes);
> - WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY);
> - } else {
> - readl(mxic->regs + RXD);
> }
> WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY);
>
> --
> 2.27.0
>
Reviewed-by: Zhengxun Li <zhengxunli@mxic.com.tw>
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: 回信: [RFC PATCH 08/10] spi: mxic: Fix the transmit path
@ 2021-10-13 7:04 ` zhengxunli
0 siblings, 0 replies; 39+ messages in thread
From: zhengxunli @ 2021-10-13 7:04 UTC (permalink / raw)
To: Miquel Raynal
Cc: Rob Herring, Mark Brown, Xiangsheng Hou, Boris Brezillon,
devicetree, linux-kernel, jaimeliao, juliensu, Thomas Petazzoni,
Miquel Raynal, stable, Mason Yang, Richard Weinberger,
Vignesh Raghavendra, Tudor Ambarus, linux-mtd, linux-spi
> By working with external hardware ECC engines, we figured out that
> Under certain circumstances, it is needed for the SPI controller to
> check INT_TX_EMPTY and INT_RX_NOT_EMPTY in both receive and transmit
> path (not only in the receive path). The delay penalty being
> negligible, move this code in the common path.
>
> Fixes: b942d80b0a39 ("spi: Add MXIC controller driver")
> Cc: stable@vger.kernel.org
> Suggested-by: Mason Yang <masonccyang@mxic.com.tw>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
> drivers/spi/spi-mxic.c | 28 ++++++++++++----------------
> 1 file changed, 12 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
> index 96b418293bf2..4fb19e6f94b0 100644
> --- a/drivers/spi/spi-mxic.c
> +++ b/drivers/spi/spi-mxic.c
> @@ -304,25 +304,21 @@ static int mxic_spi_data_xfer(struct mxic_spi
> *mxic, const void *txbuf,
>
> writel(data, mxic->regs + TXD(nbytes % 4));
>
> + ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
> + sts & INT_TX_EMPTY, 0, USEC_PER_SEC);
> + if (ret)
> + return ret;
> +
> + ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
> + sts & INT_RX_NOT_EMPTY, 0,
> + USEC_PER_SEC);
> + if (ret)
> + return ret;
> +
> + data = readl(mxic->regs + RXD);
> if (rxbuf) {
> - ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
> - sts & INT_TX_EMPTY, 0,
> - USEC_PER_SEC);
> - if (ret)
> - return ret;
> -
> - ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
> - sts & INT_RX_NOT_EMPTY, 0,
> - USEC_PER_SEC);
> - if (ret)
> - return ret;
> -
> - data = readl(mxic->regs + RXD);
> data >>= (8 * (4 - nbytes));
> memcpy(rxbuf + pos, &data, nbytes);
> - WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY);
> - } else {
> - readl(mxic->regs + RXD);
> }
> WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY);
>
> --
> 2.27.0
>
Reviewed-by: Zhengxun Li <zhengxunli@mxic.com.tw>
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: 回信: [RFC PATCH 09/10] spi: mxic: Add support for direct mapping
[not found] ` <OF86339F0C.88E145E3-ON4825876D.002567AA-4825876D.002569D9@LocalDomain>
@ 2021-10-13 7:23 ` zhengxunli
0 siblings, 0 replies; 39+ messages in thread
From: zhengxunli @ 2021-10-13 7:23 UTC (permalink / raw)
To: Miquel Raynal
Cc: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus,
linux-mtd, Rob Herring, Mark Brown, Xiangsheng Hou,
Boris Brezillon, devicetree, linux-spi, linux-kernel, jaimeliao,
juliensu, Thomas Petazzoni, Miquel Raynal
> Implement the ->dirmap_create() and ->dirmap_read/write() hooks to
> provide a fast path for read and write accesses.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
> drivers/spi/spi-mxic.c | 171 ++++++++++++++++++++++++++++++++++-------
> 1 file changed, 144 insertions(+), 27 deletions(-)
Hi Miquel,
I verified it by reading, writing, and erasing through normal and quad
modes
on the Xilinx Zynq PicoZed FPGA board. Except for the need to update the
SPI
MXIC driver version, it looks good.
Tested-by: Zhengxun Li <zhengxunli@mxic.com.tw>
Reviewed-by: Zhengxun Li <zhengxunli@mxic.com.tw>
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============================================================================
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: 回信: [RFC PATCH 09/10] spi: mxic: Add support for direct mapping
@ 2021-10-13 7:23 ` zhengxunli
0 siblings, 0 replies; 39+ messages in thread
From: zhengxunli @ 2021-10-13 7:23 UTC (permalink / raw)
To: Miquel Raynal
Cc: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus,
linux-mtd, Rob Herring, Mark Brown, Xiangsheng Hou,
Boris Brezillon, devicetree, linux-spi, linux-kernel, jaimeliao,
juliensu, Thomas Petazzoni, Miquel Raynal
> Implement the ->dirmap_create() and ->dirmap_read/write() hooks to
> provide a fast path for read and write accesses.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
> drivers/spi/spi-mxic.c | 171 ++++++++++++++++++++++++++++++++++-------
> 1 file changed, 144 insertions(+), 27 deletions(-)
Hi Miquel,
I verified it by reading, writing, and erasing through normal and quad
modes
on the Xilinx Zynq PicoZed FPGA board. Except for the need to update the
SPI
MXIC driver version, it looks good.
Tested-by: Zhengxun Li <zhengxunli@mxic.com.tw>
Reviewed-by: Zhengxun Li <zhengxunli@mxic.com.tw>
CONFIDENTIALITY NOTE:
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prohibited unless expressly permitted by personal data protection laws.
Thank you for your attention and cooperation.
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=====================================================================
============================================================================
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC PATCH 06/10] mtd: nand: mxic-ecc: Add Macronix external ECC engine support
2021-10-08 16:22 ` Miquel Raynal
(?)
@ 2021-10-13 9:15 ` xiangsheng.hou
2021-10-15 9:37 ` Miquel Raynal
-1 siblings, 1 reply; 39+ messages in thread
From: xiangsheng.hou @ 2021-10-13 9:15 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Tudor Ambarus, linux-mtd
Cc: Rob Herring, Mark Brown, Boris Brezillon, devicetree, linux-spi,
linux-kernel, jaimeliao, juliensu, Thomas Petazzoni
Hi,
On Fri, 2021-10-08 at 18:22 +0200, Miquel Raynal wrote:
>
> +static int mxic_ecc_count_biterrs(struct mxic_ecc_engine *eng,
> struct mtd_info *mtd)
> +{
> + struct device *dev = eng->dev;
> + unsigned int max_bf = 0;
> + int step;
> +
> + for (step = 0; step < eng->steps; step++) {
> + u8 stat = eng->status[step];
> +
> + if (stat == NO_ERR) {
> + dev_dbg(dev, "ECC step %d: no error\n", step);
> + } else if (stat == ERASED_CHUNK) {
> + dev_dbg(dev, "ECC step %d: erased\n", step);
> + } else if (stat == UNCORR_ERR || stat > MAX_CORR_ERR) {
> + dev_dbg(dev, "ECC step %d: uncorrectable\n",
> step);
> + mtd->ecc_stats.failed++;
> + } else {
> + dev_dbg(dev, "ECC step %d: %d bits
> corrected\n",
> + step, stat);
> + max_bf = max_t(unsigned int, max_bf, stat);
> + mtd->ecc_stats.corrected += stat;
> + }
> + }
> +
> + return max_bf;
> +}
In spinand_mtd_read() function, rely on the return value -EBADMSG to
check whether ecc failed. Therefore, maybe there also need return this
value in mxic_ecc_count_biterrs() function when uncorrectable ecc
error?
Thanks
Xiangsheng Hou
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: 回信: [RFC PATCH 09/10] spi: mxic: Add support for direct mapping
2021-10-12 7:14 ` jaimeliao
@ 2021-10-15 8:29 ` Miquel Raynal
-1 siblings, 0 replies; 39+ messages in thread
From: Miquel Raynal @ 2021-10-15 8:29 UTC (permalink / raw)
To: jaimeliao
Cc: Boris Brezillon, Mark Brown, devicetree, juliensu, linux-kernel,
linux-mtd, linux-spi, Richard Weinberger, Rob Herring,
Thomas Petazzoni, Tudor Ambarus, Vignesh Raghavendra,
Xiangsheng Hou
Hello Jaime,
jaimeliao@mxic.com.tw wrote on Tue, 12 Oct 2021 15:14:56 +0800:
> Hi Miquel
>
> ZhengxunLi have patch new mxic spi host controller before.
> The patch name as below
> spi: mxic: patch for octal DTR mode support
> Please patch mxic ECC engine base on latest version.
Yes you are right. I didn't rebase my series before sending it, as
mentioned in the cover letter this was just a way to provide this code
publicly as someone from Mediatek needed it (hence, the RFC). I will
soon send a real v1 with the bindings fixed as well.
Thanks,
Miquèl
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: 回信: [RFC PATCH 09/10] spi: mxic: Add support for direct mapping
@ 2021-10-15 8:29 ` Miquel Raynal
0 siblings, 0 replies; 39+ messages in thread
From: Miquel Raynal @ 2021-10-15 8:29 UTC (permalink / raw)
To: jaimeliao
Cc: Boris Brezillon, Mark Brown, devicetree, juliensu, linux-kernel,
linux-mtd, linux-spi, Richard Weinberger, Rob Herring,
Thomas Petazzoni, Tudor Ambarus, Vignesh Raghavendra,
Xiangsheng Hou
Hello Jaime,
jaimeliao@mxic.com.tw wrote on Tue, 12 Oct 2021 15:14:56 +0800:
> Hi Miquel
>
> ZhengxunLi have patch new mxic spi host controller before.
> The patch name as below
> spi: mxic: patch for octal DTR mode support
> Please patch mxic ECC engine base on latest version.
Yes you are right. I didn't rebase my series before sending it, as
mentioned in the cover letter this was just a way to provide this code
publicly as someone from Mediatek needed it (hence, the RFC). I will
soon send a real v1 with the bindings fixed as well.
Thanks,
Miquèl
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC PATCH 06/10] mtd: nand: mxic-ecc: Add Macronix external ECC engine support
2021-10-13 9:15 ` xiangsheng.hou
@ 2021-10-15 9:37 ` Miquel Raynal
0 siblings, 0 replies; 39+ messages in thread
From: Miquel Raynal @ 2021-10-15 9:37 UTC (permalink / raw)
To: xiangsheng.hou
Cc: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus,
linux-mtd, Rob Herring, Mark Brown, Boris Brezillon, devicetree,
linux-spi, linux-kernel, jaimeliao, juliensu, Thomas Petazzoni
Hi xiangsheng.hou,
xiangsheng.hou@mediatek.com wrote on Wed, 13 Oct 2021 17:15:49 +0800:
> Hi,
>
> On Fri, 2021-10-08 at 18:22 +0200, Miquel Raynal wrote:
> >
> > +static int mxic_ecc_count_biterrs(struct mxic_ecc_engine *eng,
> > struct mtd_info *mtd)
> > +{
> > + struct device *dev = eng->dev;
> > + unsigned int max_bf = 0;
> > + int step;
> > +
> > + for (step = 0; step < eng->steps; step++) {
> > + u8 stat = eng->status[step];
> > +
> > + if (stat == NO_ERR) {
> > + dev_dbg(dev, "ECC step %d: no error\n", step);
> > + } else if (stat == ERASED_CHUNK) {
> > + dev_dbg(dev, "ECC step %d: erased\n", step);
> > + } else if (stat == UNCORR_ERR || stat > MAX_CORR_ERR) {
> > + dev_dbg(dev, "ECC step %d: uncorrectable\n",
> > step);
> > + mtd->ecc_stats.failed++;
> > + } else {
> > + dev_dbg(dev, "ECC step %d: %d bits
> > corrected\n",
> > + step, stat);
> > + max_bf = max_t(unsigned int, max_bf, stat);
> > + mtd->ecc_stats.corrected += stat;
> > + }
> > + }
> > +
> > + return max_bf;
> > +}
>
> In spinand_mtd_read() function, rely on the return value -EBADMSG to
> check whether ecc failed. Therefore, maybe there also need return this
> value in mxic_ecc_count_biterrs() function when uncorrectable ecc
> error?
True, I'll fix this.
Thanks,
Miquèl
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [RFC PATCH 06/10] mtd: nand: mxic-ecc: Add Macronix external ECC engine support
@ 2021-10-15 9:37 ` Miquel Raynal
0 siblings, 0 replies; 39+ messages in thread
From: Miquel Raynal @ 2021-10-15 9:37 UTC (permalink / raw)
To: xiangsheng.hou
Cc: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus,
linux-mtd, Rob Herring, Mark Brown, Boris Brezillon, devicetree,
linux-spi, linux-kernel, jaimeliao, juliensu, Thomas Petazzoni
Hi xiangsheng.hou,
xiangsheng.hou@mediatek.com wrote on Wed, 13 Oct 2021 17:15:49 +0800:
> Hi,
>
> On Fri, 2021-10-08 at 18:22 +0200, Miquel Raynal wrote:
> >
> > +static int mxic_ecc_count_biterrs(struct mxic_ecc_engine *eng,
> > struct mtd_info *mtd)
> > +{
> > + struct device *dev = eng->dev;
> > + unsigned int max_bf = 0;
> > + int step;
> > +
> > + for (step = 0; step < eng->steps; step++) {
> > + u8 stat = eng->status[step];
> > +
> > + if (stat == NO_ERR) {
> > + dev_dbg(dev, "ECC step %d: no error\n", step);
> > + } else if (stat == ERASED_CHUNK) {
> > + dev_dbg(dev, "ECC step %d: erased\n", step);
> > + } else if (stat == UNCORR_ERR || stat > MAX_CORR_ERR) {
> > + dev_dbg(dev, "ECC step %d: uncorrectable\n",
> > step);
> > + mtd->ecc_stats.failed++;
> > + } else {
> > + dev_dbg(dev, "ECC step %d: %d bits
> > corrected\n",
> > + step, stat);
> > + max_bf = max_t(unsigned int, max_bf, stat);
> > + mtd->ecc_stats.corrected += stat;
> > + }
> > + }
> > +
> > + return max_bf;
> > +}
>
> In spinand_mtd_read() function, rely on the return value -EBADMSG to
> check whether ecc failed. Therefore, maybe there also need return this
> value in mxic_ecc_count_biterrs() function when uncorrectable ecc
> error?
True, I'll fix this.
Thanks,
Miquèl
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 39+ messages in thread
* 回信: Re: [RFC PATCH 03/10] dt-bindings: vendor-prefixes: Update Macronix prefix
2021-10-08 21:47 ` Rob Herring
@ 2021-10-18 1:42 ` jaimeliao
-1 siblings, 0 replies; 39+ messages in thread
From: jaimeliao @ 2021-10-18 1:42 UTC (permalink / raw)
To: Rob Herring
Cc: Boris Brezillon, Mark Brown, devicetree, juliensu, linux-kernel,
linux-mtd, linux-spi, Miquel Raynal, Richard Weinberger,
Thomas Petazzoni, Tudor Ambarus, Vignesh Raghavendra,
Xiangsheng Hou
Hi Rob
>
> Re: [RFC PATCH 03/10] dt-bindings: vendor-prefixes: Update Macronix
prefix
>
> On Fri, Oct 08, 2021 at 06:22:21PM +0200, Miquel Raynal wrote:
> > When looking at compatible prefixes, Macronix is sometimes referred as
> > mxicy:
> > - mxicy,mx25r1635f
> > - mxicy,mx25u6435f
> > - mxicy,mx25v8035f
> > - mxicy,mx25f0a-spi
> > and sometimes as mxic:
> > - mxic,multi-itfc-v009-nand-controller
> > - mxic,enable-randomizer-otp
> >
> > It looks like the more up-to-date way is mxic so declare this prefix
and
> > mark the other one as deprecated.
>
> mxicy is more widely used with flash parts. There's not a single dts
> file with 'mxic' which only seems to be some nand controller.
Yes, you are right.
Hi Miquel
Please keep using "mxicy,*" consistently for the compatible property,
thanks.
>
> >
> > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> > ---
> > Documentation/devicetree/bindings/vendor-prefixes.yaml | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/vendor-
> prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> > index b868cefc7c55..013a87850cd5 100644
> > --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> > +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> > @@ -758,8 +758,11 @@ patternProperties:
> > description: Mundo Reader S.L.
> > "^murata,.*":
> > description: Murata Manufacturing Co., Ltd.
> > + "^mxic,.*":
> > + description: Macronix International Co., Ltd.
> > "^mxicy,.*":
> > description: Macronix International Co., Ltd.
> > + deprecated: true
> > "^myir,.*":
> > description: MYIR Tech Limited
> > "^national,.*":
> > --
> > 2.27.0
> >
> >
CONFIDENTIALITY NOTE:
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Thank you for your attention and cooperation.
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=====================================================================
============================================================================
CONFIDENTIALITY NOTE:
This e-mail and any attachments may contain confidential information and/or personal data, which is protected by applicable laws. Please be reminded that duplication, disclosure, distribution, or use of this e-mail (and/or its attachments) or any part thereof is prohibited. If you receive this e-mail in error, please notify us immediately and delete this mail as well as its attachment(s) from your system. In addition, please be informed that collection, processing, and/or use of personal data is prohibited unless expressly permitted by personal data protection laws. Thank you for your attention and cooperation.
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=====================================================================
^ permalink raw reply [flat|nested] 39+ messages in thread
* 回信: Re: [RFC PATCH 03/10] dt-bindings: vendor-prefixes: Update Macronix prefix
@ 2021-10-18 1:42 ` jaimeliao
0 siblings, 0 replies; 39+ messages in thread
From: jaimeliao @ 2021-10-18 1:42 UTC (permalink / raw)
To: Rob Herring
Cc: Boris Brezillon, Mark Brown, devicetree, juliensu, linux-kernel,
linux-mtd, linux-spi, Miquel Raynal, Richard Weinberger,
Thomas Petazzoni, Tudor Ambarus, Vignesh Raghavendra,
Xiangsheng Hou
Hi Rob
>
> Re: [RFC PATCH 03/10] dt-bindings: vendor-prefixes: Update Macronix
prefix
>
> On Fri, Oct 08, 2021 at 06:22:21PM +0200, Miquel Raynal wrote:
> > When looking at compatible prefixes, Macronix is sometimes referred as
> > mxicy:
> > - mxicy,mx25r1635f
> > - mxicy,mx25u6435f
> > - mxicy,mx25v8035f
> > - mxicy,mx25f0a-spi
> > and sometimes as mxic:
> > - mxic,multi-itfc-v009-nand-controller
> > - mxic,enable-randomizer-otp
> >
> > It looks like the more up-to-date way is mxic so declare this prefix
and
> > mark the other one as deprecated.
>
> mxicy is more widely used with flash parts. There's not a single dts
> file with 'mxic' which only seems to be some nand controller.
Yes, you are right.
Hi Miquel
Please keep using "mxicy,*" consistently for the compatible property,
thanks.
>
> >
> > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> > ---
> > Documentation/devicetree/bindings/vendor-prefixes.yaml | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/vendor-
> prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> > index b868cefc7c55..013a87850cd5 100644
> > --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> > +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> > @@ -758,8 +758,11 @@ patternProperties:
> > description: Mundo Reader S.L.
> > "^murata,.*":
> > description: Murata Manufacturing Co., Ltd.
> > + "^mxic,.*":
> > + description: Macronix International Co., Ltd.
> > "^mxicy,.*":
> > description: Macronix International Co., Ltd.
> > + deprecated: true
> > "^myir,.*":
> > description: MYIR Tech Limited
> > "^national,.*":
> > --
> > 2.27.0
> >
> >
CONFIDENTIALITY NOTE:
This e-mail and any attachments may contain confidential information
and/or personal data, which is protected by applicable laws. Please be
reminded that duplication, disclosure, distribution, or use of this e-mail
(and/or its attachments) or any part thereof is prohibited. If you receive
this e-mail in error, please notify us immediately and delete this mail as
well as its attachment(s) from your system. In addition, please be
informed that collection, processing, and/or use of personal data is
prohibited unless expressly permitted by personal data protection laws.
Thank you for your attention and cooperation.
Macronix International Co., Ltd.
=====================================================================
============================================================================
CONFIDENTIALITY NOTE:
This e-mail and any attachments may contain confidential information and/or personal data, which is protected by applicable laws. Please be reminded that duplication, disclosure, distribution, or use of this e-mail (and/or its attachments) or any part thereof is prohibited. If you receive this e-mail in error, please notify us immediately and delete this mail as well as its attachment(s) from your system. In addition, please be informed that collection, processing, and/or use of personal data is prohibited unless expressly permitted by personal data protection laws. Thank you for your attention and cooperation.
Macronix International Co., Ltd.
=====================================================================
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 39+ messages in thread
end of thread, other threads:[~2021-10-18 1:44 UTC | newest]
Thread overview: 39+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-08 16:22 [RFC PATCH 00/10] Macronix ECC engine Miquel Raynal
2021-10-08 16:22 ` Miquel Raynal
2021-10-08 16:22 ` [RFC PATCH 01/10] mtd: spinand: Fix comment Miquel Raynal
2021-10-08 16:22 ` Miquel Raynal
2021-10-08 16:22 ` [RFC PATCH 02/10] mtd: spinand: macronix: Use random program load Miquel Raynal
2021-10-08 16:22 ` Miquel Raynal
2021-10-08 16:22 ` [RFC PATCH 03/10] dt-bindings: vendor-prefixes: Update Macronix prefix Miquel Raynal
2021-10-08 16:22 ` Miquel Raynal
2021-10-08 21:47 ` Rob Herring
2021-10-08 21:47 ` Rob Herring
2021-10-18 1:42 ` 回信: " jaimeliao
2021-10-18 1:42 ` jaimeliao
2021-10-08 16:22 ` [RFC PATCH 04/10] dt-bindings: mtd: Describe Macronix NAND ECC engine Miquel Raynal
2021-10-08 16:22 ` Miquel Raynal
2021-10-08 19:48 ` Rob Herring
2021-10-08 19:48 ` Rob Herring
2021-10-08 16:22 ` [RFC PATCH 05/10] mtd: nand: ecc: Add infrastructure to support hardware engines Miquel Raynal
2021-10-08 16:22 ` Miquel Raynal
2021-10-08 16:22 ` [RFC PATCH 06/10] mtd: nand: mxic-ecc: Add Macronix external ECC engine support Miquel Raynal
2021-10-08 16:22 ` Miquel Raynal
2021-10-13 9:15 ` xiangsheng.hou
2021-10-15 9:37 ` Miquel Raynal
2021-10-15 9:37 ` Miquel Raynal
2021-10-08 16:22 ` [RFC PATCH 07/10] mtd: nand: mxic-ecc: Support SPI pipelined mode Miquel Raynal
2021-10-08 16:22 ` Miquel Raynal
2021-10-08 16:22 ` [RFC PATCH 08/10] spi: mxic: Fix the transmit path Miquel Raynal
2021-10-08 16:22 ` Miquel Raynal
[not found] ` <OF11A0CCB6.4C81ABAD-ON4825876D.00256D6A-4825876D.00256F7A@LocalDomain>
2021-10-13 7:04 ` 回信: " zhengxunli
2021-10-13 7:04 ` zhengxunli
2021-10-08 16:22 ` [RFC PATCH 09/10] spi: mxic: Add support for direct mapping Miquel Raynal
2021-10-08 16:22 ` Miquel Raynal
2021-10-12 7:14 ` 回信: " jaimeliao
2021-10-12 7:14 ` jaimeliao
2021-10-15 8:29 ` Miquel Raynal
2021-10-15 8:29 ` Miquel Raynal
[not found] ` <OF86339F0C.88E145E3-ON4825876D.002567AA-4825876D.002569D9@LocalDomain>
2021-10-13 7:23 ` zhengxunli
2021-10-13 7:23 ` zhengxunli
2021-10-08 16:22 ` [RFC PATCH 10/10] spi: mxic: Add support for pipelined ECC operations Miquel Raynal
2021-10-08 16:22 ` Miquel Raynal
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