From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2219EC433EF for ; Fri, 8 Oct 2021 23:48:29 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D067B60F9D for ; Fri, 8 Oct 2021 23:48:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org D067B60F9D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 009BA6E2C7; Fri, 8 Oct 2021 23:48:28 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 26EA26E2C7; Fri, 8 Oct 2021 23:48:27 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10131"; a="226564844" X-IronPort-AV: E=Sophos;i="5.85,358,1624345200"; d="scan'208";a="226564844" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2021 16:48:26 -0700 X-IronPort-AV: E=Sophos;i="5.85,358,1624345200"; d="scan'208";a="590708028" Received: from mdroper-desk1.fm.intel.com (HELO mdroper-desk1.amr.corp.intel.com) ([10.1.27.134]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2021 16:48:26 -0700 Date: Fri, 8 Oct 2021 16:48:25 -0700 From: Matt Roper To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, Paulo Zanoni , Stuart Summers , Tvrtko Ursulin Subject: Re: [PATCH 07/11] drm/i915/xehp: Determine which tile raised an interrupt Message-ID: <20211008234825.GS602200@mdroper-desk1.amr.corp.intel.com> References: <20211008215635.2026385-1-matthew.d.roper@intel.com> <20211008215635.2026385-8-matthew.d.roper@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20211008215635.2026385-8-matthew.d.roper@intel.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Fri, Oct 08, 2021 at 02:56:31PM -0700, Matt Roper wrote: > From: Paulo Zanoni > > The first step of interrupt handling is to read a tile0 register that > tells us in which tile the interrupt happened; we can then we read the > usual interrupt registers from the appropriate tile. > > Note that this is just the first step of handling interrupts properly on > multi-tile platforms. Subsequent patches will convert other parts of > the interrupt handling flow. > > Cc: Stuart Summers > Signed-off-by: Paulo Zanoni > Signed-off-by: Tvrtko Ursulin > Signed-off-by: Matt Roper > --- > drivers/gpu/drm/i915/i915_irq.c | 31 ++++++++++++++++--------------- > 1 file changed, 16 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 038a9ec563c1..9f99ad56cde6 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -2772,37 +2772,38 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg) > { > struct drm_i915_private * const i915 = arg; > struct intel_gt *gt = &i915->gt; > - void __iomem * const regs = gt->uncore->regs; > + void __iomem * const t0_regs = gt->uncore->regs; > u32 master_tile_ctl, master_ctl; > - u32 gu_misc_iir; > + u32 gu_misc_iir = 0; > + unsigned int i; > > if (!intel_irqs_enabled(i915)) > return IRQ_NONE; > > - master_tile_ctl = dg1_master_intr_disable(regs); > + master_tile_ctl = dg1_master_intr_disable(t0_regs); > if (!master_tile_ctl) { > - dg1_master_intr_enable(regs); > + dg1_master_intr_enable(t0_regs); > return IRQ_NONE; > } > > - /* FIXME: we only support tile 0 for now. */ > - if (master_tile_ctl & DG1_MSTR_TILE(0)) { > + for_each_gt(i915, i, gt) { > + void __iomem *const regs = gt->uncore->regs; > + > + if ((master_tile_ctl & DG1_MSTR_TILE(i)) == 0) > + continue; > + > master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ); > raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, master_ctl); > - } else { > - DRM_ERROR("Tile not supported: 0x%08x\n", master_tile_ctl); > - dg1_master_intr_enable(regs); > - return IRQ_NONE; > - } > > - gen11_gt_irq_handler(gt, master_ctl); > + gen11_gt_irq_handler(gt, master_ctl); > + > + gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl); Hmm, I missed it before sending the series, but this doesn't look right. We ack every tile's gu_misc_irq separately, but... > + } > > if (master_ctl & GEN11_DISPLAY_IRQ) > gen11_display_irq_handler(i915); > > - gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl); > - > - dg1_master_intr_enable(regs); > + dg1_master_intr_enable(t0_regs); > > gen11_gu_misc_irq_handler(gt, gu_misc_iir); ...only handle the value from the final tile? Looks like this was intended to move inside the loop as well. Matt > > -- > 2.33.0 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 641CEC433EF for ; Fri, 8 Oct 2021 23:48:33 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2AE9260F9D for ; Fri, 8 Oct 2021 23:48:33 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 2AE9260F9D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 846536E2C8; Fri, 8 Oct 2021 23:48:28 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 26EA26E2C7; Fri, 8 Oct 2021 23:48:27 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10131"; a="226564844" X-IronPort-AV: E=Sophos;i="5.85,358,1624345200"; d="scan'208";a="226564844" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2021 16:48:26 -0700 X-IronPort-AV: E=Sophos;i="5.85,358,1624345200"; d="scan'208";a="590708028" Received: from mdroper-desk1.fm.intel.com (HELO mdroper-desk1.amr.corp.intel.com) ([10.1.27.134]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2021 16:48:26 -0700 Date: Fri, 8 Oct 2021 16:48:25 -0700 From: Matt Roper To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, Paulo Zanoni , Stuart Summers , Tvrtko Ursulin Message-ID: <20211008234825.GS602200@mdroper-desk1.amr.corp.intel.com> References: <20211008215635.2026385-1-matthew.d.roper@intel.com> <20211008215635.2026385-8-matthew.d.roper@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20211008215635.2026385-8-matthew.d.roper@intel.com> Subject: Re: [Intel-gfx] [PATCH 07/11] drm/i915/xehp: Determine which tile raised an interrupt X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, Oct 08, 2021 at 02:56:31PM -0700, Matt Roper wrote: > From: Paulo Zanoni > > The first step of interrupt handling is to read a tile0 register that > tells us in which tile the interrupt happened; we can then we read the > usual interrupt registers from the appropriate tile. > > Note that this is just the first step of handling interrupts properly on > multi-tile platforms. Subsequent patches will convert other parts of > the interrupt handling flow. > > Cc: Stuart Summers > Signed-off-by: Paulo Zanoni > Signed-off-by: Tvrtko Ursulin > Signed-off-by: Matt Roper > --- > drivers/gpu/drm/i915/i915_irq.c | 31 ++++++++++++++++--------------- > 1 file changed, 16 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 038a9ec563c1..9f99ad56cde6 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -2772,37 +2772,38 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg) > { > struct drm_i915_private * const i915 = arg; > struct intel_gt *gt = &i915->gt; > - void __iomem * const regs = gt->uncore->regs; > + void __iomem * const t0_regs = gt->uncore->regs; > u32 master_tile_ctl, master_ctl; > - u32 gu_misc_iir; > + u32 gu_misc_iir = 0; > + unsigned int i; > > if (!intel_irqs_enabled(i915)) > return IRQ_NONE; > > - master_tile_ctl = dg1_master_intr_disable(regs); > + master_tile_ctl = dg1_master_intr_disable(t0_regs); > if (!master_tile_ctl) { > - dg1_master_intr_enable(regs); > + dg1_master_intr_enable(t0_regs); > return IRQ_NONE; > } > > - /* FIXME: we only support tile 0 for now. */ > - if (master_tile_ctl & DG1_MSTR_TILE(0)) { > + for_each_gt(i915, i, gt) { > + void __iomem *const regs = gt->uncore->regs; > + > + if ((master_tile_ctl & DG1_MSTR_TILE(i)) == 0) > + continue; > + > master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ); > raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, master_ctl); > - } else { > - DRM_ERROR("Tile not supported: 0x%08x\n", master_tile_ctl); > - dg1_master_intr_enable(regs); > - return IRQ_NONE; > - } > > - gen11_gt_irq_handler(gt, master_ctl); > + gen11_gt_irq_handler(gt, master_ctl); > + > + gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl); Hmm, I missed it before sending the series, but this doesn't look right. We ack every tile's gu_misc_irq separately, but... > + } > > if (master_ctl & GEN11_DISPLAY_IRQ) > gen11_display_irq_handler(i915); > > - gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl); > - > - dg1_master_intr_enable(regs); > + dg1_master_intr_enable(t0_regs); > > gen11_gu_misc_irq_handler(gt, gu_misc_iir); ...only handle the value from the final tile? Looks like this was intended to move inside the loop as well. Matt > > -- > 2.33.0 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795