From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8590C433F5 for ; Tue, 12 Oct 2021 15:44:25 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 595A760E53 for ; Tue, 12 Oct 2021 15:44:25 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 595A760E53 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id DEF66835BA; Tue, 12 Oct 2021 17:44:00 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="B/9+DC/t"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 7AA7E83545; Tue, 12 Oct 2021 17:43:42 +0200 (CEST) Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 44CB98356B for ; Tue, 12 Oct 2021 17:43:35 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dsankouski@gmail.com Received: by mail-wr1-x42e.google.com with SMTP id e3so34594963wrc.11 for ; Tue, 12 Oct 2021 08:43:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GbuqO82iXdLksUUNIwmIbo50Oehz94y4HoMpDDrKDec=; b=B/9+DC/teOoSdgDP0WJBOe8nyPhEz1rIjVkCUXabr8XCYqPqUSIa2CRI4QT6XAg4s6 BFJphxkPYr6fHGoFvkKrig9ORaAnGTeRRrDFUI9cujPqlPI3QVqzrXF5lCrfYD/kL+AI y8RybRx5y/RBrOOEBqcc/aXu9KvPp5EwaNxA6NbugNy+XU/u7kG7ywttmogOlDDwMzAt T15VlFz0h0fQo1Fh1E7a8/QTjCAjfTWgaqD9w19lCd9dfMq8TQp2ZALGc4juTGdPigeU dPd7b6TnR2T00Hacy5Bk7nxZqZobcVhiwImpqynW/thIrMALii2ObY/b6MwR0thbLOeQ TzUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GbuqO82iXdLksUUNIwmIbo50Oehz94y4HoMpDDrKDec=; b=gamX0jEpKsBtytO7TFbIiN48Pc4aimx7U6mfmQlMfgdJW4Ep0xPmBWSjulQ86vhf6D Z2ZH1MqsevjctPT6L7EKbjfeUOJEg+ZOxAzvFOjarw2gO32Ekx3xJaDRmi7NP3Ddvb3I SlyTBbCBjmJVtlIwj8h7kATz5RTPOJSGNWZvTOqi4453h75PUBCBUF7pf1eZmuoLVSqp WxRUyvi3kqD1KL64K4i9B5aOsTqeO2t0KLK+hW0e3LVLoZvAjneYrI55I2GqKSGJd2o/ rFZHjWVD6RVupcu85bSS0cJakFBYeAP/YGEX+FA6s2PRBLmfOBXQkyzMooKk0o89VuIL Vw3Q== X-Gm-Message-State: AOAM531X34FMWRh/AWnS/jdlq85GEei/G5lTZ6Fu/V5PLffZE8KcJs02 LgDvseq4aTi1gSO7DYtdMynafD44/IAqug== X-Google-Smtp-Source: ABdhPJxDk3n4/qQ52tY2Eht+WcgrIsDtXA8Y50cdRw5Anb6rPg434tLYUV61AhRdK7CA+fd7OKDOWQ== X-Received: by 2002:adf:c00a:: with SMTP id z10mr31680227wre.315.1634053414671; Tue, 12 Oct 2021 08:43:34 -0700 (PDT) Received: from localhost.localdomain ([46.216.16.109]) by smtp.gmail.com with ESMTPSA id z12sm2684089wmk.38.2021.10.12.08.43.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 08:43:34 -0700 (PDT) From: Dzmitry Sankouski To: u-boot@lists.denx.de Cc: Dzmitry Sankouski , Ramon Fried , Tom Rini Subject: [PATCH 4/6] clocks: qcom: add clocks for SDM845 debug uart Date: Tue, 12 Oct 2021 18:43:12 +0300 Message-Id: <20211012154314.20057-5-dsankouski@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211012154314.20057-1-dsankouski@gmail.com> References: <20211012154314.20057-1-dsankouski@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Allows to change clock frequency of debug uart, thus supporting wide range of baudrates. Enable / disable functionality is not implemented yet. In most use cases of SDM845 (i.e. mobile phones and tablets) it's not needed, because qualcomm first stage bootloader leaves it initialized, and on the other hand there's no possibility to replace signed first stage bootloader with u-boot. Signed-off-by: Dzmitry Sankouski Cc: Ramon Fried Cc: Tom Rini --- arch/arm/mach-snapdragon/clock-sdm845.c | 92 +++++++++++++++++++++ arch/arm/mach-snapdragon/clock-snapdragon.c | 1 + arch/arm/mach-snapdragon/clock-snapdragon.h | 3 +- 3 files changed, 95 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-snapdragon/clock-sdm845.c diff --git a/arch/arm/mach-snapdragon/clock-sdm845.c b/arch/arm/mach-snapdragon/clock-sdm845.c new file mode 100644 index 0000000000..9572639238 --- /dev/null +++ b/arch/arm/mach-snapdragon/clock-sdm845.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Clock drivers for Qualcomm SDM845 + * + * (C) Copyright 2017 Jorge Ramirez Ortiz + * (C) Copyright 2021 Dzmitry Sankouski + * + * Based on Little Kernel driver, simplified + */ + +#include +#include +#include +#include +#include +#include +#include "clock-snapdragon.h" + +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } + +struct freq_tbl { + uint freq; + uint src; + u8 pre_div; + u16 m; + u16 n; +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { + F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625), + F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625), + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625), + F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75), + F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25), + F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75), + F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15), + F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25), + F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0), + F(102400000, CFG_CLK_SRC_GPLL0_EVEN, 1, 128, 375), + F(112000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 28, 75), + F(117964800, CFG_CLK_SRC_GPLL0_EVEN, 1, 6144, 15625), + F(120000000, CFG_CLK_SRC_GPLL0_EVEN, 2.5, 0, 0), + F(128000000, CFG_CLK_SRC_GPLL0, 1, 16, 75), + { } +}; + +static const struct bcr_regs uart2_regs = { + .cfg_rcgr = SE9_UART_APPS_CFG_RCGR, + .cmd_rcgr = SE9_UART_APPS_CMD_RCGR, + .M = SE9_UART_APPS_M, + .N = SE9_UART_APPS_N, + .D = SE9_UART_APPS_D, +}; + +const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate) +{ + if (!f) + return NULL; + + if (!f->freq) + return f; + + for (; f->freq; f++) + if (rate <= f->freq) + return f; + + /* Default to our fastest rate */ + return f - 1; +} + +static int clk_init_uart(struct msm_clk_priv *priv, uint rate) +{ + const struct freq_tbl *freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate); + + clk_rcg_set_rate_mnd(priv->base, &uart2_regs, + freq->pre_div, freq->m, freq->n, freq->src); + + return 0; +} + +ulong msm_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case 0x58: /*UART2*/ + return clk_init_uart(priv, rate); + default: + return 0; + } +} diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c index 2b76371718..3deb08ac4a 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.c +++ b/arch/arm/mach-snapdragon/clock-snapdragon.c @@ -135,6 +135,7 @@ static const struct udevice_id msm_clk_ids[] = { { .compatible = "qcom,gcc-apq8016" }, { .compatible = "qcom,gcc-msm8996" }, { .compatible = "qcom,gcc-apq8096" }, + { .compatible = "qcom,gcc-sdm845" }, { } }; diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.h b/arch/arm/mach-snapdragon/clock-snapdragon.h index 58fab40a2e..2ac53b538d 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.h +++ b/arch/arm/mach-snapdragon/clock-snapdragon.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Qualcomm APQ8016, APQ8096 + * Qualcomm APQ8016, APQ8096, SDM845 * * (C) Copyright 2017 Jorge Ramirez-Ortiz */ @@ -9,6 +9,7 @@ #define CFG_CLK_SRC_CXO (0 << 8) #define CFG_CLK_SRC_GPLL0 (1 << 8) +#define CFG_CLK_SRC_GPLL0_EVEN (6 << 8) #define CFG_CLK_SRC_MASK (7 << 8) struct pll_vote_clk { -- 2.20.1