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Fri, 15 Oct 2021 00:51:11 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; lists.freedesktop.org; dkim=none (message not signed) header.d=none;lists.freedesktop.org; dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT021.mail.protection.outlook.com (10.13.175.51) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4608.15 via Frontend Transport; Fri, 15 Oct 2021 00:51:11 +0000 Received: from localhost.localdomain.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.8; Thu, 14 Oct 2021 19:51:06 -0500 From: Luben Tuikov To: CC: Luben Tuikov , Alex Deucher , Lijo Lazar Subject: [PATCH 4/5] dpm/amd/pm: Sienna: 0 MHz is not a current clock frequency (v2) Date: Thu, 14 Oct 2021 20:50:45 -0400 Message-ID: <20211015005046.43486-5-luben.tuikov@amd.com> X-Mailer: git-send-email 2.33.1.558.g2bd2f258f4 In-Reply-To: <20211015005046.43486-1-luben.tuikov@amd.com> References: <20211015005046.43486-1-luben.tuikov@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ad3fabd1-3612-4b70-96d4-08d98f75e1f8 X-MS-TrafficTypeDiagnostic: MN2PR12MB4357: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1923; 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CAT:NONE; SFS:(4636009)(36840700001)(46966006)(44832011)(1076003)(336012)(6666004)(54906003)(8936002)(186003)(36756003)(26005)(508600001)(4326008)(83380400001)(426003)(356005)(7696005)(70206006)(2906002)(16526019)(86362001)(6916009)(36860700001)(82310400003)(316002)(81166007)(8676002)(47076005)(2616005)(5660300002)(70586007)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Oct 2021 00:51:11.2038 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ad3fabd1-3612-4b70-96d4-08d98f75e1f8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT021.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4357 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" A current value of a clock frequency of 0, means that the IP block is in some kind of low power state. Ignore it and don't report it here. Here we only report the possible operating (non-zero) frequencies of the block requested. So, if the current clock value is 0, then print the DPM frequencies, but don't report a current value. v2: Don't report the minimum one as the current one when reported one is 0, i.e. don't add an asterisk (Lijo). LT: It is conceivable that this may confuse user-mode tools if they scan and look for a current one, i.e. look for an asterisk, but they'll have to adapt and use other methods for finding power states of the chip--we can't report 0 as current. Cc: Alex Deucher Cc: Lijo Lazar Signed-off-by: Luben Tuikov --- .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 60 ++++++++++++------- 1 file changed, 40 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index f630d5e928ccfe..6fe792be77dbbb 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -1040,7 +1040,8 @@ static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_tabl } static int sienna_cichlid_print_clk_levels(struct smu_context *smu, - enum smu_clk_type clk_type, char *buf) + enum smu_clk_type clk_type, + char *buf) { struct amdgpu_device *adev = smu->adev; struct smu_table_context *table_context = &smu->smu_table; @@ -1052,12 +1053,12 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu, OverDriveTable_t *od_table = (OverDriveTable_t *)table_context->overdrive_table; int i, size = 0, ret = 0; - uint32_t curr_value = 0, value = 0, count = 0; + uint32_t curr_value, value, count; uint32_t freq_value[3] = {0, 0, 0}; - uint32_t mark_index = 0; uint32_t gen_speed, lane_width; uint32_t min_value, max_value; uint32_t smu_version; + bool fine_grained; smu_cmn_get_sysfs_buf(&buf, &size); @@ -1077,6 +1078,20 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu, if (ret) goto print_clk_out; + ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, + &freq_value[0]); + if (ret) + goto print_clk_out; + + /* A current value of a clock frequency of 0, means + * that the IP block is in some kind of low power + * state. Ignore it and don't report it here. Here we + * only report the possible operating (non-zero) + * frequencies of the block requested. So, if the + * current clock value is 0, then we don't report a + * "current" value from the DPM states, i.e. we don't + * add an asterisk. + */ /* no need to disable gfxoff when retrieving the current gfxclk */ if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK)) @@ -1086,38 +1101,43 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu, if (ret) goto print_clk_out; - if (!sienna_cichlid_supports_fine_grained_dpm(smu, clk_type)) { - for (i = 0; i < count; i++) { + fine_grained = sienna_cichlid_supports_fine_grained_dpm(smu, clk_type); + if (!fine_grained) { + /* We already got the 0-th index--print it + * here and continue thereafter. + */ + size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 0, freq_value[0], + curr_value == freq_value[0] ? "*" : ""); + for (i = 1; i < count; i++) { ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value); if (ret) goto print_clk_out; - size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, curr_value == value ? "*" : ""); } } else { - ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_value[0]); - if (ret) - goto print_clk_out; + freq_value[1] = curr_value ?: freq_value[0]; ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_value[2]); if (ret) goto print_clk_out; - freq_value[1] = curr_value; - mark_index = curr_value == freq_value[0] ? 0 : - curr_value == freq_value[2] ? 2 : 1; - - count = 3; - if (mark_index != 1) { + if (freq_value[1] == freq_value[0]) { + i = 1; + count = 3; + } else if (freq_value[1] == freq_value[2]) { + i = 0; count = 2; - freq_value[1] = freq_value[2]; + } else { + i = 0; + count = 3; } - for (i = 0; i < count; i++) { - size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_value[i], - curr_value == freq_value[i] ? "*" : ""); + for ( ; i < count; i++) { + size += sysfs_emit_at(buf, size, + "%d: %uMhz %s\n", + i, freq_value[i], + curr_value == freq_value[i] ? "*" : ""); } - } break; case SMU_PCIE: -- 2.33.1.558.g2bd2f258f4