From: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
To: <lukma@denx.de>, <sjg@chromium.org>, <trini@konsulko.com>,
<mr.nuke.me@gmail.com>, <u-boot@lists.denx.de>
Cc: <joel@jms.id.au>, <ryan_chen@aspeedtech.com>,
<johnny_huang@aspeedtech.com>
Subject: [PATCH next v6 03/12] clk: ast2600: Add YCLK control for HACE
Date: Fri, 15 Oct 2021 10:03:28 +0800 [thread overview]
Message-ID: <20211015020337.1024-4-chiawei_wang@aspeedtech.com> (raw)
In-Reply-To: <20211015020337.1024-1-chiawei_wang@aspeedtech.com>
From: Joel Stanley <joel@jms.id.au>
Add YCLK enable for HACE, the HW hash engine of
ASPEED AST2600 SoCs.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
---
.../arm/include/asm/arch-aspeed/scu_ast2600.h | 5 +++--
drivers/clk/aspeed/clk_ast2600.c | 20 +++++++++++++++++++
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2600.h b/arch/arm/include/asm/arch-aspeed/scu_ast2600.h
index a205fb1f76..d7b500f656 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2600.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2600.h
@@ -10,8 +10,9 @@
#define SCU_CLKGATE1_EMMC BIT(27)
#define SCU_CLKGATE1_MAC2 BIT(21)
#define SCU_CLKGATE1_MAC1 BIT(20)
-#define SCU_CLKGATE1_USB_HUB BIT(14)
-#define SCU_CLKGATE1_USB_HOST2 BIT(7)
+#define SCU_CLKGATE1_USB_HUB BIT(14)
+#define SCU_CLKGATE1_HACE BIT(13)
+#define SCU_CLKGATE1_USB_HOST2 BIT(7)
#define SCU_CLKGATE2_FSI BIT(30)
#define SCU_CLKGATE2_MAC4 BIT(21)
diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c
index 3a92739f5c..69128fd3c4 100644
--- a/drivers/clk/aspeed/clk_ast2600.c
+++ b/drivers/clk/aspeed/clk_ast2600.c
@@ -1013,6 +1013,23 @@ static ulong ast2600_enable_usbbhclk(struct ast2600_scu *scu)
return 0;
}
+static ulong ast2600_enable_haceclk(struct ast2600_scu *scu)
+{
+ uint32_t reset_bit;
+ uint32_t clkgate_bit;
+
+ reset_bit = BIT(ASPEED_RESET_HACE);
+ clkgate_bit = SCU_CLKGATE1_HACE;
+
+ writel(reset_bit, &scu->modrst_ctrl1);
+ udelay(100);
+ writel(clkgate_bit, &scu->clkgate_clr1);
+ mdelay(20);
+ writel(reset_bit, &scu->modrst_clr1);
+
+ return 0;
+}
+
static int ast2600_clk_enable(struct clk *clk)
{
struct ast2600_clk_priv *priv = dev_get_priv(clk->dev);
@@ -1051,6 +1068,9 @@ static int ast2600_clk_enable(struct clk *clk)
case ASPEED_CLK_GATE_USBPORT2CLK:
ast2600_enable_usbbhclk(priv->scu);
break;
+ case ASPEED_CLK_GATE_YCLK:
+ ast2600_enable_haceclk(priv->scu);
+ break;
default:
pr_err("can't enable clk\n");
return -ENOENT;
--
2.17.1
next prev parent reply other threads:[~2021-10-15 2:04 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-15 2:03 [PATCH next v6 00/12] aspeed: Support secure boot chain with FIT image verification Chia-Wei Wang
2021-10-15 2:03 ` [PATCH next v6 01/12] image: fit: Fix parameter name for hash algorithm Chia-Wei Wang
2021-10-15 2:03 ` [PATCH next v6 02/12] aspeed: ast2600: Enlarge SRAM size Chia-Wei Wang
2021-10-15 2:03 ` Chia-Wei Wang [this message]
2021-10-15 2:03 ` [PATCH next v6 04/12] crypto: aspeed: Add AST2600 HACE support Chia-Wei Wang
2021-10-15 2:03 ` [PATCH next v6 05/12] ARM: dts: ast2600: Add HACE to device tree Chia-Wei Wang
2021-10-15 2:03 ` [PATCH next v6 06/12] clk: ast2600: Add RSACLK control for ACRY Chia-Wei Wang
2021-10-15 2:03 ` [PATCH next v6 07/12] crypto: aspeed: Add AST2600 ACRY support Chia-Wei Wang
2021-10-18 3:06 ` ChiaWei Wang
2021-10-15 2:03 ` [PATCH next v6 08/12] ARM: dts: ast2600: Add ACRY to device tree Chia-Wei Wang
2021-10-15 2:03 ` [PATCH next v6 09/12] ast2600: spl: Locate load buffer in DRAM space Chia-Wei Wang
2021-10-15 2:03 ` [PATCH next v6 10/12] configs: ast2600-evb: Enable SPL FIT support Chia-Wei Wang
2021-10-15 2:03 ` [PATCH next v6 11/12] configs: aspeed: Make EXTRA_ENV_SETTINGS board specific Chia-Wei Wang
2021-10-15 2:03 ` [PATCH next v6 12/12] configs: ast2600: Boot kernel FIT in DRAM Chia-Wei Wang
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