From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03112C433EF for ; Sun, 17 Oct 2021 10:45:19 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4248E60EBD for ; Sun, 17 Oct 2021 10:45:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 4248E60EBD Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id D35A8833E6; Sun, 17 Oct 2021 12:45:03 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="cijazMjk"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 322088316B; Sun, 17 Oct 2021 12:44:54 +0200 (CEST) Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 3342283321 for ; Sun, 17 Oct 2021 12:44:45 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dsankouski@gmail.com Received: by mail-ed1-x532.google.com with SMTP id d3so58048170edp.3 for ; Sun, 17 Oct 2021 03:44:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GbuqO82iXdLksUUNIwmIbo50Oehz94y4HoMpDDrKDec=; b=cijazMjkSzj/r5RN4E7v2ePPlrWzo36PLK2GZFrlIkUg6klkzl1PY+TpIC3iJVL90X CE3IWd/Fecy4f8eCKElRQ8LObKw52SPCLUhpZ7ESoGpI24r9GBcN//A3JYlcLRmZKjwd ujY2u9rzJCGMmtQFEIUIY2vBG4aawz/zhlK/QCm3O9QyQWWJFliEBgjmaIwGGitjSCPz 3gXagaLaCyI2uw5EB4OyN88KQyScZRU+nkz89T0hxVI+W/Umjx/WKdN5espJpI+Why5Y hk6Owctx7f4T5m+Y7poK62uP7aqGdMXXjnl0+z6p3xTvxDoYYsZik/8lFdky45AU+mbZ /S8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GbuqO82iXdLksUUNIwmIbo50Oehz94y4HoMpDDrKDec=; b=Hyg+mRy5Hi47lHhRsMz1T6jlQs5nnyYEH8HCvz+7MENF6t/5HqPRskG7h0Gz7jOPzJ YJWlJ6TZ5JY6bfG9aUQZIqtOGYkTkpwi5vrMVatyfOicJ+JvY4OaKj266dKyXYWGSQvz ngw7RSYmYNCTOG9cyYN1f5VQkl0qNV2guH7J+NwqmE2uVvfGrdMzuxt2w/ilmb3ApmLz gLwF1LSbCX/BfcamkW8c/HGChw7yIuk74JlbIrbS3MRr8GSnXU+k3WbG9gu3hYMwTBpm XrDDwfNTDOHQZLd8Lfi1AEtkIHFcxFYrKnvA30Gmf6Ns+tP1ZImCvKWB20LXpFcv4W7Q TZMA== X-Gm-Message-State: AOAM5304x12y8SQyxY+wQqXMJ/8k+iE61MrUR8sxrD9VbhDjyxD5Vxj6 HINNTmzvxqVrOjgf0/GEMmCRKHqtkquugA== X-Google-Smtp-Source: ABdhPJw6g9oQMWnO7Fi7RkdksaivY4FS3e/baVmwjVJIebRdDBiwo2QDU0rWWMspBvz9OBQEYakVXA== X-Received: by 2002:a17:906:7632:: with SMTP id c18mr22484570ejn.317.1634467484662; Sun, 17 Oct 2021 03:44:44 -0700 (PDT) Received: from localhost.localdomain ([46.216.16.109]) by smtp.gmail.com with ESMTPSA id c6sm7267607ejb.41.2021.10.17.03.44.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Oct 2021 03:44:44 -0700 (PDT) From: Dzmitry Sankouski To: u-boot@lists.denx.de Cc: Dzmitry Sankouski , Ramon Fried , Tom Rini Subject: [PATCH 4/6] clocks: qcom: add clocks for SDM845 debug uart Date: Sun, 17 Oct 2021 13:44:30 +0300 Message-Id: <20211017104432.3703-5-dsankouski@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211017104432.3703-1-dsankouski@gmail.com> References: <20211017104432.3703-1-dsankouski@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Allows to change clock frequency of debug uart, thus supporting wide range of baudrates. Enable / disable functionality is not implemented yet. In most use cases of SDM845 (i.e. mobile phones and tablets) it's not needed, because qualcomm first stage bootloader leaves it initialized, and on the other hand there's no possibility to replace signed first stage bootloader with u-boot. Signed-off-by: Dzmitry Sankouski Cc: Ramon Fried Cc: Tom Rini --- arch/arm/mach-snapdragon/clock-sdm845.c | 92 +++++++++++++++++++++ arch/arm/mach-snapdragon/clock-snapdragon.c | 1 + arch/arm/mach-snapdragon/clock-snapdragon.h | 3 +- 3 files changed, 95 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-snapdragon/clock-sdm845.c diff --git a/arch/arm/mach-snapdragon/clock-sdm845.c b/arch/arm/mach-snapdragon/clock-sdm845.c new file mode 100644 index 0000000000..9572639238 --- /dev/null +++ b/arch/arm/mach-snapdragon/clock-sdm845.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Clock drivers for Qualcomm SDM845 + * + * (C) Copyright 2017 Jorge Ramirez Ortiz + * (C) Copyright 2021 Dzmitry Sankouski + * + * Based on Little Kernel driver, simplified + */ + +#include +#include +#include +#include +#include +#include +#include "clock-snapdragon.h" + +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } + +struct freq_tbl { + uint freq; + uint src; + u8 pre_div; + u16 m; + u16 n; +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { + F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625), + F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625), + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625), + F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75), + F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25), + F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75), + F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15), + F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25), + F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0), + F(102400000, CFG_CLK_SRC_GPLL0_EVEN, 1, 128, 375), + F(112000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 28, 75), + F(117964800, CFG_CLK_SRC_GPLL0_EVEN, 1, 6144, 15625), + F(120000000, CFG_CLK_SRC_GPLL0_EVEN, 2.5, 0, 0), + F(128000000, CFG_CLK_SRC_GPLL0, 1, 16, 75), + { } +}; + +static const struct bcr_regs uart2_regs = { + .cfg_rcgr = SE9_UART_APPS_CFG_RCGR, + .cmd_rcgr = SE9_UART_APPS_CMD_RCGR, + .M = SE9_UART_APPS_M, + .N = SE9_UART_APPS_N, + .D = SE9_UART_APPS_D, +}; + +const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate) +{ + if (!f) + return NULL; + + if (!f->freq) + return f; + + for (; f->freq; f++) + if (rate <= f->freq) + return f; + + /* Default to our fastest rate */ + return f - 1; +} + +static int clk_init_uart(struct msm_clk_priv *priv, uint rate) +{ + const struct freq_tbl *freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate); + + clk_rcg_set_rate_mnd(priv->base, &uart2_regs, + freq->pre_div, freq->m, freq->n, freq->src); + + return 0; +} + +ulong msm_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case 0x58: /*UART2*/ + return clk_init_uart(priv, rate); + default: + return 0; + } +} diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c index 2b76371718..3deb08ac4a 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.c +++ b/arch/arm/mach-snapdragon/clock-snapdragon.c @@ -135,6 +135,7 @@ static const struct udevice_id msm_clk_ids[] = { { .compatible = "qcom,gcc-apq8016" }, { .compatible = "qcom,gcc-msm8996" }, { .compatible = "qcom,gcc-apq8096" }, + { .compatible = "qcom,gcc-sdm845" }, { } }; diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.h b/arch/arm/mach-snapdragon/clock-snapdragon.h index 58fab40a2e..2ac53b538d 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.h +++ b/arch/arm/mach-snapdragon/clock-snapdragon.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Qualcomm APQ8016, APQ8096 + * Qualcomm APQ8016, APQ8096, SDM845 * * (C) Copyright 2017 Jorge Ramirez-Ortiz */ @@ -9,6 +9,7 @@ #define CFG_CLK_SRC_CXO (0 << 8) #define CFG_CLK_SRC_GPLL0 (1 << 8) +#define CFG_CLK_SRC_GPLL0_EVEN (6 << 8) #define CFG_CLK_SRC_MASK (7 << 8) struct pll_vote_clk { -- 2.20.1