From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A449DC433F5 for ; Mon, 18 Oct 2021 01:14:43 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2F39560F25 for ; Mon, 18 Oct 2021 01:14:43 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 2F39560F25 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:38584 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcHEg-0002PQ-71 for qemu-devel@archiver.kernel.org; Sun, 17 Oct 2021 21:14:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48094) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcH2f-0006no-T9; Sun, 17 Oct 2021 21:02:21 -0400 Received: from mail-ua1-x933.google.com ([2607:f8b0:4864:20::933]:39680) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mcH2d-000257-GJ; Sun, 17 Oct 2021 21:02:17 -0400 Received: by mail-ua1-x933.google.com with SMTP id f3so4748285uap.6; Sun, 17 Oct 2021 18:02:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eRE1vTD16G0zofRanu6U3rQerdaIrRMjzzaKnlikiUo=; b=VXNsYwc78bRZeAh+SZ4oQ0M7lFz7Wl1xvdubceD6p0mQ5sOHUcY8iJ//qZTVdmcJJg 31yq3pqetOYU8KzUFVqHmrET6p91MWD21IOmF/h4Z4ILCLubF1ASND9VSEy1F2RQc4UE TyqE0flIQOBRRv2hmMsHLOsTUusw6xLQNFbFVTpuJRkOov9FOVm7gL+5HkEFJh0QMdko 8d2aR89ZQ0lyFgBHQDTdcLIZZIts5hKXWbbiwtAGLK4Tuz9KhlqCjfnjDrjUfropU3kB 2ckTwsP32JzVGNVUhcTHf3G9coZtLIGPqqU7sj6bDdpkmMC+kmDamE0BmKa8v1VjwGJE ASKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eRE1vTD16G0zofRanu6U3rQerdaIrRMjzzaKnlikiUo=; b=NhN9myx1QIxa1IgKGnvtupRMmSkvjdxymoOabwEKcCyPtnZN+fF6I53/VK8aSvX0NZ L4G4ZlSE3WkPFtEY5S4Daymk1Pm5VGMDXAxBkJ7nhHEWcugs2zxuB2vS1aUbVhCAc2Ca Zinw+7QDy+tOpZT+g5eu+f6EDQ2w4M+fw48l0qRlulxxfbjzTECh8DALFNn4K6FbCFPX Bz53z7/krf6E1soOkwM+v9U8NigutiBoPKsMPaPRzew5lXCC7kTML0qCw6w7epJpYcgd TxMvVD+ANhZ2oRA44pc390mrl3bVT7jYO+e/ib/Uxb8f8tTPVsqjs3NRmEPGA8mOvja1 G3EA== X-Gm-Message-State: AOAM530tyeKquOxyK5BQBt3Bc4o2vz5qTcvVMLpfEcH/AJG95B+SzmMB /LXvtaEPc9V+dMGc7DY23BJfrVGGTag= X-Google-Smtp-Source: ABdhPJyOsP5GK1O3YBtNJuOWLzshBZVAa6dFOzlwzDjGhTSTAhpDBAS2tuxoU0XuS7DvYBUyM6ZGBA== X-Received: by 2002:a05:6102:c01:: with SMTP id x1mr7053338vss.8.1634518934074; Sun, 17 Oct 2021 18:02:14 -0700 (PDT) Received: from rekt.COMFAST ([179.247.137.170]) by smtp.gmail.com with ESMTPSA id m15sm8271607vsh.31.2021.10.17.18.02.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Oct 2021 18:02:13 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v4 13/15] PPC64/TCG: Implement 'rfebb' instruction Date: Sun, 17 Oct 2021 22:01:31 -0300 Message-Id: <20211018010133.315842-14-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211018010133.315842-1-danielhb413@gmail.com> References: <20211018010133.315842-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::933; envelope-from=danielhb413@gmail.com; helo=mail-ua1-x933.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Henrique Barboza , richard.henderson@linaro.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" An Event-Based Branch (EBB) allows applications to change the NIA when a event-based exception occurs. Event-based exceptions are enabled by setting the Branch Event Status and Control Register (BESCR). If the event-based exception is enabled when the exception occurs, an EBB happens. The following operations happens during an EBB: - Global Enable (GE) bit of BESCR is set to 0; - bits 0-61 of the Event-Based Branch Return Register (EBBRR) are set to the the effective address of the NIA that would have executed if the EBB didn't happen; - Instruction fetch and execution will continue in the effective address contained in the Event-Based Branch Handler Register (EBBHR). The EBB Handler will process the event and then execute the Return From Event-Based Branch (rfebb) instruction. rfebb sets BESCR_GE and then redirects execution to the address pointed in EBBRR. This process is described in the PowerISA v3.1, Book II, Chapter 6 [1]. This patch implements the rfebb instruction. Descriptions of all relevant BESCR bits are also added - this patch is only using BESCR_GE, but the next patches will use the remaining bits. [1] https://wiki.raptorcs.com/w/images/f/f5/PowerISA_public.v3.1.pdf Reviewed-by: Matheus Ferst Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 13 ++++++++++ target/ppc/excp_helper.c | 31 ++++++++++++++++++++++++ target/ppc/helper.h | 1 + target/ppc/insn32.decode | 5 ++++ target/ppc/translate.c | 2 ++ target/ppc/translate/branch-impl.c.inc | 33 ++++++++++++++++++++++++++ 6 files changed, 85 insertions(+) create mode 100644 target/ppc/translate/branch-impl.c.inc diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 6f9a48a5a1..bccf135847 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -402,6 +402,19 @@ typedef struct PMUEvent { /* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */ #define CTRL_RUN PPC_BIT(63) +/* EBB/BESCR bits */ +/* Global Enable */ +#define BESCR_GE PPC_BIT(0) +/* External Event-based Exception Enable */ +#define BESCR_EE PPC_BIT(30) +/* Performance Monitor Event-based Exception Enable */ +#define BESCR_PME PPC_BIT(31) +/* External Event-based Exception Occurred */ +#define BESCR_EEO PPC_BIT(62) +/* Performance Monitor Event-based Exception Occurred */ +#define BESCR_PMEO PPC_BIT(63) +#define BESCR_INVALID PPC_BITMASK(32, 33) + /* LPCR bits */ #define LPCR_VPM0 PPC_BIT(0) #define LPCR_VPM1 PPC_BIT(1) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index b7d1767920..7be334e007 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1248,6 +1248,37 @@ void helper_hrfid(CPUPPCState *env) } #endif +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) +void helper_rfebb(CPUPPCState *env, target_ulong s) +{ + target_ulong msr = env->msr; + + /* + * Handling of BESCR bits 32:33 according to PowerISA v3.1: + * + * "If BESCR 32:33 != 0b00 the instruction is treated as if + * the instruction form were invalid." + */ + if (env->spr[SPR_BESCR] & BESCR_INVALID) { + raise_exception_err(env, POWERPC_EXCP_PROGRAM, + POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL); + } + + env->nip = env->spr[SPR_EBBRR]; + + /* Switching to 32-bit ? Crop the nip */ + if (!msr_is_64bit(env, msr)) { + env->nip = (uint32_t)env->spr[SPR_EBBRR]; + } + + if (s) { + env->spr[SPR_BESCR] |= BESCR_GE; + } else { + env->spr[SPR_BESCR] &= ~BESCR_GE; + } +} +#endif + /*****************************************************************************/ /* Embedded PowerPC specific helpers */ void helper_40x_rfci(CPUPPCState *env) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index b0ebfaff51..8bc38b5e4b 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -18,6 +18,7 @@ DEF_HELPER_2(pminsn, void, env, i32) DEF_HELPER_1(rfid, void, env) DEF_HELPER_1(rfscv, void, env) DEF_HELPER_1(hrfid, void, env) +DEF_HELPER_2(rfebb, void, env, tl) DEF_HELPER_2(store_lpcr, void, env, tl) DEF_HELPER_2(store_pcr, void, env, tl) DEF_HELPER_2(store_mmcr0, void, env, tl) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 9fd8d6b817..deb7374ea4 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -124,3 +124,8 @@ SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi ## Vector Bit Manipulation Instruction VCFUGED 000100 ..... ..... ..... 10101001101 @VX + +### rfebb +&XL_s s:uint8_t +@XL_s ......-------------- s:1 .......... - &XL_s +RFEBB 010011-------------- . 0010010010 - @XL_s diff --git a/target/ppc/translate.c b/target/ppc/translate.c index e2839883be..cdb1171b88 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7554,6 +7554,8 @@ static int times_4(DisasContext *ctx, int x) #include "translate/spe-impl.c.inc" +#include "translate/branch-impl.c.inc" + /* Handles lfdp, lxsd, lxssp */ static void gen_dform39(DisasContext *ctx) { diff --git a/target/ppc/translate/branch-impl.c.inc b/target/ppc/translate/branch-impl.c.inc new file mode 100644 index 0000000000..29cfa11854 --- /dev/null +++ b/target/ppc/translate/branch-impl.c.inc @@ -0,0 +1,33 @@ +/* + * Power ISA decode for branch instructions + * + * Copyright IBM Corp. 2021 + * + * Authors: + * Daniel Henrique Barboza + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) + +static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg) +{ + REQUIRE_INSNS_FLAGS2(ctx, ISA207S); + + gen_icount_io_start(ctx); + gen_update_cfar(ctx, ctx->cia); + gen_helper_rfebb(cpu_env, cpu_gpr[arg->s]); + + ctx->base.is_jmp = DISAS_CHAIN; + + return true; +} +#else +static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg) +{ + gen_invalid(ctx); + return true; +} +#endif -- 2.31.1