* [Intel-gfx] [PATCH 0/9] drm/i915: Split plane updates to noarm+arm phases
@ 2021-10-18 11:50 Ville Syrjala
2021-10-18 11:50 ` [Intel-gfx] [PATCH 1/9] drm/i915: Reject planar formats when doing async flips Ville Syrjala
` (16 more replies)
0 siblings, 17 replies; 38+ messages in thread
From: Ville Syrjala @ 2021-10-18 11:50 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Write all non-arming double buffered plane registers ahead of
the vblank evade critical section. This reduces the amount of
work we have to inside the critical section and thus should
speed it up a bit.
I didn't convert cursors yet because IIRC they had some
intersting double buffering behaviours. Similar story with
skl+ scalers. Need to do further studies on those topics
to do this safely. For now we're left with a few TODOs.
Also tossed in a few async flip fixes at the start.
Ville Syrjälä (9):
drm/i915: Reject planar formats when doing async flips
drm/i915: Fix async flip with decryption and/or DPT
drm/i915: Fix up the sprite namespacing
drm/i915: Split update_plane() into update_noarm() + update_arm()
drm/i915: Split skl+ plane update into noarm+arm pair
drm/i915: Split pre-skl primary plane update into noarm+arm pair
drm/i915: Split g4x+ sprite plane update into noarm+arm pair
drm/i915: Split ivb+ sprite plane update into noarm+arm pair
drm/i915: Split vlv/chv sprite plane update into noarm+arm pair
drivers/gpu/drm/i915/display/i9xx_plane.c | 72 +++---
.../gpu/drm/i915/display/intel_atomic_plane.c | 88 +++++--
.../gpu/drm/i915/display/intel_atomic_plane.h | 23 +-
drivers/gpu/drm/i915/display/intel_cursor.c | 44 ++--
drivers/gpu/drm/i915/display/intel_display.c | 18 +-
.../drm/i915/display/intel_display_types.h | 12 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 214 +++++++++++-------
.../drm/i915/display/skl_universal_plane.c | 150 +++++++-----
drivers/gpu/drm/i915/i915_trace.h | 33 ++-
9 files changed, 431 insertions(+), 223 deletions(-)
--
2.32.0
^ permalink raw reply [flat|nested] 38+ messages in thread
* [Intel-gfx] [PATCH 1/9] drm/i915: Reject planar formats when doing async flips
2021-10-18 11:50 [Intel-gfx] [PATCH 0/9] drm/i915: Split plane updates to noarm+arm phases Ville Syrjala
@ 2021-10-18 11:50 ` Ville Syrjala
2021-10-27 16:12 ` Lisovskiy, Stanislav
2021-10-18 11:50 ` [Intel-gfx] [PATCH 2/9] drm/i915: Fix async flip with decryption and/or DPT Ville Syrjala
` (15 subsequent siblings)
16 siblings, 1 reply; 38+ messages in thread
From: Ville Syrjala @ 2021-10-18 11:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Karthik B S
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Async flips are only capable of changing PLANE_SURF, hence we
they can't easily be used with planar formats.
Older platforms could require updating AUX_DIST as well, which
is not possible. We'd have to make sure AUX_DIST doesn't change
before allowing the async flip through. If we could get async
flips with CCS then that might be interesting, but since the hw
doesn't allow async flips with CCS I don't see much point in
allowing this for planar formats either. No one renders their
game content in YUV anyway.
icl+ could in theory do this I suppose since each color plane
has its own PLANE_SURF register, but I don't know if there is
some magic to guarantee that both the Y and UV plane would
async flip synchronously if you will. Ie. beyond just a clean
tear we'd potentially get some kind of weird tear with some
random mix of luma and chroma from the old and new frames.
So let's just say no to async flips when scanning out planar
formats.
Cc: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ce5d6633029a..8bb87e839f4a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8884,6 +8884,12 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
return -EINVAL;
}
+ if (new_plane_state->hw.fb->format->num_planes > 1) {
+ drm_dbg_kms(&i915->drm,
+ "Planar formats not supported with async flips\n");
+ return -EINVAL;
+ }
+
if (old_plane_state->view.color_plane[0].stride !=
new_plane_state->view.color_plane[0].stride) {
drm_dbg_kms(&i915->drm, "Stride cannot be changed in async flip\n");
--
2.32.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Intel-gfx] [PATCH 2/9] drm/i915: Fix async flip with decryption and/or DPT
2021-10-18 11:50 [Intel-gfx] [PATCH 0/9] drm/i915: Split plane updates to noarm+arm phases Ville Syrjala
2021-10-18 11:50 ` [Intel-gfx] [PATCH 1/9] drm/i915: Reject planar formats when doing async flips Ville Syrjala
@ 2021-10-18 11:50 ` Ville Syrjala
2021-11-03 18:39 ` Lisovskiy, Stanislav
2021-10-18 11:50 ` [Intel-gfx] [PATCH 3/9] drm/i915: Fix up the sprite namespacing Ville Syrjala
` (14 subsequent siblings)
16 siblings, 1 reply; 38+ messages in thread
From: Ville Syrjala @ 2021-10-18 11:50 UTC (permalink / raw)
To: intel-gfx
Cc: Anshuman Gupta, Daniele Ceraolo Spurio, Juston Li, Rodrigo Vivi,
Uma Shankar, Karthik B S
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We're currently forgetting to set the PLANE_SURF_DECRYPT
flag in the async flip path. So if the hardware were to
latch that bit despite this being an async flip we'd start
scanning out garbage. And if it doesn't latch it then I
guess we'd just end up with a weird register value that
doesn't actually match the hardware state, which isn't
great for anyone starting at register dumps.
Similarly the async flip path also forgets to call
skl_surf_address() which means the DPT address space to
GGTT address space downshift is not being applied to
the offset. Which means we are pointing PLANE_SURF
at some random location in GGTT instead of the correct
DPT page.
So let's fix two birds with one stone and extract the
PLANE_SURF calculation from skl_program_plane() into
a small helper and use it in the async flip path as well.
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Juston Li <juston.li@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/skl_universal_plane.c | 30 ++++++++++++-------
1 file changed, 20 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 7444b88829ea..e2f024449149 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1011,6 +1011,20 @@ static u32 skl_surf_address(const struct intel_plane_state *plane_state,
}
}
+static u32 skl_plane_surf(const struct intel_plane_state *plane_state,
+ int color_plane)
+{
+ u32 plane_surf;
+
+ plane_surf = intel_plane_ggtt_offset(plane_state) +
+ skl_surf_address(plane_state, color_plane);
+
+ if (plane_state->decrypt)
+ plane_surf |= PLANE_SURF_DECRYPT;
+
+ return plane_surf;
+}
+
static void icl_plane_csc_load_black(struct intel_plane *plane)
{
struct drm_i915_private *i915 = to_i915(plane->base.dev);
@@ -1045,7 +1059,6 @@ skl_program_plane(struct intel_plane *plane,
enum plane_id plane_id = plane->id;
enum pipe pipe = plane->pipe;
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
- u32 surf_addr = skl_surf_address(plane_state, color_plane);
u32 stride = skl_plane_stride(plane_state, color_plane);
const struct drm_framebuffer *fb = plane_state->hw.fb;
int aux_plane = skl_main_to_aux_plane(fb, color_plane);
@@ -1058,7 +1071,7 @@ skl_program_plane(struct intel_plane *plane,
u8 alpha = plane_state->hw.alpha >> 8;
u32 plane_color_ctl = 0, aux_dist = 0;
unsigned long irqflags;
- u32 keymsk, keymax, plane_surf;
+ u32 keymsk, keymax;
u32 plane_ctl = plane_state->ctl;
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
@@ -1084,16 +1097,13 @@ skl_program_plane(struct intel_plane *plane,
}
if (aux_plane) {
- aux_dist = skl_surf_address(plane_state, aux_plane) - surf_addr;
+ aux_dist = skl_surf_address(plane_state, aux_plane) -
+ skl_surf_address(plane_state, color_plane);
if (DISPLAY_VER(dev_priv) < 12)
aux_dist |= skl_plane_stride(plane_state, aux_plane);
}
- plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
- if (plane_state->decrypt)
- plane_surf |= PLANE_SURF_DECRYPT;
-
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
/*
@@ -1157,7 +1167,8 @@ skl_program_plane(struct intel_plane *plane,
* the control register just before the surface register.
*/
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
- intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
+ intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
+ skl_plane_surf(plane_state, color_plane));
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
@@ -1172,7 +1183,6 @@ skl_plane_async_flip(struct intel_plane *plane,
unsigned long irqflags;
enum plane_id plane_id = plane->id;
enum pipe pipe = plane->pipe;
- u32 surf_addr = plane_state->view.color_plane[0].offset;
u32 plane_ctl = plane_state->ctl;
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
@@ -1184,7 +1194,7 @@ skl_plane_async_flip(struct intel_plane *plane,
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
- intel_plane_ggtt_offset(plane_state) + surf_addr);
+ skl_plane_surf(plane_state, 0));
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
--
2.32.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Intel-gfx] [PATCH 3/9] drm/i915: Fix up the sprite namespacing
2021-10-18 11:50 [Intel-gfx] [PATCH 0/9] drm/i915: Split plane updates to noarm+arm phases Ville Syrjala
2021-10-18 11:50 ` [Intel-gfx] [PATCH 1/9] drm/i915: Reject planar formats when doing async flips Ville Syrjala
2021-10-18 11:50 ` [Intel-gfx] [PATCH 2/9] drm/i915: Fix async flip with decryption and/or DPT Ville Syrjala
@ 2021-10-18 11:50 ` Ville Syrjala
2021-11-03 18:47 ` Lisovskiy, Stanislav
2021-10-18 11:50 ` [Intel-gfx] [PATCH 4/9] drm/i915: Split update_plane() into update_noarm() + update_arm() Ville Syrjala
` (13 subsequent siblings)
16 siblings, 1 reply; 38+ messages in thread
From: Ville Syrjala @ 2021-10-18 11:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Stanislav Lisovskiy
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Give all sprite exclusive functions/etc. a proper namespace.
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 106 ++++++++++----------
1 file changed, 53 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 08116f41da26..1daa3360cf02 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -118,7 +118,7 @@ static void i9xx_plane_linear_gamma(u16 gamma[8])
}
static void
-chv_update_csc(const struct intel_plane_state *plane_state)
+chv_sprite_update_csc(const struct intel_plane_state *plane_state)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
@@ -190,7 +190,7 @@ chv_update_csc(const struct intel_plane_state *plane_state)
#define COS_0 1
static void
-vlv_update_clrc(const struct intel_plane_state *plane_state)
+vlv_sprite_update_clrc(const struct intel_plane_state *plane_state)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
@@ -393,7 +393,7 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
return sprctl;
}
-static void vlv_update_gamma(const struct intel_plane_state *plane_state)
+static void vlv_sprite_update_gamma(const struct intel_plane_state *plane_state)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
@@ -417,9 +417,9 @@ static void vlv_update_gamma(const struct intel_plane_state *plane_state)
}
static void
-vlv_update_plane(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
+vlv_sprite_update(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
@@ -455,7 +455,7 @@ vlv_update_plane(struct intel_plane *plane,
intel_de_write_fw(dev_priv, SPCONSTALPHA(pipe, plane_id), 0);
if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
- chv_update_csc(plane_state);
+ chv_sprite_update_csc(plane_state);
if (key->flags) {
intel_de_write_fw(dev_priv, SPKEYMINVAL(pipe, plane_id),
@@ -478,15 +478,15 @@ vlv_update_plane(struct intel_plane *plane,
intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id),
intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
- vlv_update_clrc(plane_state);
- vlv_update_gamma(plane_state);
+ vlv_sprite_update_clrc(plane_state);
+ vlv_sprite_update_gamma(plane_state);
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
static void
-vlv_disable_plane(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state)
+vlv_sprite_disable(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
@@ -502,8 +502,8 @@ vlv_disable_plane(struct intel_plane *plane,
}
static bool
-vlv_plane_get_hw_state(struct intel_plane *plane,
- enum pipe *pipe)
+vlv_sprite_get_hw_state(struct intel_plane *plane,
+ enum pipe *pipe)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum intel_display_power_domain power_domain;
@@ -805,7 +805,7 @@ static void ivb_sprite_linear_gamma(const struct intel_plane_state *plane_state,
i++;
}
-static void ivb_update_gamma(const struct intel_plane_state *plane_state)
+static void ivb_sprite_update_gamma(const struct intel_plane_state *plane_state)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
@@ -835,9 +835,9 @@ static void ivb_update_gamma(const struct intel_plane_state *plane_state)
}
static void
-ivb_update_plane(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
+ivb_sprite_update(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
@@ -902,14 +902,14 @@ ivb_update_plane(struct intel_plane *plane,
intel_de_write_fw(dev_priv, SPRSURF(pipe),
intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
- ivb_update_gamma(plane_state);
+ ivb_sprite_update_gamma(plane_state);
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
static void
-ivb_disable_plane(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state)
+ivb_sprite_disable(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
@@ -927,8 +927,8 @@ ivb_disable_plane(struct intel_plane *plane,
}
static bool
-ivb_plane_get_hw_state(struct intel_plane *plane,
- enum pipe *pipe)
+ivb_sprite_get_hw_state(struct intel_plane *plane,
+ enum pipe *pipe)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum intel_display_power_domain power_domain;
@@ -1106,7 +1106,7 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
return dvscntr;
}
-static void g4x_update_gamma(const struct intel_plane_state *plane_state)
+static void g4x_sprite_update_gamma(const struct intel_plane_state *plane_state)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
@@ -1136,7 +1136,7 @@ static void ilk_sprite_linear_gamma(u16 gamma[17])
gamma[i] = (i << 10) / 16;
}
-static void ilk_update_gamma(const struct intel_plane_state *plane_state)
+static void ilk_sprite_update_gamma(const struct intel_plane_state *plane_state)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
@@ -1163,9 +1163,9 @@ static void ilk_update_gamma(const struct intel_plane_state *plane_state)
}
static void
-g4x_update_plane(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
+g4x_sprite_update(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
@@ -1224,16 +1224,16 @@ g4x_update_plane(struct intel_plane *plane,
intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
if (IS_G4X(dev_priv))
- g4x_update_gamma(plane_state);
+ g4x_sprite_update_gamma(plane_state);
else
- ilk_update_gamma(plane_state);
+ ilk_sprite_update_gamma(plane_state);
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
static void
-g4x_disable_plane(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state)
+g4x_sprite_disable(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
@@ -1250,8 +1250,8 @@ g4x_disable_plane(struct intel_plane *plane,
}
static bool
-g4x_plane_get_hw_state(struct intel_plane *plane,
- enum pipe *pipe)
+g4x_sprite_get_hw_state(struct intel_plane *plane,
+ enum pipe *pipe)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum intel_display_power_domain power_domain;
@@ -1567,7 +1567,7 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
return ret;
}
-static const u32 g4x_plane_formats[] = {
+static const u32 g4x_sprite_formats[] = {
DRM_FORMAT_XRGB8888,
DRM_FORMAT_YUYV,
DRM_FORMAT_YVYU,
@@ -1581,7 +1581,7 @@ static const u64 i9xx_plane_format_modifiers[] = {
DRM_FORMAT_MOD_INVALID
};
-static const u32 snb_plane_formats[] = {
+static const u32 snb_sprite_formats[] = {
DRM_FORMAT_XRGB8888,
DRM_FORMAT_XBGR8888,
DRM_FORMAT_XRGB2101010,
@@ -1594,7 +1594,7 @@ static const u32 snb_plane_formats[] = {
DRM_FORMAT_VYUY,
};
-static const u32 vlv_plane_formats[] = {
+static const u32 vlv_sprite_formats[] = {
DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
DRM_FORMAT_XRGB8888,
@@ -1762,9 +1762,9 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
return plane;
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- plane->update_plane = vlv_update_plane;
- plane->disable_plane = vlv_disable_plane;
- plane->get_hw_state = vlv_plane_get_hw_state;
+ plane->update_plane = vlv_sprite_update;
+ plane->disable_plane = vlv_sprite_disable;
+ plane->get_hw_state = vlv_sprite_get_hw_state;
plane->check_plane = vlv_sprite_check;
plane->max_stride = i965_plane_max_stride;
plane->min_cdclk = vlv_plane_min_cdclk;
@@ -1773,16 +1773,16 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
formats = chv_pipe_b_sprite_formats;
num_formats = ARRAY_SIZE(chv_pipe_b_sprite_formats);
} else {
- formats = vlv_plane_formats;
- num_formats = ARRAY_SIZE(vlv_plane_formats);
+ formats = vlv_sprite_formats;
+ num_formats = ARRAY_SIZE(vlv_sprite_formats);
}
modifiers = i9xx_plane_format_modifiers;
plane_funcs = &vlv_sprite_funcs;
} else if (DISPLAY_VER(dev_priv) >= 7) {
- plane->update_plane = ivb_update_plane;
- plane->disable_plane = ivb_disable_plane;
- plane->get_hw_state = ivb_plane_get_hw_state;
+ plane->update_plane = ivb_sprite_update;
+ plane->disable_plane = ivb_sprite_disable;
+ plane->get_hw_state = ivb_sprite_get_hw_state;
plane->check_plane = g4x_sprite_check;
if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
@@ -1793,28 +1793,28 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
plane->min_cdclk = ivb_sprite_min_cdclk;
}
- formats = snb_plane_formats;
- num_formats = ARRAY_SIZE(snb_plane_formats);
+ formats = snb_sprite_formats;
+ num_formats = ARRAY_SIZE(snb_sprite_formats);
modifiers = i9xx_plane_format_modifiers;
plane_funcs = &snb_sprite_funcs;
} else {
- plane->update_plane = g4x_update_plane;
- plane->disable_plane = g4x_disable_plane;
- plane->get_hw_state = g4x_plane_get_hw_state;
+ plane->update_plane = g4x_sprite_update;
+ plane->disable_plane = g4x_sprite_disable;
+ plane->get_hw_state = g4x_sprite_get_hw_state;
plane->check_plane = g4x_sprite_check;
plane->max_stride = g4x_sprite_max_stride;
plane->min_cdclk = g4x_sprite_min_cdclk;
modifiers = i9xx_plane_format_modifiers;
if (IS_SANDYBRIDGE(dev_priv)) {
- formats = snb_plane_formats;
- num_formats = ARRAY_SIZE(snb_plane_formats);
+ formats = snb_sprite_formats;
+ num_formats = ARRAY_SIZE(snb_sprite_formats);
plane_funcs = &snb_sprite_funcs;
} else {
- formats = g4x_plane_formats;
- num_formats = ARRAY_SIZE(g4x_plane_formats);
+ formats = g4x_sprite_formats;
+ num_formats = ARRAY_SIZE(g4x_sprite_formats);
plane_funcs = &g4x_sprite_funcs;
}
--
2.32.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Intel-gfx] [PATCH 4/9] drm/i915: Split update_plane() into update_noarm() + update_arm()
2021-10-18 11:50 [Intel-gfx] [PATCH 0/9] drm/i915: Split plane updates to noarm+arm phases Ville Syrjala
` (2 preceding siblings ...)
2021-10-18 11:50 ` [Intel-gfx] [PATCH 3/9] drm/i915: Fix up the sprite namespacing Ville Syrjala
@ 2021-10-18 11:50 ` Ville Syrjala
2021-10-27 16:35 ` Lisovskiy, Stanislav
2021-11-03 18:47 ` Lisovskiy, Stanislav
2021-10-18 11:50 ` [Intel-gfx] [PATCH 5/9] drm/i915: Split skl+ plane update into noarm+arm pair Ville Syrjala
` (12 subsequent siblings)
16 siblings, 2 replies; 38+ messages in thread
From: Ville Syrjala @ 2021-10-18 11:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Stanislav Lisovskiy
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The amount of plane registers we have to write has been steadily
increasing, putting more pressure on the vblank evasion mechanism
and forcing us to increase its time budget. Let's try to take some
of the pressure off by splitting plane updates into two parts:
1) write all non-self arming plane registers, ie. the registers
where the write actually does nothing until a separate arming
register is also written which will cause the hardware to latch
the new register values at the next start of vblank
2) write all self arming plane registers, ie. registers which always
just latch at the next start of vblank, and registers which also
arm other registers to do so
Here we just provide the mechanism, but don't actually implement
the split on any platform yet. so everything stays now in the _arm()
hooks. Subsequently we can move a whole bunch of stuff into the
_noarm() part, especially in more modern platforms where the number
of registers we have to write is also the greatest. On older
platforms this is less beneficial probably, but no real reason
to deviate from a common behaviour.
And let's sprinkle some TODOs around the areas that will need
adapting.
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 15 ++--
.../gpu/drm/i915/display/intel_atomic_plane.c | 88 ++++++++++++++-----
.../gpu/drm/i915/display/intel_atomic_plane.h | 23 +++--
drivers/gpu/drm/i915/display/intel_cursor.c | 44 +++++-----
drivers/gpu/drm/i915/display/intel_display.c | 12 +--
.../drm/i915/display/intel_display_types.h | 12 ++-
drivers/gpu/drm/i915/display/intel_sprite.c | 44 +++++-----
.../drm/i915/display/skl_universal_plane.c | 15 ++--
drivers/gpu/drm/i915/i915_trace.h | 33 ++++++-
9 files changed, 192 insertions(+), 94 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index b1439ba78f67..93163f9100a8 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -418,9 +418,10 @@ static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
return DIV_ROUND_UP(pixel_rate * num, den);
}
-static void i9xx_update_plane(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
+/* TODO: split into noarm+arm pair */
+static void i9xx_plane_update_arm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
@@ -493,8 +494,8 @@ static void i9xx_update_plane(struct intel_plane *plane,
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
-static void i9xx_disable_plane(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state)
+static void i9xx_plane_disable_arm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
@@ -851,8 +852,8 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
plane->max_stride = ilk_primary_max_stride;
}
- plane->update_plane = i9xx_update_plane;
- plane->disable_plane = i9xx_disable_plane;
+ plane->update_arm = i9xx_plane_update_arm;
+ plane->disable_arm = i9xx_plane_disable_arm;
plane->get_hw_state = i9xx_plane_get_hw_state;
plane->check_plane = i9xx_plane_check;
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 0be8c00e3db9..ae21770fc321 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -469,31 +469,72 @@ skl_next_plane_to_commit(struct intel_atomic_state *state,
return NULL;
}
-void intel_update_plane(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
+void intel_plane_update_noarm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- trace_intel_update_plane(&plane->base, crtc);
+ trace_intel_plane_update_noarm(&plane->base, crtc);
+
+ if (plane->update_noarm)
+ plane->update_noarm(plane, crtc_state, plane_state);
+}
+
+void intel_plane_update_arm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+ trace_intel_plane_update_arm(&plane->base, crtc);
if (crtc_state->uapi.async_flip && plane->async_flip)
plane->async_flip(plane, crtc_state, plane_state, true);
else
- plane->update_plane(plane, crtc_state, plane_state);
+ plane->update_arm(plane, crtc_state, plane_state);
}
-void intel_disable_plane(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state)
+void intel_plane_disable_arm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- trace_intel_disable_plane(&plane->base, crtc);
- plane->disable_plane(plane, crtc_state);
+ trace_intel_plane_disable_arm(&plane->base, crtc);
+ plane->disable_arm(plane, crtc_state);
}
-void skl_update_planes_on_crtc(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+void intel_update_planes_on_crtc(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ u32 update_mask = new_crtc_state->update_planes;
+ struct intel_plane_state *new_plane_state;
+ struct intel_plane *plane;
+ int i;
+
+ if (new_crtc_state->uapi.async_flip)
+ return;
+
+ /*
+ * Since we only write non-arming registers here,
+ * the order does not matter even for skl+.
+ */
+ for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
+ if (crtc->pipe != plane->pipe ||
+ !(update_mask & BIT(plane->id)))
+ continue;
+
+ /* TODO: for mailbox updates this should be skipped */
+ if (new_plane_state->uapi.visible ||
+ new_plane_state->planar_slave)
+ intel_plane_update_noarm(plane, new_crtc_state, new_plane_state);
+ }
+}
+
+void skl_arm_planes_on_crtc(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
@@ -515,17 +556,20 @@ void skl_update_planes_on_crtc(struct intel_atomic_state *state,
struct intel_plane_state *new_plane_state =
intel_atomic_get_new_plane_state(state, plane);
+ /*
+ * TODO: for mailbox updates intel_plane_update_noarm()
+ * would have to be called here as well.
+ */
if (new_plane_state->uapi.visible ||
- new_plane_state->planar_slave) {
- intel_update_plane(plane, new_crtc_state, new_plane_state);
- } else {
- intel_disable_plane(plane, new_crtc_state);
- }
+ new_plane_state->planar_slave)
+ intel_plane_update_arm(plane, new_crtc_state, new_plane_state);
+ else
+ intel_plane_disable_arm(plane, new_crtc_state);
}
}
-void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+void i9xx_arm_planes_on_crtc(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
@@ -539,10 +583,14 @@ void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
!(update_mask & BIT(plane->id)))
continue;
+ /*
+ * TODO: for mailbox updates intel_plane_update_noarm()
+ * would have to be called here as well.
+ */
if (new_plane_state->uapi.visible)
- intel_update_plane(plane, new_crtc_state, new_plane_state);
+ intel_plane_update_arm(plane, new_crtc_state, new_plane_state);
else
- intel_disable_plane(plane, new_crtc_state);
+ intel_plane_disable_arm(plane, new_crtc_state);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index 62e5a2a77fd4..7907f601598e 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -30,20 +30,25 @@ void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
struct intel_crtc *crtc);
void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,
const struct intel_plane_state *from_plane_state);
-void intel_update_plane(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state);
-void intel_disable_plane(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state);
+void intel_plane_update_noarm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state);
+void intel_plane_update_arm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state);
+void intel_plane_disable_arm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state);
struct intel_plane *intel_plane_alloc(void);
void intel_plane_free(struct intel_plane *plane);
struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
void intel_plane_destroy_state(struct drm_plane *plane,
struct drm_plane_state *state);
-void skl_update_planes_on_crtc(struct intel_atomic_state *state,
- struct intel_crtc *crtc);
-void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
- struct intel_crtc *crtc);
+void intel_update_planes_on_crtc(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
+void skl_arm_planes_on_crtc(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
+void i9xx_arm_planes_on_crtc(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
struct intel_crtc_state *crtc_state,
const struct intel_plane_state *old_plane_state,
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index 11842f212613..826337a769b5 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -253,9 +253,10 @@ static int i845_check_cursor(struct intel_crtc_state *crtc_state,
return 0;
}
-static void i845_update_cursor(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
+/* TODO: split into noarm+arm pair */
+static void i845_cursor_update_arm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
u32 cntl = 0, base = 0, pos = 0, size = 0;
@@ -298,10 +299,10 @@ static void i845_update_cursor(struct intel_plane *plane,
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
-static void i845_disable_cursor(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state)
+static void i845_cursor_disable_arm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state)
{
- i845_update_cursor(plane, crtc_state, NULL);
+ i845_cursor_update_arm(plane, crtc_state, NULL);
}
static bool i845_cursor_get_hw_state(struct intel_plane *plane,
@@ -488,9 +489,10 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
return 0;
}
-static void i9xx_update_cursor(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
+/* TODO: split into noarm+arm pair */
+static void i9xx_cursor_update_arm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
@@ -562,10 +564,10 @@ static void i9xx_update_cursor(struct intel_plane *plane,
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
-static void i9xx_disable_cursor(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state)
+static void i9xx_cursor_disable_arm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state)
{
- i9xx_update_cursor(plane, crtc_state, NULL);
+ i9xx_cursor_update_arm(plane, crtc_state, NULL);
}
static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
@@ -717,10 +719,12 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
*/
crtc_state->active_planes = new_crtc_state->active_planes;
- if (new_plane_state->uapi.visible)
- intel_update_plane(plane, crtc_state, new_plane_state);
- else
- intel_disable_plane(plane, crtc_state);
+ if (new_plane_state->uapi.visible) {
+ intel_plane_update_noarm(plane, crtc_state, new_plane_state);
+ intel_plane_update_arm(plane, crtc_state, new_plane_state);
+ } else {
+ intel_plane_disable_arm(plane, crtc_state);
+ }
intel_plane_unpin_fb(old_plane_state);
@@ -766,14 +770,14 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
cursor->max_stride = i845_cursor_max_stride;
- cursor->update_plane = i845_update_cursor;
- cursor->disable_plane = i845_disable_cursor;
+ cursor->update_arm = i845_cursor_update_arm;
+ cursor->disable_arm = i845_cursor_disable_arm;
cursor->get_hw_state = i845_cursor_get_hw_state;
cursor->check_plane = i845_check_cursor;
} else {
cursor->max_stride = i9xx_cursor_max_stride;
- cursor->update_plane = i9xx_update_cursor;
- cursor->disable_plane = i9xx_disable_cursor;
+ cursor->update_arm = i9xx_cursor_update_arm;
+ cursor->disable_arm = i9xx_cursor_disable_arm;
cursor->get_hw_state = i9xx_cursor_get_hw_state;
cursor->check_plane = i9xx_check_cursor;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8bb87e839f4a..a685aad738f3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1126,7 +1126,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
- intel_disable_plane(plane, crtc_state);
+ intel_plane_disable_arm(plane, crtc_state);
intel_wait_for_vblank(dev_priv, crtc->pipe);
}
@@ -2156,7 +2156,7 @@ static void intel_crtc_disable_planes(struct intel_atomic_state *state,
!(update_mask & BIT(plane->id)))
continue;
- intel_disable_plane(plane, new_crtc_state);
+ intel_plane_disable_arm(plane, new_crtc_state);
if (old_plane_state->uapi.visible)
fb_bits |= plane->frontbuffer_bit;
@@ -2423,7 +2423,7 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_plane *plane = to_intel_plane(crtc->base.primary);
- plane->disable_plane(plane, crtc_state);
+ plane->disable_arm(plane, crtc_state);
}
static void ilk_crtc_enable(struct intel_atomic_state *state,
@@ -9387,15 +9387,17 @@ static void intel_update_crtc(struct intel_atomic_state *state,
intel_fbc_update(state, crtc);
+ intel_update_planes_on_crtc(state, crtc);
+
/* Perform vblank evasion around commit operation */
intel_pipe_update_start(new_crtc_state);
commit_pipe_pre_planes(state, crtc);
if (DISPLAY_VER(dev_priv) >= 9)
- skl_update_planes_on_crtc(state, crtc);
+ skl_arm_planes_on_crtc(state, crtc);
else
- i9xx_update_planes_on_crtc(state, crtc);
+ i9xx_arm_planes_on_crtc(state, crtc);
commit_pipe_post_planes(state, crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 39e11eaec1a3..907389fd6f85 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1362,11 +1362,17 @@ struct intel_plane {
unsigned int (*max_stride)(struct intel_plane *plane,
u32 pixel_format, u64 modifier,
unsigned int rotation);
- void (*update_plane)(struct intel_plane *plane,
+ /* Write all non-self arming plane registers */
+ void (*update_noarm)(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
- void (*disable_plane)(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state);
+ /* Write all self-arming plane registers */
+ void (*update_arm)(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state);
+ /* Disable the plane, must arm */
+ void (*disable_arm)(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state);
bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
int (*check_plane)(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state);
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 1daa3360cf02..9c36c1492b33 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -416,10 +416,11 @@ static void vlv_sprite_update_gamma(const struct intel_plane_state *plane_state)
gamma[i] << 16 | gamma[i] << 8 | gamma[i]);
}
+/* TODO: split into noarm+arm pair */
static void
-vlv_sprite_update(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
+vlv_sprite_update_arm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
@@ -485,8 +486,8 @@ vlv_sprite_update(struct intel_plane *plane,
}
static void
-vlv_sprite_disable(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state)
+vlv_sprite_disable_arm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
@@ -834,10 +835,11 @@ static void ivb_sprite_update_gamma(const struct intel_plane_state *plane_state)
i++;
}
+/* TODO: split into noarm+arm pair */
static void
-ivb_sprite_update(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
+ivb_sprite_update_arm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
@@ -908,8 +910,8 @@ ivb_sprite_update(struct intel_plane *plane,
}
static void
-ivb_sprite_disable(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state)
+ivb_sprite_disable_arm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
@@ -1163,9 +1165,9 @@ static void ilk_sprite_update_gamma(const struct intel_plane_state *plane_state)
}
static void
-g4x_sprite_update(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
+g4x_sprite_update_arm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
@@ -1232,8 +1234,8 @@ g4x_sprite_update(struct intel_plane *plane,
}
static void
-g4x_sprite_disable(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state)
+g4x_sprite_disable_arm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
@@ -1762,8 +1764,8 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
return plane;
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- plane->update_plane = vlv_sprite_update;
- plane->disable_plane = vlv_sprite_disable;
+ plane->update_arm = vlv_sprite_update_arm;
+ plane->disable_arm = vlv_sprite_disable_arm;
plane->get_hw_state = vlv_sprite_get_hw_state;
plane->check_plane = vlv_sprite_check;
plane->max_stride = i965_plane_max_stride;
@@ -1780,8 +1782,8 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
plane_funcs = &vlv_sprite_funcs;
} else if (DISPLAY_VER(dev_priv) >= 7) {
- plane->update_plane = ivb_sprite_update;
- plane->disable_plane = ivb_sprite_disable;
+ plane->update_arm = ivb_sprite_update_arm;
+ plane->disable_arm = ivb_sprite_disable_arm;
plane->get_hw_state = ivb_sprite_get_hw_state;
plane->check_plane = g4x_sprite_check;
@@ -1799,8 +1801,8 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
plane_funcs = &snb_sprite_funcs;
} else {
- plane->update_plane = g4x_sprite_update;
- plane->disable_plane = g4x_sprite_disable;
+ plane->update_arm = g4x_sprite_update_arm;
+ plane->disable_arm = g4x_sprite_disable_arm;
plane->get_hw_state = g4x_sprite_get_hw_state;
plane->check_plane = g4x_sprite_check;
plane->max_stride = g4x_sprite_max_stride;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index e2f024449149..74f3870d39b1 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -642,8 +642,8 @@ static u32 skl_plane_stride(const struct intel_plane_state *plane_state,
}
static void
-skl_disable_plane(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state)
+skl_plane_disable_arm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum plane_id plane_id = plane->id;
@@ -1199,10 +1199,11 @@ skl_plane_async_flip(struct intel_plane *plane,
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
+/* TODO: split into noarm+arm pair */
static void
-skl_update_plane(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
+skl_plane_update_arm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
{
int color_plane = 0;
@@ -2158,8 +2159,8 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
}
plane->max_stride = skl_plane_max_stride;
- plane->update_plane = skl_update_plane;
- plane->disable_plane = skl_disable_plane;
+ plane->update_arm = skl_plane_update_arm;
+ plane->disable_arm = skl_plane_disable_arm;
plane->get_hw_state = skl_plane_get_hw_state;
plane->check_plane = skl_plane_check;
diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
index 9795f456cccf..214696d6b270 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -288,7 +288,7 @@ TRACE_EVENT(vlv_fifo_size,
/* plane updates */
-TRACE_EVENT(intel_update_plane,
+TRACE_EVENT(intel_plane_update_noarm,
TP_PROTO(struct drm_plane *plane, struct intel_crtc *crtc),
TP_ARGS(plane, crtc),
@@ -317,7 +317,36 @@ TRACE_EVENT(intel_update_plane,
DRM_RECT_ARG((const struct drm_rect *)__entry->dst))
);
-TRACE_EVENT(intel_disable_plane,
+TRACE_EVENT(intel_plane_update_arm,
+ TP_PROTO(struct drm_plane *plane, struct intel_crtc *crtc),
+ TP_ARGS(plane, crtc),
+
+ TP_STRUCT__entry(
+ __field(enum pipe, pipe)
+ __field(u32, frame)
+ __field(u32, scanline)
+ __array(int, src, 4)
+ __array(int, dst, 4)
+ __string(name, plane->name)
+ ),
+
+ TP_fast_assign(
+ __assign_str(name, plane->name);
+ __entry->pipe = crtc->pipe;
+ __entry->frame = intel_crtc_get_vblank_counter(crtc);
+ __entry->scanline = intel_get_crtc_scanline(crtc);
+ memcpy(__entry->src, &plane->state->src, sizeof(__entry->src));
+ memcpy(__entry->dst, &plane->state->dst, sizeof(__entry->dst));
+ ),
+
+ TP_printk("pipe %c, plane %s, frame=%u, scanline=%u, " DRM_RECT_FP_FMT " -> " DRM_RECT_FMT,
+ pipe_name(__entry->pipe), __get_str(name),
+ __entry->frame, __entry->scanline,
+ DRM_RECT_FP_ARG((const struct drm_rect *)__entry->src),
+ DRM_RECT_ARG((const struct drm_rect *)__entry->dst))
+);
+
+TRACE_EVENT(intel_plane_disable_arm,
TP_PROTO(struct drm_plane *plane, struct intel_crtc *crtc),
TP_ARGS(plane, crtc),
--
2.32.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Intel-gfx] [PATCH 5/9] drm/i915: Split skl+ plane update into noarm+arm pair
2021-10-18 11:50 [Intel-gfx] [PATCH 0/9] drm/i915: Split plane updates to noarm+arm phases Ville Syrjala
` (3 preceding siblings ...)
2021-10-18 11:50 ` [Intel-gfx] [PATCH 4/9] drm/i915: Split update_plane() into update_noarm() + update_arm() Ville Syrjala
@ 2021-10-18 11:50 ` Ville Syrjala
2021-10-18 12:06 ` Lisovskiy, Stanislav
` (2 more replies)
2021-10-18 11:50 ` [Intel-gfx] [PATCH 6/9] drm/i915: Split pre-skl primary " Ville Syrjala
` (11 subsequent siblings)
16 siblings, 3 replies; 38+ messages in thread
From: Ville Syrjala @ 2021-10-18 11:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Stanislav Lisovskiy
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Chop skl_program_plane() into two halves. Fist half becomes
the _noarm() variant, second part the _arm() variant.
Fortunately I have already previously grouped the register
writes into roughtly the correct order, so the split looks
surprisingly clean.
A few notable oddities I did not realize were self arming
are AUX_DIST and COLOR_CTL.
i915_update_info doesn't look too terrible on my cfl running
kms_atomic_transition --r plane-all-transition --extended:
w/o patch w/ patch
Updates: 2178 Updates: 2018
| |
1us | 1us |
| |
4us | 4us |*****
|********* |**********
16us |********** 16us |*******
|*** |
66us | 66us |
| |
262us | 262us |
| |
1ms | 1ms |
| |
4ms | 4ms |
| |
17ms | 17ms |
| |
Min update: 8332ns Min update: 6164ns
Max update: 48758ns Max update: 31808ns
Average update: 19959ns Average update: 13159ns
Overruns > 100us: 0 Overruns > 100us: 0
And with lockdep enabled:
w/o patch w/ patch
Updates: 2177 Updates: 2172
| |
1us | 1us |
| |
4us | 4us |
|******* |*********
16us |********** 16us |**********
|******* |*
66us | 66us |
| |
262us | 262us |
| |
1ms | 1ms |
| |
4ms | 4ms |
| |
17ms | 17ms |
| |
Min update: 12645ns Min update: 9980ns
Max update: 50153ns Max update: 33533ns
Average update: 25337ns Average update: 18245ns
Overruns > 250us: 0 Overruns > 250us: 0
TODO: On icl+ everything seems to be armed by PLANE_SURF, so we
can optimize this even further on modern platforms. But I
think there's a bit of refactoring to be done first to
figure out the best way to go about it (eg. just reusing
the current skl+ functions, or doing a lower level split).
TODO: Split scaler programming as well, but IIRC the scaler
has some oddball double buffering behaviour on some
platforms, so needs proper reverse engineering
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/skl_universal_plane.c | 113 +++++++++++-------
1 file changed, 72 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 74f3870d39b1..2a822e1e465e 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1050,60 +1050,32 @@ static void icl_plane_csc_load_black(struct intel_plane *plane)
}
static void
-skl_program_plane(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state,
- int color_plane)
+skl_program_plane_noarm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state,
+ int color_plane)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum plane_id plane_id = plane->id;
enum pipe pipe = plane->pipe;
- const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
u32 stride = skl_plane_stride(plane_state, color_plane);
const struct drm_framebuffer *fb = plane_state->hw.fb;
- int aux_plane = skl_main_to_aux_plane(fb, color_plane);
int crtc_x = plane_state->uapi.dst.x1;
int crtc_y = plane_state->uapi.dst.y1;
- u32 x = plane_state->view.color_plane[color_plane].x;
- u32 y = plane_state->view.color_plane[color_plane].y;
u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
- u8 alpha = plane_state->hw.alpha >> 8;
- u32 plane_color_ctl = 0, aux_dist = 0;
unsigned long irqflags;
- u32 keymsk, keymax;
- u32 plane_ctl = plane_state->ctl;
-
- plane_ctl |= skl_plane_ctl_crtc(crtc_state);
-
- if (DISPLAY_VER(dev_priv) >= 10)
- plane_color_ctl = plane_state->color_ctl |
- glk_plane_color_ctl_crtc(crtc_state);
/* Sizes are 0 based */
src_w--;
src_h--;
- keymax = (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
-
- keymsk = key->channel_mask & 0x7ffffff;
- if (alpha < 0xff)
- keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
-
/* The scaler will handle the output position */
if (plane_state->scaler_id >= 0) {
crtc_x = 0;
crtc_y = 0;
}
- if (aux_plane) {
- aux_dist = skl_surf_address(plane_state, aux_plane) -
- skl_surf_address(plane_state, color_plane);
-
- if (DISPLAY_VER(dev_priv) < 12)
- aux_dist |= skl_plane_stride(plane_state, aux_plane);
- }
-
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
/*
@@ -1119,16 +1091,10 @@ skl_program_plane(struct intel_plane *plane,
intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
(src_h << 16) | src_w);
- intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);
-
if (icl_is_hdr_plane(dev_priv, plane_id))
intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id),
plane_state->cus_ctl);
- if (DISPLAY_VER(dev_priv) >= 10)
- intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id),
- plane_color_ctl);
-
if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
icl_program_input_csc(plane, crtc_state, plane_state);
@@ -1138,6 +1104,52 @@ skl_program_plane(struct intel_plane *plane,
skl_write_plane_wm(plane, crtc_state);
+ intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane);
+
+ spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+}
+
+static void
+skl_program_plane_arm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state,
+ int color_plane)
+{
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ enum plane_id plane_id = plane->id;
+ enum pipe pipe = plane->pipe;
+ const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ int aux_plane = skl_main_to_aux_plane(fb, color_plane);
+ u32 x = plane_state->view.color_plane[color_plane].x;
+ u32 y = plane_state->view.color_plane[color_plane].y;
+ u32 keymsk, keymax, aux_dist = 0, plane_color_ctl = 0;
+ u8 alpha = plane_state->hw.alpha >> 8;
+ u32 plane_ctl = plane_state->ctl;
+ unsigned long irqflags;
+
+ plane_ctl |= skl_plane_ctl_crtc(crtc_state);
+
+ if (DISPLAY_VER(dev_priv) >= 10)
+ plane_color_ctl = plane_state->color_ctl |
+ glk_plane_color_ctl_crtc(crtc_state);
+
+ keymax = (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
+
+ keymsk = key->channel_mask & 0x7ffffff;
+ if (alpha < 0xff)
+ keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
+
+ if (aux_plane) {
+ aux_dist = skl_surf_address(plane_state, aux_plane) -
+ skl_surf_address(plane_state, color_plane);
+
+ if (DISPLAY_VER(dev_priv) < 12)
+ aux_dist |= skl_plane_stride(plane_state, aux_plane);
+ }
+
+ spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+
intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id),
key->min_value);
intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), keymsk);
@@ -1146,17 +1158,22 @@ skl_program_plane(struct intel_plane *plane,
intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
(y << 16) | x);
+ intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);
+
if (DISPLAY_VER(dev_priv) < 11)
intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
(plane_state->view.color_plane[1].y << 16) |
plane_state->view.color_plane[1].x);
- intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane);
+ if (DISPLAY_VER(dev_priv) >= 10)
+ intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
/*
* Enable the scaler before the plane so that we don't
* get a catastrophic underrun even if the two operations
* end up happening in two different frames.
+ *
+ * TODO: split into noarm+arm pair
*/
if (plane_state->scaler_id >= 0)
skl_program_plane_scaler(plane, crtc_state, plane_state);
@@ -1199,7 +1216,20 @@ skl_plane_async_flip(struct intel_plane *plane,
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
-/* TODO: split into noarm+arm pair */
+static void
+skl_plane_update_noarm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
+{
+ int color_plane = 0;
+
+ if (plane_state->planar_linked_plane && !plane_state->planar_slave)
+ /* Program the UV plane on planar master */
+ color_plane = 1;
+
+ skl_program_plane_noarm(plane, crtc_state, plane_state, color_plane);
+}
+
static void
skl_plane_update_arm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
@@ -1211,7 +1241,7 @@ skl_plane_update_arm(struct intel_plane *plane,
/* Program the UV plane on planar master */
color_plane = 1;
- skl_program_plane(plane, crtc_state, plane_state, color_plane);
+ skl_program_plane_arm(plane, crtc_state, plane_state, color_plane);
}
static bool intel_format_is_p01x(u32 format)
@@ -2159,6 +2189,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
}
plane->max_stride = skl_plane_max_stride;
+ plane->update_noarm = skl_plane_update_noarm;
plane->update_arm = skl_plane_update_arm;
plane->disable_arm = skl_plane_disable_arm;
plane->get_hw_state = skl_plane_get_hw_state;
--
2.32.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Intel-gfx] [PATCH 6/9] drm/i915: Split pre-skl primary plane update into noarm+arm pair
2021-10-18 11:50 [Intel-gfx] [PATCH 0/9] drm/i915: Split plane updates to noarm+arm phases Ville Syrjala
` (4 preceding siblings ...)
2021-10-18 11:50 ` [Intel-gfx] [PATCH 5/9] drm/i915: Split skl+ plane update into noarm+arm pair Ville Syrjala
@ 2021-10-18 11:50 ` Ville Syrjala
2021-10-20 21:27 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2021-11-03 18:47 ` [Intel-gfx] [PATCH " Lisovskiy, Stanislav
2021-10-18 11:50 ` [Intel-gfx] [PATCH 7/9] drm/i915: Split g4x+ sprite " Ville Syrjala
` (10 subsequent siblings)
16 siblings, 2 replies; 38+ messages in thread
From: Ville Syrjala @ 2021-10-18 11:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Stanislav Lisovskiy
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Chop i9xx_plane_update() into two halves. Fist half becomes
the _noarm() variant, second part the _arm() variant.
Fortunately I have already previously grouped the register
writes into roughtly the correct order, so the split looks
surprisingly clean.
One slightly surprising fact was that the CHV pipe B PRIMPOS/SIZE
registers are self arming unlike their pre-ctg DSPPOS/SIZE
counterparts. In fact all the new CHV pipe B registers are
self arming.
I didn't do any i915_update_info measurements for this one
alone. I'll get total numbers with the corrsponding sprite
plane changes.
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 61 +++++++++++++++--------
1 file changed, 40 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 93163f9100a8..9dfd0a53e0ee 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -418,23 +418,49 @@ static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
return DIV_ROUND_UP(pixel_rate * num, den);
}
-/* TODO: split into noarm+arm pair */
+static void i9xx_plane_update_noarm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+
+ intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),
+ plane_state->view.color_plane[0].stride);
+
+ if (DISPLAY_VER(dev_priv) < 4) {
+ int crtc_x = plane_state->uapi.dst.x1;
+ int crtc_y = plane_state->uapi.dst.y1;
+ int crtc_w = drm_rect_width(&plane_state->uapi.dst);
+ int crtc_h = drm_rect_height(&plane_state->uapi.dst);
+
+ /*
+ * PLANE_A doesn't actually have a full window
+ * generator but let's assume we still need to
+ * program whatever is there.
+ */
+ intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
+ (crtc_y << 16) | crtc_x);
+ intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
+ ((crtc_h - 1) << 16) | (crtc_w - 1));
+ }
+
+ spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+}
+
static void i9xx_plane_update_arm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
- u32 linear_offset;
int x = plane_state->view.color_plane[0].x;
int y = plane_state->view.color_plane[0].y;
- int crtc_x = plane_state->uapi.dst.x1;
- int crtc_y = plane_state->uapi.dst.y1;
- int crtc_w = drm_rect_width(&plane_state->uapi.dst);
- int crtc_h = drm_rect_height(&plane_state->uapi.dst);
+ u32 dspcntr, dspaddr_offset, linear_offset;
unsigned long irqflags;
- u32 dspaddr_offset;
- u32 dspcntr;
dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
@@ -447,20 +473,12 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
- intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),
- plane_state->view.color_plane[0].stride);
+ if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
+ int crtc_x = plane_state->uapi.dst.x1;
+ int crtc_y = plane_state->uapi.dst.y1;
+ int crtc_w = drm_rect_width(&plane_state->uapi.dst);
+ int crtc_h = drm_rect_height(&plane_state->uapi.dst);
- if (DISPLAY_VER(dev_priv) < 4) {
- /*
- * PLANE_A doesn't actually have a full window
- * generator but let's assume we still need to
- * program whatever is there.
- */
- intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
- (crtc_y << 16) | crtc_x);
- intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
- ((crtc_h - 1) << 16) | (crtc_w - 1));
- } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane),
(crtc_y << 16) | crtc_x);
intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane),
@@ -852,6 +870,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
plane->max_stride = ilk_primary_max_stride;
}
+ plane->update_noarm = i9xx_plane_update_noarm;
plane->update_arm = i9xx_plane_update_arm;
plane->disable_arm = i9xx_plane_disable_arm;
plane->get_hw_state = i9xx_plane_get_hw_state;
--
2.32.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Intel-gfx] [PATCH 7/9] drm/i915: Split g4x+ sprite plane update into noarm+arm pair
2021-10-18 11:50 [Intel-gfx] [PATCH 0/9] drm/i915: Split plane updates to noarm+arm phases Ville Syrjala
` (5 preceding siblings ...)
2021-10-18 11:50 ` [Intel-gfx] [PATCH 6/9] drm/i915: Split pre-skl primary " Ville Syrjala
@ 2021-10-18 11:50 ` Ville Syrjala
2021-11-03 18:46 ` Lisovskiy, Stanislav
2021-10-18 11:50 ` [Intel-gfx] [PATCH 8/9] drm/i915: Split ivb+ " Ville Syrjala
` (9 subsequent siblings)
16 siblings, 1 reply; 38+ messages in thread
From: Ville Syrjala @ 2021-10-18 11:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Stanislav Lisovskiy
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Chop g4x_sprite_update() into two halves. Fist half becomes
the _noarm() variant, second part the _arm() variant.
Fortunately I have already previously grouped the register
writes into roughtly the correct order, so the split looks
surprisingly clean.
Not much of a change in i915_update_info on these older
platforms that don't have so many planes or registers to
begin with. Here are the numbers from snb (totally unpatched
vs. both primary plane and sprite patched applied) running
kms_atomic_transition --r plane-all-transition --extended:
w/o patch w/ patch
Updates: 5404 Updates: 5405
| |
1us |****** 1us |******
|********* |*********
4us |*********** 4us |***********
|********** |**********
16us |** 16us |**
| |
66us | 66us |
| |
262us | 262us |
| |
1ms | 1ms |
| |
4ms | 4ms |
| |
17ms | 17ms |
| |
Min update: 1400ns Min update: 1307ns
Max update: 19809ns Max update: 20194ns
Average update: 6957ns Average update: 6432ns
Overruns > 100us: 0 Overruns > 100us: 0
But there seems to be a slight improvement with
lockdep enabled:
w/o patch w/ patch
Updates: 17612 Updates: 16364
| |
1us | 1us |
|****** |******
4us |********** 4us |**********
|************ |*************
16us |************* 16us |************
|*** |*
66us | 66us |
| |
262us | 262us |
| |
1ms | 1ms |
| |
4ms | 4ms |
| |
17ms | 17ms |
| |
Min update: 3141ns Min update: 3562ns
Max update: 126450ns Max update: 73354ns
Average update: 16373ns Average update: 15153ns
Overruns > 250us: 0 Overruns > 250us: 0
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 41 ++++++++++++++-------
1 file changed, 28 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 9c36c1492b33..03e3bf890ce9 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -1165,28 +1165,21 @@ static void ilk_sprite_update_gamma(const struct intel_plane_state *plane_state)
}
static void
-g4x_sprite_update_arm(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
+g4x_sprite_update_noarm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
- u32 dvssurf_offset = plane_state->view.color_plane[0].offset;
- u32 linear_offset;
- const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
int crtc_x = plane_state->uapi.dst.x1;
int crtc_y = plane_state->uapi.dst.y1;
u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
- u32 x = plane_state->view.color_plane[0].x;
- u32 y = plane_state->view.color_plane[0].y;
u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
- u32 dvscntr, dvsscale = 0;
+ u32 dvsscale = 0;
unsigned long irqflags;
- dvscntr = plane_state->ctl | g4x_sprite_ctl_crtc(crtc_state);
-
/* Sizes are 0 based */
src_w--;
src_h--;
@@ -1196,8 +1189,6 @@ g4x_sprite_update_arm(struct intel_plane *plane,
if (crtc_w != src_w || crtc_h != src_h)
dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
- linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
-
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, DVSSTRIDE(pipe),
@@ -1206,6 +1197,29 @@ g4x_sprite_update_arm(struct intel_plane *plane,
intel_de_write_fw(dev_priv, DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale);
+ spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+}
+
+static void
+g4x_sprite_update_arm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ enum pipe pipe = plane->pipe;
+ const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
+ u32 dvssurf_offset = plane_state->view.color_plane[0].offset;
+ u32 x = plane_state->view.color_plane[0].x;
+ u32 y = plane_state->view.color_plane[0].y;
+ u32 dvscntr, linear_offset;
+ unsigned long irqflags;
+
+ dvscntr = plane_state->ctl | g4x_sprite_ctl_crtc(crtc_state);
+
+ linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
+
+ spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+
if (key->flags) {
intel_de_write_fw(dev_priv, DVSKEYVAL(pipe), key->min_value);
intel_de_write_fw(dev_priv, DVSKEYMSK(pipe),
@@ -1801,6 +1815,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
plane_funcs = &snb_sprite_funcs;
} else {
+ plane->update_noarm = g4x_sprite_update_noarm;
plane->update_arm = g4x_sprite_update_arm;
plane->disable_arm = g4x_sprite_disable_arm;
plane->get_hw_state = g4x_sprite_get_hw_state;
--
2.32.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Intel-gfx] [PATCH 8/9] drm/i915: Split ivb+ sprite plane update into noarm+arm pair
2021-10-18 11:50 [Intel-gfx] [PATCH 0/9] drm/i915: Split plane updates to noarm+arm phases Ville Syrjala
` (6 preceding siblings ...)
2021-10-18 11:50 ` [Intel-gfx] [PATCH 7/9] drm/i915: Split g4x+ sprite " Ville Syrjala
@ 2021-10-18 11:50 ` Ville Syrjala
2021-11-03 18:45 ` Lisovskiy, Stanislav
2021-10-18 11:50 ` [Intel-gfx] [PATCH 9/9] drm/i915: Split vlv/chv " Ville Syrjala
` (8 subsequent siblings)
16 siblings, 1 reply; 38+ messages in thread
From: Ville Syrjala @ 2021-10-18 11:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Stanislav Lisovskiy
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Chop ivb_sprite_update() into two halves. Fist half becomes
the _noarm() variant, second part the _arm() variant.
Fortunately I have already previously grouped the register
writes into roughtly the correct order, so the split looks
surprisingly clean.
Didn't bother with i915_update_info numbers for this one.
I expect the results to be pretty much identical to the snb
numbers from the corresponding g4x+ sprite modification.
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 42 ++++++++++++++-------
1 file changed, 28 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 03e3bf890ce9..4e5f95aebeca 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -835,30 +835,22 @@ static void ivb_sprite_update_gamma(const struct intel_plane_state *plane_state)
i++;
}
-/* TODO: split into noarm+arm pair */
static void
-ivb_sprite_update_arm(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
+ivb_sprite_update_noarm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
- u32 sprsurf_offset = plane_state->view.color_plane[0].offset;
- u32 linear_offset;
- const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
int crtc_x = plane_state->uapi.dst.x1;
int crtc_y = plane_state->uapi.dst.y1;
u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
- u32 x = plane_state->view.color_plane[0].x;
- u32 y = plane_state->view.color_plane[0].y;
u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
- u32 sprctl, sprscale = 0;
+ u32 sprscale = 0;
unsigned long irqflags;
- sprctl = plane_state->ctl | ivb_sprite_ctl_crtc(crtc_state);
-
/* Sizes are 0 based */
src_w--;
src_h--;
@@ -868,8 +860,6 @@ ivb_sprite_update_arm(struct intel_plane *plane,
if (crtc_w != src_w || crtc_h != src_h)
sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
- linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
-
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, SPRSTRIDE(pipe),
@@ -879,6 +869,29 @@ ivb_sprite_update_arm(struct intel_plane *plane,
if (IS_IVYBRIDGE(dev_priv))
intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale);
+ spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+}
+
+static void
+ivb_sprite_update_arm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ enum pipe pipe = plane->pipe;
+ const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
+ u32 sprsurf_offset = plane_state->view.color_plane[0].offset;
+ u32 x = plane_state->view.color_plane[0].x;
+ u32 y = plane_state->view.color_plane[0].y;
+ u32 sprctl, linear_offset;
+ unsigned long irqflags;
+
+ sprctl = plane_state->ctl | ivb_sprite_ctl_crtc(crtc_state);
+
+ linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
+
+ spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+
if (key->flags) {
intel_de_write_fw(dev_priv, SPRKEYVAL(pipe), key->min_value);
intel_de_write_fw(dev_priv, SPRKEYMSK(pipe),
@@ -1796,6 +1809,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
plane_funcs = &vlv_sprite_funcs;
} else if (DISPLAY_VER(dev_priv) >= 7) {
+ plane->update_noarm = ivb_sprite_update_noarm;
plane->update_arm = ivb_sprite_update_arm;
plane->disable_arm = ivb_sprite_disable_arm;
plane->get_hw_state = ivb_sprite_get_hw_state;
--
2.32.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Intel-gfx] [PATCH 9/9] drm/i915: Split vlv/chv sprite plane update into noarm+arm pair
2021-10-18 11:50 [Intel-gfx] [PATCH 0/9] drm/i915: Split plane updates to noarm+arm phases Ville Syrjala
` (7 preceding siblings ...)
2021-10-18 11:50 ` [Intel-gfx] [PATCH 8/9] drm/i915: Split ivb+ " Ville Syrjala
@ 2021-10-18 11:50 ` Ville Syrjala
2021-11-03 18:44 ` Lisovskiy, Stanislav
2021-10-18 13:06 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Split plane updates to noarm+arm phases Patchwork
` (7 subsequent siblings)
16 siblings, 1 reply; 38+ messages in thread
From: Ville Syrjala @ 2021-10-18 11:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Stanislav Lisovskiy
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Chop vlv_sprite_update() into two halves. Fist half becomes
the _noarm() variant, second part the _arm() variant.
Fortunately I have already previously grouped the register
writes into roughtly the correct order, so the split looks
surprisingly clean.
Looks like most of the hardware logic wa scopied from the
pre-ctg sprite C, so SPSTRIDE/POS/SIZE are armed by SPSURF,
while the rest are self arming. SPCONSTALPHA is the one
entirely new register that didn't exist in the old sprite C,
and looks like that one is self arming. The CHV pipe B CSC
is also self arming, like the rest of the CHV pipe B
additions.
I didn't have time to capture i915_update_info numbers for
these, but since all the other platforms generally showed
improvements, and crucially no regression, I am fairly
confident this should behave similarly.
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 45 ++++++++++++++-------
1 file changed, 30 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 4e5f95aebeca..fc6ecb41a40e 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -416,35 +416,24 @@ static void vlv_sprite_update_gamma(const struct intel_plane_state *plane_state)
gamma[i] << 16 | gamma[i] << 8 | gamma[i]);
}
-/* TODO: split into noarm+arm pair */
static void
-vlv_sprite_update_arm(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
+vlv_sprite_update_noarm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
enum plane_id plane_id = plane->id;
- u32 sprsurf_offset = plane_state->view.color_plane[0].offset;
- u32 linear_offset;
- const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
int crtc_x = plane_state->uapi.dst.x1;
int crtc_y = plane_state->uapi.dst.y1;
u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
- u32 x = plane_state->view.color_plane[0].x;
- u32 y = plane_state->view.color_plane[0].y;
unsigned long irqflags;
- u32 sprctl;
-
- sprctl = plane_state->ctl | vlv_sprite_ctl_crtc(crtc_state);
/* Sizes are 0 based */
crtc_w--;
crtc_h--;
- linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
-
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id),
@@ -453,7 +442,30 @@ vlv_sprite_update_arm(struct intel_plane *plane,
(crtc_y << 16) | crtc_x);
intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id),
(crtc_h << 16) | crtc_w);
- intel_de_write_fw(dev_priv, SPCONSTALPHA(pipe, plane_id), 0);
+
+ spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+}
+
+static void
+vlv_sprite_update_arm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ enum pipe pipe = plane->pipe;
+ enum plane_id plane_id = plane->id;
+ const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
+ u32 sprsurf_offset = plane_state->view.color_plane[0].offset;
+ u32 x = plane_state->view.color_plane[0].x;
+ u32 y = plane_state->view.color_plane[0].y;
+ u32 sprctl, linear_offset;
+ unsigned long irqflags;
+
+ sprctl = plane_state->ctl | vlv_sprite_ctl_crtc(crtc_state);
+
+ linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
+
+ spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
chv_sprite_update_csc(plane_state);
@@ -467,6 +479,8 @@ vlv_sprite_update_arm(struct intel_plane *plane,
key->max_value);
}
+ intel_de_write_fw(dev_priv, SPCONSTALPHA(pipe, plane_id), 0);
+
intel_de_write_fw(dev_priv, SPLINOFF(pipe, plane_id), linear_offset);
intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id), (y << 16) | x);
@@ -1791,6 +1805,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
return plane;
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+ plane->update_noarm = vlv_sprite_update_noarm;
plane->update_arm = vlv_sprite_update_arm;
plane->disable_arm = vlv_sprite_disable_arm;
plane->get_hw_state = vlv_sprite_get_hw_state;
--
2.32.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [Intel-gfx] [PATCH 5/9] drm/i915: Split skl+ plane update into noarm+arm pair
2021-10-18 11:50 ` [Intel-gfx] [PATCH 5/9] drm/i915: Split skl+ plane update into noarm+arm pair Ville Syrjala
@ 2021-10-18 12:06 ` Lisovskiy, Stanislav
2021-10-18 17:14 ` Ville Syrjälä
2021-10-27 17:11 ` Lisovskiy, Stanislav
2021-11-03 18:46 ` Lisovskiy, Stanislav
2 siblings, 1 reply; 38+ messages in thread
From: Lisovskiy, Stanislav @ 2021-10-18 12:06 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Mon, Oct 18, 2021 at 02:50:26PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Chop skl_program_plane() into two halves. Fist half becomes
> the _noarm() variant, second part the _arm() variant.
>
> Fortunately I have already previously grouped the register
> writes into roughtly the correct order, so the split looks
> surprisingly clean.
>
> A few notable oddities I did not realize were self arming
> are AUX_DIST and COLOR_CTL.
>
> i915_update_info doesn't look too terrible on my cfl running
> kms_atomic_transition --r plane-all-transition --extended:
> w/o patch w/ patch
> Updates: 2178 Updates: 2018
> | |
> 1us | 1us |
> | |
> 4us | 4us |*****
> |********* |**********
> 16us |********** 16us |*******
> |*** |
> 66us | 66us |
> | |
> 262us | 262us |
> | |
> 1ms | 1ms |
> | |
> 4ms | 4ms |
> | |
> 17ms | 17ms |
> | |
> Min update: 8332ns Min update: 6164ns
> Max update: 48758ns Max update: 31808ns
> Average update: 19959ns Average update: 13159ns
> Overruns > 100us: 0 Overruns > 100us: 0
>
> And with lockdep enabled:
> w/o patch w/ patch
> Updates: 2177 Updates: 2172
> | |
> 1us | 1us |
> | |
> 4us | 4us |
> |******* |*********
> 16us |********** 16us |**********
> |******* |*
> 66us | 66us |
> | |
> 262us | 262us |
> | |
> 1ms | 1ms |
> | |
> 4ms | 4ms |
> | |
> 17ms | 17ms |
> | |
> Min update: 12645ns Min update: 9980ns
> Max update: 50153ns Max update: 33533ns
> Average update: 25337ns Average update: 18245ns
> Overruns > 250us: 0 Overruns > 250us: 0
>
> TODO: On icl+ everything seems to be armed by PLANE_SURF, so we
> can optimize this even further on modern platforms. But I
> think there's a bit of refactoring to be done first to
> figure out the best way to go about it (eg. just reusing
> the current skl+ functions, or doing a lower level split).
>
> TODO: Split scaler programming as well, but IIRC the scaler
> has some oddball double buffering behaviour on some
> platforms, so needs proper reverse engineering
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Should I use that one as a base for further splitting, i.e for DG2?
Which refactoring has to be done first, as I understand should be
pretty safe to leave only PLANE_SURF update in arm section, and
of course scaler is a different thing.
Stan
> ---
> .../drm/i915/display/skl_universal_plane.c | 113 +++++++++++-------
> 1 file changed, 72 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 74f3870d39b1..2a822e1e465e 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -1050,60 +1050,32 @@ static void icl_plane_csc_load_black(struct intel_plane *plane)
> }
>
> static void
> -skl_program_plane(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state,
> - int color_plane)
> +skl_program_plane_noarm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state,
> + int color_plane)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum plane_id plane_id = plane->id;
> enum pipe pipe = plane->pipe;
> - const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> u32 stride = skl_plane_stride(plane_state, color_plane);
> const struct drm_framebuffer *fb = plane_state->hw.fb;
> - int aux_plane = skl_main_to_aux_plane(fb, color_plane);
> int crtc_x = plane_state->uapi.dst.x1;
> int crtc_y = plane_state->uapi.dst.y1;
> - u32 x = plane_state->view.color_plane[color_plane].x;
> - u32 y = plane_state->view.color_plane[color_plane].y;
> u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
> u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
> - u8 alpha = plane_state->hw.alpha >> 8;
> - u32 plane_color_ctl = 0, aux_dist = 0;
> unsigned long irqflags;
> - u32 keymsk, keymax;
> - u32 plane_ctl = plane_state->ctl;
> -
> - plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> -
> - if (DISPLAY_VER(dev_priv) >= 10)
> - plane_color_ctl = plane_state->color_ctl |
> - glk_plane_color_ctl_crtc(crtc_state);
>
> /* Sizes are 0 based */
> src_w--;
> src_h--;
>
> - keymax = (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
> -
> - keymsk = key->channel_mask & 0x7ffffff;
> - if (alpha < 0xff)
> - keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
> -
> /* The scaler will handle the output position */
> if (plane_state->scaler_id >= 0) {
> crtc_x = 0;
> crtc_y = 0;
> }
>
> - if (aux_plane) {
> - aux_dist = skl_surf_address(plane_state, aux_plane) -
> - skl_surf_address(plane_state, color_plane);
> -
> - if (DISPLAY_VER(dev_priv) < 12)
> - aux_dist |= skl_plane_stride(plane_state, aux_plane);
> - }
> -
> spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>
> /*
> @@ -1119,16 +1091,10 @@ skl_program_plane(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
> (src_h << 16) | src_w);
>
> - intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);
> -
> if (icl_is_hdr_plane(dev_priv, plane_id))
> intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id),
> plane_state->cus_ctl);
>
> - if (DISPLAY_VER(dev_priv) >= 10)
> - intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id),
> - plane_color_ctl);
> -
> if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
> icl_program_input_csc(plane, crtc_state, plane_state);
>
> @@ -1138,6 +1104,52 @@ skl_program_plane(struct intel_plane *plane,
>
> skl_write_plane_wm(plane, crtc_state);
>
> + intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane);
> +
> + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> +}
> +
> +static void
> +skl_program_plane_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state,
> + int color_plane)
> +{
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + enum plane_id plane_id = plane->id;
> + enum pipe pipe = plane->pipe;
> + const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> + const struct drm_framebuffer *fb = plane_state->hw.fb;
> + int aux_plane = skl_main_to_aux_plane(fb, color_plane);
> + u32 x = plane_state->view.color_plane[color_plane].x;
> + u32 y = plane_state->view.color_plane[color_plane].y;
> + u32 keymsk, keymax, aux_dist = 0, plane_color_ctl = 0;
> + u8 alpha = plane_state->hw.alpha >> 8;
> + u32 plane_ctl = plane_state->ctl;
> + unsigned long irqflags;
> +
> + plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> +
> + if (DISPLAY_VER(dev_priv) >= 10)
> + plane_color_ctl = plane_state->color_ctl |
> + glk_plane_color_ctl_crtc(crtc_state);
> +
> + keymax = (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
> +
> + keymsk = key->channel_mask & 0x7ffffff;
> + if (alpha < 0xff)
> + keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
> +
> + if (aux_plane) {
> + aux_dist = skl_surf_address(plane_state, aux_plane) -
> + skl_surf_address(plane_state, color_plane);
> +
> + if (DISPLAY_VER(dev_priv) < 12)
> + aux_dist |= skl_plane_stride(plane_state, aux_plane);
> + }
> +
> + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> +
> intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id),
> key->min_value);
> intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), keymsk);
> @@ -1146,17 +1158,22 @@ skl_program_plane(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
> (y << 16) | x);
>
> + intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);
> +
> if (DISPLAY_VER(dev_priv) < 11)
> intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
> (plane_state->view.color_plane[1].y << 16) |
> plane_state->view.color_plane[1].x);
>
> - intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane);
> + if (DISPLAY_VER(dev_priv) >= 10)
> + intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
>
> /*
> * Enable the scaler before the plane so that we don't
> * get a catastrophic underrun even if the two operations
> * end up happening in two different frames.
> + *
> + * TODO: split into noarm+arm pair
> */
> if (plane_state->scaler_id >= 0)
> skl_program_plane_scaler(plane, crtc_state, plane_state);
> @@ -1199,7 +1216,20 @@ skl_plane_async_flip(struct intel_plane *plane,
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
>
> -/* TODO: split into noarm+arm pair */
> +static void
> +skl_plane_update_noarm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> +{
> + int color_plane = 0;
> +
> + if (plane_state->planar_linked_plane && !plane_state->planar_slave)
> + /* Program the UV plane on planar master */
> + color_plane = 1;
> +
> + skl_program_plane_noarm(plane, crtc_state, plane_state, color_plane);
> +}
> +
> static void
> skl_plane_update_arm(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> @@ -1211,7 +1241,7 @@ skl_plane_update_arm(struct intel_plane *plane,
> /* Program the UV plane on planar master */
> color_plane = 1;
>
> - skl_program_plane(plane, crtc_state, plane_state, color_plane);
> + skl_program_plane_arm(plane, crtc_state, plane_state, color_plane);
> }
>
> static bool intel_format_is_p01x(u32 format)
> @@ -2159,6 +2189,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
> }
>
> plane->max_stride = skl_plane_max_stride;
> + plane->update_noarm = skl_plane_update_noarm;
> plane->update_arm = skl_plane_update_arm;
> plane->disable_arm = skl_plane_disable_arm;
> plane->get_hw_state = skl_plane_get_hw_state;
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Split plane updates to noarm+arm phases
2021-10-18 11:50 [Intel-gfx] [PATCH 0/9] drm/i915: Split plane updates to noarm+arm phases Ville Syrjala
` (8 preceding siblings ...)
2021-10-18 11:50 ` [Intel-gfx] [PATCH 9/9] drm/i915: Split vlv/chv " Ville Syrjala
@ 2021-10-18 13:06 ` Patchwork
2021-10-18 13:08 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (6 subsequent siblings)
16 siblings, 0 replies; 38+ messages in thread
From: Patchwork @ 2021-10-18 13:06 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Split plane updates to noarm+arm phases
URL : https://patchwork.freedesktop.org/series/95962/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4347a5768329 drm/i915: Reject planar formats when doing async flips
9ca3181d87a4 drm/i915: Fix async flip with decryption and/or DPT
35deba336895 drm/i915: Fix up the sprite namespacing
41063002deec drm/i915: Split update_plane() into update_noarm() + update_arm()
-:596: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#596: FILE: drivers/gpu/drm/i915/i915_trace.h:324:
+ TP_STRUCT__entry(
-:605: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#605: FILE: drivers/gpu/drm/i915/i915_trace.h:333:
+ TP_fast_assign(
-:614: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#614: FILE: drivers/gpu/drm/i915/i915_trace.h:342:
+ TP_printk("pipe %c, plane %s, frame=%u, scanline=%u, " DRM_RECT_FP_FMT " -> " DRM_RECT_FMT,
total: 0 errors, 1 warnings, 2 checks, 521 lines checked
e1f91ae7cee9 drm/i915: Split skl+ plane update into noarm+arm pair
901268a16647 drm/i915: Split pre-skl primary plane update into noarm+arm pair
1202bc6cfc3a drm/i915: Split g4x+ sprite plane update into noarm+arm pair
437389a78c69 drm/i915: Split ivb+ sprite plane update into noarm+arm pair
c83a5cef2006 drm/i915: Split vlv/chv sprite plane update into noarm+arm pair
^ permalink raw reply [flat|nested] 38+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Split plane updates to noarm+arm phases
2021-10-18 11:50 [Intel-gfx] [PATCH 0/9] drm/i915: Split plane updates to noarm+arm phases Ville Syrjala
` (9 preceding siblings ...)
2021-10-18 13:06 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Split plane updates to noarm+arm phases Patchwork
@ 2021-10-18 13:08 ` Patchwork
2021-10-18 13:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (5 subsequent siblings)
16 siblings, 0 replies; 38+ messages in thread
From: Patchwork @ 2021-10-18 13:08 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Split plane updates to noarm+arm phases
URL : https://patchwork.freedesktop.org/series/95962/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
^ permalink raw reply [flat|nested] 38+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Split plane updates to noarm+arm phases
2021-10-18 11:50 [Intel-gfx] [PATCH 0/9] drm/i915: Split plane updates to noarm+arm phases Ville Syrjala
` (10 preceding siblings ...)
2021-10-18 13:08 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-10-18 13:38 ` Patchwork
2021-10-18 16:43 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
` (4 subsequent siblings)
16 siblings, 0 replies; 38+ messages in thread
From: Patchwork @ 2021-10-18 13:38 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5712 bytes --]
== Series Details ==
Series: drm/i915: Split plane updates to noarm+arm phases
URL : https://patchwork.freedesktop.org/series/95962/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10752 -> Patchwork_21368
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/index.html
Known issues
------------
Here are the changes found in Patchwork_21368 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/fi-bsw-kefka/igt@amdgpu/amd_basic@query-info.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][2] ([fdo#109315])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/fi-tgl-1115g4/igt@amdgpu/amd_basic@query-info.html
* igt@amdgpu/amd_cs_nop@nop-gfx0:
- fi-tgl-1115g4: NOTRUN -> [SKIP][3] ([fdo#109315] / [i915#2575]) +16 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/fi-tgl-1115g4/igt@amdgpu/amd_cs_nop@nop-gfx0.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-1115g4: NOTRUN -> [SKIP][4] ([i915#2190])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/fi-tgl-1115g4/igt@gem_huc_copy@huc-copy.html
* igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4: NOTRUN -> [SKIP][5] ([i915#1155])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/fi-tgl-1115g4/igt@i915_pm_backlight@basic-brightness.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-1115g4: NOTRUN -> [SKIP][6] ([fdo#111827]) +8 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/fi-tgl-1115g4/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-1115g4: NOTRUN -> [SKIP][7] ([i915#4103]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/fi-tgl-1115g4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-1115g4: NOTRUN -> [SKIP][8] ([fdo#109285])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/fi-tgl-1115g4/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_psr@primary_mmap_gtt:
- fi-tgl-1115g4: NOTRUN -> [SKIP][9] ([i915#1072]) +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-1115g4: NOTRUN -> [SKIP][10] ([i915#3301])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/fi-tgl-1115g4/igt@prime_vgem@basic-userptr.html
#### Possible fixes ####
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: [INCOMPLETE][11] ([i915#2940]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@gt_lrc:
- fi-bsw-n3050: [DMESG-FAIL][13] ([i915#2373]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
Participating hosts (38 -> 37)
------------------------------
Additional (1): fi-tgl-1115g4
Missing (2): bat-dg1-6 bat-dg1-5
Build changes
-------------
* Linux: CI_DRM_10752 -> Patchwork_21368
CI-20190529: 20190529
CI_DRM_10752: c76aaeb23ed1eebb2af30e8ba3dca7c31b9f66ec @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6252: 996f2707195ed10c19905bcd8ccdb860a5e9d9c5 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21368: c83a5cef2006f8aa4919634eff6e2e4c8bbb3aff @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c83a5cef2006 drm/i915: Split vlv/chv sprite plane update into noarm+arm pair
437389a78c69 drm/i915: Split ivb+ sprite plane update into noarm+arm pair
1202bc6cfc3a drm/i915: Split g4x+ sprite plane update into noarm+arm pair
901268a16647 drm/i915: Split pre-skl primary plane update into noarm+arm pair
e1f91ae7cee9 drm/i915: Split skl+ plane update into noarm+arm pair
41063002deec drm/i915: Split update_plane() into update_noarm() + update_arm()
35deba336895 drm/i915: Fix up the sprite namespacing
9ca3181d87a4 drm/i915: Fix async flip with decryption and/or DPT
4347a5768329 drm/i915: Reject planar formats when doing async flips
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/index.html
[-- Attachment #2: Type: text/html, Size: 6726 bytes --]
^ permalink raw reply [flat|nested] 38+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Split plane updates to noarm+arm phases
2021-10-18 11:50 [Intel-gfx] [PATCH 0/9] drm/i915: Split plane updates to noarm+arm phases Ville Syrjala
` (11 preceding siblings ...)
2021-10-18 13:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-10-18 16:43 ` Patchwork
2021-10-20 22:39 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Split plane updates to noarm+arm phases (rev2) Patchwork
` (3 subsequent siblings)
16 siblings, 0 replies; 38+ messages in thread
From: Patchwork @ 2021-10-18 16:43 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30272 bytes --]
== Series Details ==
Series: drm/i915: Split plane updates to noarm+arm phases
URL : https://patchwork.freedesktop.org/series/95962/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10752_full -> Patchwork_21368_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21368_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21368_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21368_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_bw@linear-tiling-1-displays-2560x1440p:
- shard-snb: NOTRUN -> [FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-snb5/igt@kms_bw@linear-tiling-1-displays-2560x1440p.html
Known issues
------------
Here are the changes found in Patchwork_21368_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@legacy-engines-queued:
- shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +2 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-snb5/igt@gem_ctx_persistence@legacy-engines-queued.html
* igt@gem_ctx_sseu@invalid-sseu:
- shard-tglb: NOTRUN -> [SKIP][3] ([i915#280])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb5/igt@gem_ctx_sseu@invalid-sseu.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][4] -> [TIMEOUT][5] ([i915#2369] / [i915#3063] / [i915#3648])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-tglb7/igt@gem_eio@unwedge-stress.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb8/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][6] -> [FAIL][7] ([i915#2846])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-glk1/igt@gem_exec_fair@basic-deadline.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-glk6/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: [PASS][8] -> [FAIL][9] ([i915#2842]) +2 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-kbl2/igt@gem_exec_fair@basic-none-solo@rcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-kbl7/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][10] -> [FAIL][11] ([i915#2842])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-glk7/igt@gem_exec_fair@basic-throttle@rcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-glk6/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_whisper@basic-fds-all:
- shard-glk: [PASS][12] -> [DMESG-WARN][13] ([i915#118]) +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-glk3/igt@gem_exec_whisper@basic-fds-all.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-glk7/igt@gem_exec_whisper@basic-fds-all.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][14] -> [SKIP][15] ([i915#2190])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-tglb1/igt@gem_huc_copy@huc-copy.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb6/igt@gem_huc_copy@huc-copy.html
* igt@gem_media_vme:
- shard-tglb: NOTRUN -> [SKIP][16] ([i915#284])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb8/igt@gem_media_vme.html
* igt@gem_pxp@regular-baseline-src-copy-readible:
- shard-tglb: NOTRUN -> [SKIP][17] ([i915#4270])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb5/igt@gem_pxp@regular-baseline-src-copy-readible.html
* igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
- shard-kbl: NOTRUN -> [SKIP][18] ([fdo#109271]) +63 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-kbl3/igt@gem_render_copy@x-tiled-to-vebox-yf-tiled.html
* igt@gem_userptr_blits@readonly-pwrite-unsync:
- shard-tglb: NOTRUN -> [SKIP][19] ([i915#3297]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb8/igt@gem_userptr_blits@readonly-pwrite-unsync.html
* igt@gen7_exec_parse@bitmasks:
- shard-tglb: NOTRUN -> [SKIP][20] ([fdo#109289])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb5/igt@gen7_exec_parse@bitmasks.html
* igt@gen9_exec_parse@basic-rejected:
- shard-tglb: NOTRUN -> [SKIP][21] ([i915#2856]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb5/igt@gen9_exec_parse@basic-rejected.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-skl: [PASS][22] -> [DMESG-WARN][23] ([i915#1982])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-skl5/igt@i915_module_load@reload-with-fault-injection.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-skl10/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_suspend@debugfs-reader:
- shard-tglb: [PASS][24] -> [INCOMPLETE][25] ([i915#456])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-tglb1/igt@i915_suspend@debugfs-reader.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb7/igt@i915_suspend@debugfs-reader.html
* igt@i915_suspend@forcewake:
- shard-apl: NOTRUN -> [DMESG-WARN][26] ([i915#180]) +1 similar issue
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-apl3/igt@i915_suspend@forcewake.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][27] ([fdo#111614]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb1/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-apl: NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#3777]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-apl8/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][29] ([fdo#111615])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb5/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html
* igt@kms_bw@linear-tiling-2-displays-1920x1080p:
- shard-apl: NOTRUN -> [DMESG-FAIL][30] ([i915#4298]) +2 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-apl3/igt@kms_bw@linear-tiling-2-displays-1920x1080p.html
- shard-skl: NOTRUN -> [DMESG-FAIL][31] ([i915#4298])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-skl9/igt@kms_bw@linear-tiling-2-displays-1920x1080p.html
* igt@kms_bw@linear-tiling-2-displays-2560x1440p:
- shard-kbl: NOTRUN -> [DMESG-FAIL][32] ([i915#4298])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-kbl6/igt@kms_bw@linear-tiling-2-displays-2560x1440p.html
* igt@kms_bw@linear-tiling-5-displays-3840x2160p:
- shard-tglb: NOTRUN -> [FAIL][33] ([i915#1385]) +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb8/igt@kms_bw@linear-tiling-5-displays-3840x2160p.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][34] ([i915#3689]) +10 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb8/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][35] ([i915#3689] / [i915#3886])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb5/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#3886]) +9 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-apl8/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@hdmi-hpd-with-enabled-mode:
- shard-kbl: NOTRUN -> [SKIP][37] ([fdo#109271] / [fdo#111827]) +2 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-kbl6/igt@kms_chamelium@hdmi-hpd-with-enabled-mode.html
* igt@kms_chamelium@vga-hpd:
- shard-apl: NOTRUN -> [SKIP][38] ([fdo#109271] / [fdo#111827]) +16 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-apl8/igt@kms_chamelium@vga-hpd.html
* igt@kms_chamelium@vga-hpd-without-ddc:
- shard-snb: NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +13 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-snb6/igt@kms_chamelium@vga-hpd-without-ddc.html
* igt@kms_color_chamelium@pipe-b-ctm-0-75:
- shard-tglb: NOTRUN -> [SKIP][40] ([fdo#109284] / [fdo#111827]) +4 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb1/igt@kms_color_chamelium@pipe-b-ctm-0-75.html
* igt@kms_color_chamelium@pipe-c-degamma:
- shard-skl: NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-skl9/igt@kms_color_chamelium@pipe-c-degamma.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-tglb: NOTRUN -> [SKIP][42] ([i915#3116])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb1/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_content_protection@srm:
- shard-apl: NOTRUN -> [TIMEOUT][43] ([i915#1319]) +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-apl3/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@pipe-b-cursor-32x10-sliding:
- shard-skl: NOTRUN -> [SKIP][44] ([fdo#109271]) +6 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-skl7/igt@kms_cursor_crc@pipe-b-cursor-32x10-sliding.html
- shard-tglb: NOTRUN -> [SKIP][45] ([i915#3359]) +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb6/igt@kms_cursor_crc@pipe-b-cursor-32x10-sliding.html
- shard-iclb: NOTRUN -> [SKIP][46] ([fdo#109278])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-iclb6/igt@kms_cursor_crc@pipe-b-cursor-32x10-sliding.html
* igt@kms_cursor_crc@pipe-c-cursor-32x32-onscreen:
- shard-tglb: NOTRUN -> [SKIP][47] ([i915#3319]) +2 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb8/igt@kms_cursor_crc@pipe-c-cursor-32x32-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-512x512-offscreen:
- shard-tglb: NOTRUN -> [SKIP][48] ([fdo#109279] / [i915#3359])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb6/igt@kms_cursor_crc@pipe-d-cursor-512x512-offscreen.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [PASS][49] -> [FAIL][50] ([i915#2346] / [i915#533])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@2x-absolute-wf_vblank:
- shard-tglb: NOTRUN -> [SKIP][51] ([fdo#111825] / [i915#3966])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb8/igt@kms_flip@2x-absolute-wf_vblank.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][52] -> [FAIL][53] ([i915#79])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-msflip-blt:
- shard-snb: NOTRUN -> [SKIP][54] ([fdo#109271]) +311 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-snb6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-blt:
- shard-tglb: NOTRUN -> [SKIP][55] ([fdo#111825]) +16 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-iclb: NOTRUN -> [SKIP][56] ([fdo#109280])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-kbl: [PASS][57] -> [DMESG-WARN][58] ([i915#180]) +2 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-kbl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-kbl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][59] ([fdo#108145] / [i915#265]) +2 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][60] ([i915#265])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-apl8/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][61] -> [FAIL][62] ([fdo#108145] / [i915#265])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-tglb: NOTRUN -> [SKIP][63] ([i915#3536])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb8/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-2:
- shard-tglb: NOTRUN -> [SKIP][64] ([i915#2920])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb5/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html
- shard-apl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#658]) +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-apl2/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html
* igt@kms_psr2_su@frontbuffer:
- shard-kbl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#658])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-kbl3/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-tglb: NOTRUN -> [FAIL][67] ([i915#132] / [i915#3467]) +3 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb8/igt@kms_psr@psr2_cursor_plane_onoff.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][68] -> [SKIP][69] ([fdo#109441])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-iclb4/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> [FAIL][70] ([IGT#2])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-apl2/igt@kms_sysfs_edid_timing.html
* igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
- shard-tglb: [PASS][71] -> [INCOMPLETE][72] ([i915#2828] / [i915#456])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-tglb6/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb7/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-apl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#2437])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-apl2/igt@kms_writeback@writeback-invalid-parameters.html
* igt@nouveau_crc@pipe-a-ctx-flip-skip-current-frame:
- shard-tglb: NOTRUN -> [SKIP][74] ([i915#2530]) +2 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb5/igt@nouveau_crc@pipe-a-ctx-flip-skip-current-frame.html
* igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame:
- shard-apl: NOTRUN -> [SKIP][75] ([fdo#109271]) +174 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-apl6/igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame.html
* igt@prime_nv_api@i915_nv_import_twice:
- shard-tglb: NOTRUN -> [SKIP][76] ([fdo#109291])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb8/igt@prime_nv_api@i915_nv_import_twice.html
* igt@prime_vgem@basic-userptr:
- shard-tglb: NOTRUN -> [SKIP][77] ([i915#3301])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb8/igt@prime_vgem@basic-userptr.html
* igt@sysfs_clients@create:
- shard-tglb: NOTRUN -> [SKIP][78] ([i915#2994]) +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb8/igt@sysfs_clients@create.html
* igt@sysfs_clients@sema-25:
- shard-apl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#2994])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-apl2/igt@sysfs_clients@sema-25.html
* igt@sysfs_clients@split-50:
- shard-kbl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#2994]) +2 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-kbl6/igt@sysfs_clients@split-50.html
#### Possible fixes ####
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-tglb: [INCOMPLETE][81] ([i915#456]) -> [PASS][82] +2 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-tglb7/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb8/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_eio@unwedge-stress:
- shard-iclb: [TIMEOUT][83] ([i915#2369] / [i915#2481] / [i915#3070]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-iclb2/igt@gem_eio@unwedge-stress.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-iclb2/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-kbl: [FAIL][85] ([i915#2842]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-kbl7/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-kbl1/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-apl: [DMESG-WARN][87] ([i915#180]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-apl3/igt@gem_workarounds@suspend-resume-fd.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-apl6/igt@gem_workarounds@suspend-resume-fd.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][89] ([i915#180]) -> [PASS][90] +7 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][91] ([i915#2122]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [DMESG-WARN][93] ([i915#1982]) -> [PASS][94] +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-skl5/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend@b-edp1:
- shard-skl: [INCOMPLETE][95] ([i915#146] / [i915#198]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-skl3/igt@kms_flip@flip-vs-suspend@b-edp1.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-skl1/igt@kms_flip@flip-vs-suspend@b-edp1.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [FAIL][97] ([i915#1188]) -> [PASS][98] +1 similar issue
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-skl10/igt@kms_hdr@bpc-switch-suspend.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-skl2/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane_alpha_blend@pipe-d-alpha-basic:
- shard-tglb: [INCOMPLETE][99] -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-tglb8/igt@kms_plane_alpha_blend@pipe-d-alpha-basic.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-tglb1/igt@kms_plane_alpha_blend@pipe-d-alpha-basic.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [SKIP][101] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-iclb5/igt@kms_psr2_su@frontbuffer.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][103] ([i915#588]) -> [SKIP][104] ([i915#658])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-iclb5/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1:
- shard-iclb: [SKIP][105] ([i915#2920]) -> [SKIP][106] ([i915#658]) +2 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-iclb8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
- shard-iclb: [SKIP][107] ([i915#658]) -> [SKIP][108] ([i915#2920]) +1 similar issue
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-iclb8/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][109], [FAIL][110], [FAIL][111], [FAIL][112], [FAIL][113], [FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) -> ([FAIL][118], [FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124], [FAIL][125], [FAIL][126]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#3363])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-kbl1/igt@runner@aborted.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-kbl1/igt@runner@aborted.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-kbl7/igt@runner@aborted.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-kbl6/igt@runner@aborted.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-kbl6/igt@runner@aborted.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-kbl6/igt@runner@aborted.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-kbl7/igt@runner@aborted.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-kbl1/igt@runner@aborted.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-kbl1/igt@runner@aborted.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-kbl1/igt@runner@aborted.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-kbl1/igt@runner@aborted.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-kbl1/igt@runner@aborted.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-kbl7/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-kbl6/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-kbl7/igt@runner@aborted.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-kbl7/igt@runner@aborted.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-kbl7/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-kbl4/igt@runner@aborted.html
- shard-apl: ([FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#3363]) -> ([FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143]) ([i915#180] / [i915#3002] / [i915#3363])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-apl1/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-apl8/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-apl1/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-apl1/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-apl7/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-apl2/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10752/shard-apl3/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-apl3/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-apl3/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-apl1/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-apl3/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-apl6/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-apl1/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-apl3/igt@runner@aborted.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-apl8/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-apl3/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/shard-apl6/igt@runner@aborted.html
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1385]: https://gitlab.freedesktop.org/drm/intel/issues/1385
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#146]: http
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21368/index.html
[-- Attachment #2: Type: text/html, Size: 34902 bytes --]
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Intel-gfx] [PATCH 5/9] drm/i915: Split skl+ plane update into noarm+arm pair
2021-10-18 12:06 ` Lisovskiy, Stanislav
@ 2021-10-18 17:14 ` Ville Syrjälä
2021-10-18 17:22 ` Ville Syrjälä
0 siblings, 1 reply; 38+ messages in thread
From: Ville Syrjälä @ 2021-10-18 17:14 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
On Mon, Oct 18, 2021 at 03:06:34PM +0300, Lisovskiy, Stanislav wrote:
> On Mon, Oct 18, 2021 at 02:50:26PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Chop skl_program_plane() into two halves. Fist half becomes
> > the _noarm() variant, second part the _arm() variant.
> >
> > Fortunately I have already previously grouped the register
> > writes into roughtly the correct order, so the split looks
> > surprisingly clean.
> >
> > A few notable oddities I did not realize were self arming
> > are AUX_DIST and COLOR_CTL.
> >
> > i915_update_info doesn't look too terrible on my cfl running
> > kms_atomic_transition --r plane-all-transition --extended:
> > w/o patch w/ patch
> > Updates: 2178 Updates: 2018
> > | |
> > 1us | 1us |
> > | |
> > 4us | 4us |*****
> > |********* |**********
> > 16us |********** 16us |*******
> > |*** |
> > 66us | 66us |
> > | |
> > 262us | 262us |
> > | |
> > 1ms | 1ms |
> > | |
> > 4ms | 4ms |
> > | |
> > 17ms | 17ms |
> > | |
> > Min update: 8332ns Min update: 6164ns
> > Max update: 48758ns Max update: 31808ns
> > Average update: 19959ns Average update: 13159ns
> > Overruns > 100us: 0 Overruns > 100us: 0
> >
> > And with lockdep enabled:
> > w/o patch w/ patch
> > Updates: 2177 Updates: 2172
> > | |
> > 1us | 1us |
> > | |
> > 4us | 4us |
> > |******* |*********
> > 16us |********** 16us |**********
> > |******* |*
> > 66us | 66us |
> > | |
> > 262us | 262us |
> > | |
> > 1ms | 1ms |
> > | |
> > 4ms | 4ms |
> > | |
> > 17ms | 17ms |
> > | |
> > Min update: 12645ns Min update: 9980ns
> > Max update: 50153ns Max update: 33533ns
> > Average update: 25337ns Average update: 18245ns
> > Overruns > 250us: 0 Overruns > 250us: 0
> >
> > TODO: On icl+ everything seems to be armed by PLANE_SURF, so we
> > can optimize this even further on modern platforms. But I
> > think there's a bit of refactoring to be done first to
> > figure out the best way to go about it (eg. just reusing
> > the current skl+ functions, or doing a lower level split).
> >
> > TODO: Split scaler programming as well, but IIRC the scaler
> > has some oddball double buffering behaviour on some
> > platforms, so needs proper reverse engineering
> >
> > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Should I use that one as a base for further splitting, i.e for DG2?
> Which refactoring has to be done first, as I understand should be
> pretty safe to leave only PLANE_SURF update in arm section, and
> of course scaler is a different thing.
I'm not really sure which way we should do the skl+ vs. icl+ split.
Various ideas I've had:
- Definitly pull all the icl+ specific things out from the skl+
functions and stuff them into icl_plane_update_noarm()
- After that just call the remaining skl_plane_update_noarm()+arm()
back to back from icl_update_noarm() maybe? I don't like this
idea much actually.
- Maybe instead pull some sequences of register writes into small
helpers (eg. colorkey registers could be one). But dunno if there
are other clear groups to make this super useful.
- Or perhaps just pull most fiddly register value calculations
(aux_dist,ckey+alpha things,maybe others) into small helpers
to avoid duplicating themm but otherwise fully duplicate all
the actual register writes?
The sweet spot is probably some combination of those.
I was also thinking of doing an overhaul of the register
defines to use REG_BI() & co. That might help with approaches
that involves any amount of duplication.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Intel-gfx] [PATCH 5/9] drm/i915: Split skl+ plane update into noarm+arm pair
2021-10-18 17:14 ` Ville Syrjälä
@ 2021-10-18 17:22 ` Ville Syrjälä
0 siblings, 0 replies; 38+ messages in thread
From: Ville Syrjälä @ 2021-10-18 17:22 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
On Mon, Oct 18, 2021 at 08:14:04PM +0300, Ville Syrjälä wrote:
> On Mon, Oct 18, 2021 at 03:06:34PM +0300, Lisovskiy, Stanislav wrote:
> > On Mon, Oct 18, 2021 at 02:50:26PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Chop skl_program_plane() into two halves. Fist half becomes
> > > the _noarm() variant, second part the _arm() variant.
> > >
> > > Fortunately I have already previously grouped the register
> > > writes into roughtly the correct order, so the split looks
> > > surprisingly clean.
> > >
> > > A few notable oddities I did not realize were self arming
> > > are AUX_DIST and COLOR_CTL.
> > >
> > > i915_update_info doesn't look too terrible on my cfl running
> > > kms_atomic_transition --r plane-all-transition --extended:
> > > w/o patch w/ patch
> > > Updates: 2178 Updates: 2018
> > > | |
> > > 1us | 1us |
> > > | |
> > > 4us | 4us |*****
> > > |********* |**********
> > > 16us |********** 16us |*******
> > > |*** |
> > > 66us | 66us |
> > > | |
> > > 262us | 262us |
> > > | |
> > > 1ms | 1ms |
> > > | |
> > > 4ms | 4ms |
> > > | |
> > > 17ms | 17ms |
> > > | |
> > > Min update: 8332ns Min update: 6164ns
> > > Max update: 48758ns Max update: 31808ns
> > > Average update: 19959ns Average update: 13159ns
> > > Overruns > 100us: 0 Overruns > 100us: 0
> > >
> > > And with lockdep enabled:
> > > w/o patch w/ patch
> > > Updates: 2177 Updates: 2172
> > > | |
> > > 1us | 1us |
> > > | |
> > > 4us | 4us |
> > > |******* |*********
> > > 16us |********** 16us |**********
> > > |******* |*
> > > 66us | 66us |
> > > | |
> > > 262us | 262us |
> > > | |
> > > 1ms | 1ms |
> > > | |
> > > 4ms | 4ms |
> > > | |
> > > 17ms | 17ms |
> > > | |
> > > Min update: 12645ns Min update: 9980ns
> > > Max update: 50153ns Max update: 33533ns
> > > Average update: 25337ns Average update: 18245ns
> > > Overruns > 250us: 0 Overruns > 250us: 0
> > >
> > > TODO: On icl+ everything seems to be armed by PLANE_SURF, so we
> > > can optimize this even further on modern platforms. But I
> > > think there's a bit of refactoring to be done first to
> > > figure out the best way to go about it (eg. just reusing
> > > the current skl+ functions, or doing a lower level split).
> > >
> > > TODO: Split scaler programming as well, but IIRC the scaler
> > > has some oddball double buffering behaviour on some
> > > platforms, so needs proper reverse engineering
> > >
> > > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Should I use that one as a base for further splitting, i.e for DG2?
> > Which refactoring has to be done first, as I understand should be
> > pretty safe to leave only PLANE_SURF update in arm section, and
> > of course scaler is a different thing.
>
> I'm not really sure which way we should do the skl+ vs. icl+ split.
>
> Various ideas I've had:
> - Definitly pull all the icl+ specific things out from the skl+
> functions and stuff them into icl_plane_update_noarm()
> - After that just call the remaining skl_plane_update_noarm()+arm()
> back to back from icl_update_noarm() maybe? I don't like this
> idea much actually.
> - Maybe instead pull some sequences of register writes into small
> helpers (eg. colorkey registers could be one). But dunno if there
> are other clear groups to make this super useful.
> - Or perhaps just pull most fiddly register value calculations
> (aux_dist,ckey+alpha things,maybe others) into small helpers
> to avoid duplicating themm but otherwise fully duplicate all
> the actual register writes?
I guess that last thing is what I already did with skl_plane_surf()
earlier in the series. So maybe we should just embrace it fully.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 38+ messages in thread
* [Intel-gfx] [PATCH v2 6/9] drm/i915: Split pre-skl primary plane update into noarm+arm pair
2021-10-18 11:50 ` [Intel-gfx] [PATCH 6/9] drm/i915: Split pre-skl primary " Ville Syrjala
@ 2021-10-20 21:27 ` Ville Syrjala
2021-11-03 18:49 ` Lisovskiy, Stanislav
2021-11-03 18:47 ` [Intel-gfx] [PATCH " Lisovskiy, Stanislav
1 sibling, 1 reply; 38+ messages in thread
From: Ville Syrjala @ 2021-10-20 21:27 UTC (permalink / raw)
To: intel-gfx; +Cc: Stanislav Lisovskiy
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Chop i9xx_plane_update() into two halves. Fist half becomes
the _noarm() variant, second part the _arm() variant.
Fortunately I have already previously grouped the register
writes into roughtly the correct order, so the split looks
surprisingly clean.
One slightly surprising fact was that the CHV pipe B PRIMPOS/SIZE
registers are self arming unlike their pre-ctg DSPPOS/SIZE
counterparts. In fact all the new CHV pipe B registers are
self arming.
Also we must remind ourselves that i830/i845 are a bit borked
in that all of their plane registers are self-arming.
I didn't do any i915_update_info measurements for this one
alone. I'll get total numbers with the corrsponding sprite
plane changes.
v2: Don't break my precious i830/i845
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 85 ++++++++++++++++-------
1 file changed, 61 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 93163f9100a8..66aa79abe71c 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -418,32 +418,13 @@ static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
return DIV_ROUND_UP(pixel_rate * num, den);
}
-/* TODO: split into noarm+arm pair */
-static void i9xx_plane_update_arm(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
+static void i9xx_plane_update_noarm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
- u32 linear_offset;
- int x = plane_state->view.color_plane[0].x;
- int y = plane_state->view.color_plane[0].y;
- int crtc_x = plane_state->uapi.dst.x1;
- int crtc_y = plane_state->uapi.dst.y1;
- int crtc_w = drm_rect_width(&plane_state->uapi.dst);
- int crtc_h = drm_rect_height(&plane_state->uapi.dst);
unsigned long irqflags;
- u32 dspaddr_offset;
- u32 dspcntr;
-
- dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
-
- linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
-
- if (DISPLAY_VER(dev_priv) >= 4)
- dspaddr_offset = plane_state->view.color_plane[0].offset;
- else
- dspaddr_offset = linear_offset;
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
@@ -451,6 +432,11 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
plane_state->view.color_plane[0].stride);
if (DISPLAY_VER(dev_priv) < 4) {
+ int crtc_x = plane_state->uapi.dst.x1;
+ int crtc_y = plane_state->uapi.dst.y1;
+ int crtc_w = drm_rect_width(&plane_state->uapi.dst);
+ int crtc_h = drm_rect_height(&plane_state->uapi.dst);
+
/*
* PLANE_A doesn't actually have a full window
* generator but let's assume we still need to
@@ -460,7 +446,39 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
(crtc_y << 16) | crtc_x);
intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
((crtc_h - 1) << 16) | (crtc_w - 1));
- } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
+ }
+
+ spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+}
+
+static void i9xx_plane_update_arm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
+ int x = plane_state->view.color_plane[0].x;
+ int y = plane_state->view.color_plane[0].y;
+ u32 dspcntr, dspaddr_offset, linear_offset;
+ unsigned long irqflags;
+
+ dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
+
+ linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
+
+ if (DISPLAY_VER(dev_priv) >= 4)
+ dspaddr_offset = plane_state->view.color_plane[0].offset;
+ else
+ dspaddr_offset = linear_offset;
+
+ spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+
+ if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
+ int crtc_x = plane_state->uapi.dst.x1;
+ int crtc_y = plane_state->uapi.dst.y1;
+ int crtc_w = drm_rect_width(&plane_state->uapi.dst);
+ int crtc_h = drm_rect_height(&plane_state->uapi.dst);
+
intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane),
(crtc_y << 16) | crtc_x);
intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane),
@@ -494,6 +512,20 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
+static void i830_plane_update_arm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
+{
+ /*
+ * On i830/i845 all registers are self-arming [ALM040].
+ *
+ * Additional breakage on i830 causes register reads to return
+ * the last latched value instead of the last written value [ALM026].
+ */
+ i9xx_plane_update_noarm(plane, crtc_state, plane_state);
+ i9xx_plane_update_arm(plane, crtc_state, plane_state);
+}
+
static void i9xx_plane_disable_arm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state)
{
@@ -852,7 +884,12 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
plane->max_stride = ilk_primary_max_stride;
}
- plane->update_arm = i9xx_plane_update_arm;
+ if (IS_I830(dev_priv) || IS_I845G(dev_priv)) {
+ plane->update_arm = i830_plane_update_arm;
+ } else {
+ plane->update_noarm = i9xx_plane_update_noarm;
+ plane->update_arm = i9xx_plane_update_arm;
+ }
plane->disable_arm = i9xx_plane_disable_arm;
plane->get_hw_state = i9xx_plane_get_hw_state;
plane->check_plane = i9xx_plane_check;
--
2.32.0
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Split plane updates to noarm+arm phases (rev2)
2021-10-18 11:50 [Intel-gfx] [PATCH 0/9] drm/i915: Split plane updates to noarm+arm phases Ville Syrjala
` (12 preceding siblings ...)
2021-10-18 16:43 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2021-10-20 22:39 ` Patchwork
2021-10-20 22:40 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
16 siblings, 0 replies; 38+ messages in thread
From: Patchwork @ 2021-10-20 22:39 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Split plane updates to noarm+arm phases (rev2)
URL : https://patchwork.freedesktop.org/series/95962/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0af9d48ba766 drm/i915: Reject planar formats when doing async flips
d6008f7429e8 drm/i915: Fix async flip with decryption and/or DPT
0e1b125748d4 drm/i915: Fix up the sprite namespacing
ae42a64df447 drm/i915: Split update_plane() into update_noarm() + update_arm()
-:596: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#596: FILE: drivers/gpu/drm/i915/i915_trace.h:324:
+ TP_STRUCT__entry(
-:605: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#605: FILE: drivers/gpu/drm/i915/i915_trace.h:333:
+ TP_fast_assign(
-:614: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#614: FILE: drivers/gpu/drm/i915/i915_trace.h:342:
+ TP_printk("pipe %c, plane %s, frame=%u, scanline=%u, " DRM_RECT_FP_FMT " -> " DRM_RECT_FMT,
total: 0 errors, 1 warnings, 2 checks, 521 lines checked
d235981045de drm/i915: Split skl+ plane update into noarm+arm pair
de67af6ad7c0 drm/i915: Split pre-skl primary plane update into noarm+arm pair
aff585c97390 drm/i915: Split g4x+ sprite plane update into noarm+arm pair
3666ba39b832 drm/i915: Split ivb+ sprite plane update into noarm+arm pair
1108d9cc547a drm/i915: Split vlv/chv sprite plane update into noarm+arm pair
^ permalink raw reply [flat|nested] 38+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Split plane updates to noarm+arm phases (rev2)
2021-10-18 11:50 [Intel-gfx] [PATCH 0/9] drm/i915: Split plane updates to noarm+arm phases Ville Syrjala
` (13 preceding siblings ...)
2021-10-20 22:39 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Split plane updates to noarm+arm phases (rev2) Patchwork
@ 2021-10-20 22:40 ` Patchwork
2021-10-20 23:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-21 3:19 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
16 siblings, 0 replies; 38+ messages in thread
From: Patchwork @ 2021-10-20 22:40 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Split plane updates to noarm+arm phases (rev2)
URL : https://patchwork.freedesktop.org/series/95962/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
^ permalink raw reply [flat|nested] 38+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Split plane updates to noarm+arm phases (rev2)
2021-10-18 11:50 [Intel-gfx] [PATCH 0/9] drm/i915: Split plane updates to noarm+arm phases Ville Syrjala
` (14 preceding siblings ...)
2021-10-20 22:40 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-10-20 23:08 ` Patchwork
2021-10-21 3:19 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
16 siblings, 0 replies; 38+ messages in thread
From: Patchwork @ 2021-10-20 23:08 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6392 bytes --]
== Series Details ==
Series: drm/i915: Split plane updates to noarm+arm phases (rev2)
URL : https://patchwork.freedesktop.org/series/95962/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10766 -> Patchwork_21396
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/index.html
Known issues
------------
Here are the changes found in Patchwork_21396 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@query-info:
- fi-tgl-1115g4: NOTRUN -> [SKIP][1] ([fdo#109315])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/fi-tgl-1115g4/igt@amdgpu/amd_basic@query-info.html
* igt@amdgpu/amd_cs_nop@nop-gfx0:
- fi-tgl-1115g4: NOTRUN -> [SKIP][2] ([fdo#109315] / [i915#2575]) +16 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/fi-tgl-1115g4/igt@amdgpu/amd_cs_nop@nop-gfx0.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-1115g4: NOTRUN -> [SKIP][3] ([i915#2190])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/fi-tgl-1115g4/igt@gem_huc_copy@huc-copy.html
* igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4: NOTRUN -> [SKIP][4] ([i915#1155])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/fi-tgl-1115g4/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [PASS][5] -> [INCOMPLETE][6] ([i915#3921])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-1115g4: NOTRUN -> [SKIP][7] ([fdo#111827]) +8 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/fi-tgl-1115g4/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-1115g4: NOTRUN -> [SKIP][8] ([i915#4103]) +1 similar issue
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/fi-tgl-1115g4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_flip@basic-flip-vs-modeset@c-dp1:
- fi-cfl-8109u: [PASS][9] -> [FAIL][10] ([i915#4165]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-modeset@c-dp1.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-modeset@c-dp1.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-1115g4: NOTRUN -> [SKIP][11] ([fdo#109285])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/fi-tgl-1115g4/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][12] -> [DMESG-WARN][13] ([i915#4269])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [PASS][14] -> [DMESG-WARN][15] ([i915#295]) +18 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
* igt@kms_psr@primary_mmap_gtt:
- fi-tgl-1115g4: NOTRUN -> [SKIP][16] ([i915#1072]) +3 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-1115g4: NOTRUN -> [SKIP][17] ([i915#3301])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/fi-tgl-1115g4/igt@prime_vgem@basic-userptr.html
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4165]: https://gitlab.freedesktop.org/drm/intel/issues/4165
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
Participating hosts (40 -> 37)
------------------------------
Additional (1): fi-tgl-1115g4
Missing (4): fi-ctg-p8600 fi-bsw-cyan bat-dg1-6 fi-hsw-4200u
Build changes
-------------
* Linux: CI_DRM_10766 -> Patchwork_21396
CI-20190529: 20190529
CI_DRM_10766: ec5a16c84280673a3a09a67c445b0df3d205c30b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6258: 4c80c71d7dec29b6376846ae96bd04dc0b6e34d9 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21396: 1108d9cc547afb2ada79ad2a04a64ca709d0fef3 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
1108d9cc547a drm/i915: Split vlv/chv sprite plane update into noarm+arm pair
3666ba39b832 drm/i915: Split ivb+ sprite plane update into noarm+arm pair
aff585c97390 drm/i915: Split g4x+ sprite plane update into noarm+arm pair
de67af6ad7c0 drm/i915: Split pre-skl primary plane update into noarm+arm pair
d235981045de drm/i915: Split skl+ plane update into noarm+arm pair
ae42a64df447 drm/i915: Split update_plane() into update_noarm() + update_arm()
0e1b125748d4 drm/i915: Fix up the sprite namespacing
d6008f7429e8 drm/i915: Fix async flip with decryption and/or DPT
0af9d48ba766 drm/i915: Reject planar formats when doing async flips
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/index.html
[-- Attachment #2: Type: text/html, Size: 7432 bytes --]
^ permalink raw reply [flat|nested] 38+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Split plane updates to noarm+arm phases (rev2)
2021-10-18 11:50 [Intel-gfx] [PATCH 0/9] drm/i915: Split plane updates to noarm+arm phases Ville Syrjala
` (15 preceding siblings ...)
2021-10-20 23:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-10-21 3:19 ` Patchwork
16 siblings, 0 replies; 38+ messages in thread
From: Patchwork @ 2021-10-21 3:19 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 27038 bytes --]
== Series Details ==
Series: drm/i915: Split plane updates to noarm+arm phases (rev2)
URL : https://patchwork.freedesktop.org/series/95962/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10766_full -> Patchwork_21396_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_21396_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-skl: [PASS][1] -> [INCOMPLETE][2] ([i915#198]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-skl7/igt@gem_ctx_isolation@preservation-s3@vcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-skl8/igt@gem_ctx_isolation@preservation-s3@vcs0.html
* igt@gem_ctx_persistence@processes:
- shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-snb5/igt@gem_ctx_persistence@processes.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [PASS][4] -> [FAIL][5] ([i915#2842])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-tglb6/igt@gem_exec_fair@basic-pace@bcs0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-tglb3/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2876])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-tglb6/igt@gem_exec_fair@basic-pace@rcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-tglb3/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-tglb: NOTRUN -> [FAIL][8] ([i915#2842])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-tglb2/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_media_vme:
- shard-skl: NOTRUN -> [SKIP][9] ([fdo#109271]) +47 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-skl6/igt@gem_media_vme.html
* igt@gem_pread@exhaustion:
- shard-apl: NOTRUN -> [WARN][10] ([i915#2658])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-apl1/igt@gem_pread@exhaustion.html
- shard-skl: NOTRUN -> [WARN][11] ([i915#2658])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-skl6/igt@gem_pread@exhaustion.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-apl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#3323])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-apl3/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@readonly-unsync:
- shard-tglb: NOTRUN -> [SKIP][13] ([i915#3297])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-tglb5/igt@gem_userptr_blits@readonly-unsync.html
* igt@gen9_exec_parse@basic-rejected:
- shard-tglb: NOTRUN -> [SKIP][14] ([i915#2856])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-tglb5/igt@gen9_exec_parse@basic-rejected.html
* igt@i915_pm_rpm@dpms-non-lpsp:
- shard-tglb: NOTRUN -> [SKIP][15] ([fdo#111644] / [i915#1397] / [i915#2411])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-tglb5/igt@i915_pm_rpm@dpms-non-lpsp.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-0:
- shard-glk: [PASS][16] -> [DMESG-WARN][17] ([i915#118])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-glk6/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-glk1/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][18] ([i915#3743])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-skl6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-apl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3777]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-apl1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
- shard-apl: NOTRUN -> [SKIP][20] ([fdo#109271]) +278 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-apl1/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#3886]) +13 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-apl8/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#3886])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-skl6/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][23] ([i915#3689])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-tglb2/igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs.html
* igt@kms_chamelium@dp-crc-multiple:
- shard-skl: NOTRUN -> [SKIP][24] ([fdo#109271] / [fdo#111827]) +2 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-skl6/igt@kms_chamelium@dp-crc-multiple.html
* igt@kms_color_chamelium@pipe-a-ctm-0-25:
- shard-snb: NOTRUN -> [SKIP][25] ([fdo#109271] / [fdo#111827]) +13 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-snb7/igt@kms_color_chamelium@pipe-a-ctm-0-25.html
* igt@kms_color_chamelium@pipe-b-ctm-0-75:
- shard-tglb: NOTRUN -> [SKIP][26] ([fdo#109284] / [fdo#111827])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-tglb2/igt@kms_color_chamelium@pipe-b-ctm-0-75.html
* igt@kms_color_chamelium@pipe-c-ctm-0-25:
- shard-apl: NOTRUN -> [SKIP][27] ([fdo#109271] / [fdo#111827]) +27 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-apl2/igt@kms_color_chamelium@pipe-c-ctm-0-25.html
* igt@kms_color_chamelium@pipe-c-ctm-negative:
- shard-kbl: NOTRUN -> [SKIP][28] ([fdo#109271] / [fdo#111827]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-kbl1/igt@kms_color_chamelium@pipe-c-ctm-negative.html
* igt@kms_content_protection@atomic:
- shard-apl: NOTRUN -> [TIMEOUT][29] ([i915#1319])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-apl8/igt@kms_content_protection@atomic.html
* igt@kms_cursor_crc@pipe-b-cursor-512x170-random:
- shard-tglb: NOTRUN -> [SKIP][30] ([fdo#109279] / [i915#3359])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-tglb5/igt@kms_cursor_crc@pipe-b-cursor-512x170-random.html
* igt@kms_cursor_edge_walk@pipe-a-64x64-bottom-edge:
- shard-skl: [PASS][31] -> [DMESG-WARN][32] ([i915#1982])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-skl5/igt@kms_cursor_edge_walk@pipe-a-64x64-bottom-edge.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-skl9/igt@kms_cursor_edge_walk@pipe-a-64x64-bottom-edge.html
* igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge:
- shard-snb: NOTRUN -> [SKIP][33] ([fdo#109271]) +294 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-snb5/igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-tglb: NOTRUN -> [SKIP][34] ([fdo#111825]) +2 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-tglb5/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@pipe-d-torture-bo:
- shard-apl: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#533]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-apl8/igt@kms_cursor_legacy@pipe-d-torture-bo.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [PASS][36] -> [INCOMPLETE][37] ([i915#180] / [i915#636])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-kbl6/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][38] -> [FAIL][39] ([i915#2122])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [PASS][40] -> [DMESG-WARN][41] ([i915#180]) +9 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-apl: [PASS][42] -> [DMESG-WARN][43] ([i915#180]) +2 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-apl8/igt@kms_flip@flip-vs-suspend@a-dp1.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-apl1/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
- shard-apl: NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#2672])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-apl3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
* igt@kms_frontbuffer_tracking@fbcpsr-badstride:
- shard-kbl: NOTRUN -> [SKIP][45] ([fdo#109271]) +31 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-kbl1/igt@kms_frontbuffer_tracking@fbcpsr-badstride.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [PASS][46] -> [FAIL][47] ([i915#1188])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-skl7/igt@kms_hdr@bpc-switch.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-skl6/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: NOTRUN -> [FAIL][48] ([i915#1188])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-skl6/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#533])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-kbl1/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][50] ([i915#265])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-apl8/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][51] -> [FAIL][52] ([fdo#108145] / [i915#265])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-skl: NOTRUN -> [FAIL][53] ([fdo#108145] / [i915#265])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html
- shard-apl: NOTRUN -> [FAIL][54] ([fdo#108145] / [i915#265])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-apl1/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5:
- shard-apl: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#658]) +5 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-apl7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
- shard-kbl: NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#658])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-kbl1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
- shard-tglb: NOTRUN -> [SKIP][57] ([i915#2920])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-tglb5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
* igt@kms_setmode@basic:
- shard-snb: NOTRUN -> [FAIL][58] ([i915#31])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-snb2/igt@kms_setmode@basic.html
* igt@kms_writeback@writeback-check-output:
- shard-apl: NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#2437]) +2 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-apl7/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-skl: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#2437])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-skl6/igt@kms_writeback@writeback-invalid-parameters.html
* igt@nouveau_crc@pipe-d-ctx-flip-skip-current-frame:
- shard-tglb: NOTRUN -> [SKIP][61] ([i915#2530])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-tglb5/igt@nouveau_crc@pipe-d-ctx-flip-skip-current-frame.html
* igt@prime_vgem@fence-write-hang:
- shard-tglb: NOTRUN -> [SKIP][62] ([fdo#109295])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-tglb5/igt@prime_vgem@fence-write-hang.html
* igt@sysfs_clients@create:
- shard-apl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#2994]) +2 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-apl8/igt@sysfs_clients@create.html
#### Possible fixes ####
* igt@drm_mm@all@evict:
- shard-skl: [INCOMPLETE][64] ([i915#198]) -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-skl8/igt@drm_mm@all@evict.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-skl3/igt@drm_mm@all@evict.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-iclb: [FAIL][66] ([i915#2842]) -> [PASS][67] +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs0.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-iclb8/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [FAIL][68] ([i915#2842]) -> [PASS][69] +2 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-kbl7/igt@gem_exec_fair@basic-pace@vecs0.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-kbl7/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][70] ([i915#2849]) -> [PASS][71]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [INCOMPLETE][72] ([i915#3921]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-snb2/igt@i915_selftest@live@hangcheck.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-snb7/igt@i915_selftest@live@hangcheck.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [DMESG-WARN][74] ([i915#180]) -> [PASS][75] +2 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-apl8/igt@i915_suspend@fence-restore-tiled2untiled.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-apl3/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-kbl: [DMESG-WARN][76] ([i915#180]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-kbl6/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-kbl1/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [FAIL][78] ([i915#2346] / [i915#533]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [INCOMPLETE][80] ([i915#180] / [i915#1982]) -> [PASS][81]
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-apl7/igt@kms_fbcon_fbt@fbc-suspend.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-apl2/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][82] ([i915#1188]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-skl8/igt@kms_hdr@bpc-switch-dpms.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-skl3/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][84] ([fdo#108145] / [i915#265]) -> [PASS][85] +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@syncobj_timeline@reset-unsignaled:
- shard-skl: [DMESG-WARN][86] ([i915#1982]) -> [PASS][87] +1 similar issue
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-skl1/igt@syncobj_timeline@reset-unsignaled.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-skl10/igt@syncobj_timeline@reset-unsignaled.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][88] ([i915#1804] / [i915#2684]) -> [WARN][89] ([i915#2684])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-iclb6/igt@i915_pm_rc6_residency@rc6-idle.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-iclb5/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][90], [FAIL][91], [FAIL][92]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / [i915#4312]) -> ([FAIL][93], [FAIL][94], [FAIL][95], [FAIL][96], [FAIL][97], [FAIL][98], [FAIL][99], [FAIL][100], [FAIL][101]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / [i915#4312] / [i915#602] / [i915#92])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-kbl6/igt@runner@aborted.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-kbl4/igt@runner@aborted.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-kbl4/igt@runner@aborted.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-kbl6/igt@runner@aborted.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-kbl2/igt@runner@aborted.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-kbl6/igt@runner@aborted.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-kbl3/igt@runner@aborted.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-kbl6/igt@runner@aborted.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-kbl3/igt@runner@aborted.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-kbl3/igt@runner@aborted.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-kbl3/igt@runner@aborted.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-kbl3/igt@runner@aborted.html
- shard-apl: ([FAIL][102], [FAIL][103], [FAIL][104], [FAIL][105], [FAIL][106]) ([i915#180] / [i915#3363] / [i915#4312]) -> ([FAIL][107], [FAIL][108], [FAIL][109]) ([i915#180] / [i915#1814] / [i915#3363] / [i915#4312])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-apl8/igt@runner@aborted.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-apl7/igt@runner@aborted.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-apl8/igt@runner@aborted.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-apl3/igt@runner@aborted.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-apl3/igt@runner@aborted.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-apl2/igt@runner@aborted.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-apl1/igt@runner@aborted.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-apl6/igt@runner@aborted.html
- shard-skl: ([FAIL][110], [FAIL][111]) ([i915#3002] / [i915#3363] / [i915#4312]) -> ([FAIL][112], [FAIL][113], [FAIL][114]) ([i915#1436] / [i915#1814] / [i915#2029] / [i915#3002] / [i915#3363] / [i915#4312])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-skl2/igt@runner@aborted.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10766/shard-skl3/igt@runner@aborted.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-skl4/igt@runner@aborted.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-skl8/igt@runner@aborted.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/shard-skl3/igt@runner@aborted.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2876]: https://gitlab.freedesktop.org/drm/intel/issues/2876
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3777]: https://gitlab.freedesktop.org/drm/intel/issues/3777
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#602]: https://gitlab.freedesktop.org/drm/intel/issues/602
[i915#636]: https://gitlab.freedesktop.org/drm/intel/issues/636
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_10766 -> Patchwork_21396
CI-20190529: 20190529
CI_DRM_10766: ec5a16c84280673a3a09a67c445b0df3d205c30b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6258: 4c80c71d7dec29b6376846ae96bd04dc0b6e34d9 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21396: 1108d9cc547afb2ada79ad2a04a64ca709d0fef3 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21396/index.html
[-- Attachment #2: Type: text/html, Size: 34429 bytes --]
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Intel-gfx] [PATCH 1/9] drm/i915: Reject planar formats when doing async flips
2021-10-18 11:50 ` [Intel-gfx] [PATCH 1/9] drm/i915: Reject planar formats when doing async flips Ville Syrjala
@ 2021-10-27 16:12 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 38+ messages in thread
From: Lisovskiy, Stanislav @ 2021-10-27 16:12 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx, Karthik B S
On Mon, Oct 18, 2021 at 02:50:22PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Async flips are only capable of changing PLANE_SURF, hence we
> they can't easily be used with planar formats.
>
> Older platforms could require updating AUX_DIST as well, which
> is not possible. We'd have to make sure AUX_DIST doesn't change
> before allowing the async flip through. If we could get async
> flips with CCS then that might be interesting, but since the hw
> doesn't allow async flips with CCS I don't see much point in
> allowing this for planar formats either. No one renders their
> game content in YUV anyway.
>
> icl+ could in theory do this I suppose since each color plane
> has its own PLANE_SURF register, but I don't know if there is
> some magic to guarantee that both the Y and UV plane would
> async flip synchronously if you will. Ie. beyond just a clean
> tear we'd potentially get some kind of weird tear with some
> random mix of luma and chroma from the old and new frames.
>
> So let's just say no to async flips when scanning out planar
> formats.
>
> Cc: Karthik B S <karthik.b.s@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index ce5d6633029a..8bb87e839f4a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -8884,6 +8884,12 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
> return -EINVAL;
> }
>
> + if (new_plane_state->hw.fb->format->num_planes > 1) {
> + drm_dbg_kms(&i915->drm,
> + "Planar formats not supported with async flips\n");
> + return -EINVAL;
> + }
> +
> if (old_plane_state->view.color_plane[0].stride !=
> new_plane_state->view.color_plane[0].stride) {
> drm_dbg_kms(&i915->drm, "Stride cannot be changed in async flip\n");
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Intel-gfx] [PATCH 4/9] drm/i915: Split update_plane() into update_noarm() + update_arm()
2021-10-18 11:50 ` [Intel-gfx] [PATCH 4/9] drm/i915: Split update_plane() into update_noarm() + update_arm() Ville Syrjala
@ 2021-10-27 16:35 ` Lisovskiy, Stanislav
2021-11-03 18:47 ` Lisovskiy, Stanislav
1 sibling, 0 replies; 38+ messages in thread
From: Lisovskiy, Stanislav @ 2021-10-27 16:35 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Mon, Oct 18, 2021 at 02:50:25PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The amount of plane registers we have to write has been steadily
> increasing, putting more pressure on the vblank evasion mechanism
> and forcing us to increase its time budget. Let's try to take some
> of the pressure off by splitting plane updates into two parts:
> 1) write all non-self arming plane registers, ie. the registers
> where the write actually does nothing until a separate arming
> register is also written which will cause the hardware to latch
> the new register values at the next start of vblank
> 2) write all self arming plane registers, ie. registers which always
> just latch at the next start of vblank, and registers which also
> arm other registers to do so
>
> Here we just provide the mechanism, but don't actually implement
> the split on any platform yet. so everything stays now in the _arm()
> hooks. Subsequently we can move a whole bunch of stuff into the
> _noarm() part, especially in more modern platforms where the number
> of registers we have to write is also the greatest. On older
> platforms this is less beneficial probably, but no real reason
> to deviate from a common behaviour.
>
> And let's sprinkle some TODOs around the areas that will need
> adapting.
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c | 15 ++--
> .../gpu/drm/i915/display/intel_atomic_plane.c | 88 ++++++++++++++-----
> .../gpu/drm/i915/display/intel_atomic_plane.h | 23 +++--
> drivers/gpu/drm/i915/display/intel_cursor.c | 44 +++++-----
> drivers/gpu/drm/i915/display/intel_display.c | 12 +--
> .../drm/i915/display/intel_display_types.h | 12 ++-
> drivers/gpu/drm/i915/display/intel_sprite.c | 44 +++++-----
> .../drm/i915/display/skl_universal_plane.c | 15 ++--
> drivers/gpu/drm/i915/i915_trace.h | 33 ++++++-
> 9 files changed, 192 insertions(+), 94 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index b1439ba78f67..93163f9100a8 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -418,9 +418,10 @@ static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
> return DIV_ROUND_UP(pixel_rate * num, den);
> }
>
> -static void i9xx_update_plane(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state)
> +/* TODO: split into noarm+arm pair */
> +static void i9xx_plane_update_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> @@ -493,8 +494,8 @@ static void i9xx_update_plane(struct intel_plane *plane,
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
>
> -static void i9xx_disable_plane(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state)
> +static void i9xx_plane_disable_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> @@ -851,8 +852,8 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> plane->max_stride = ilk_primary_max_stride;
> }
>
> - plane->update_plane = i9xx_update_plane;
> - plane->disable_plane = i9xx_disable_plane;
> + plane->update_arm = i9xx_plane_update_arm;
> + plane->disable_arm = i9xx_plane_disable_arm;
> plane->get_hw_state = i9xx_plane_get_hw_state;
> plane->check_plane = i9xx_plane_check;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 0be8c00e3db9..ae21770fc321 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -469,31 +469,72 @@ skl_next_plane_to_commit(struct intel_atomic_state *state,
> return NULL;
> }
>
> -void intel_update_plane(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state)
> +void intel_plane_update_noarm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> - trace_intel_update_plane(&plane->base, crtc);
> + trace_intel_plane_update_noarm(&plane->base, crtc);
> +
> + if (plane->update_noarm)
> + plane->update_noarm(plane, crtc_state, plane_state);
> +}
> +
> +void intel_plane_update_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +
> + trace_intel_plane_update_arm(&plane->base, crtc);
>
> if (crtc_state->uapi.async_flip && plane->async_flip)
> plane->async_flip(plane, crtc_state, plane_state, true);
> else
> - plane->update_plane(plane, crtc_state, plane_state);
> + plane->update_arm(plane, crtc_state, plane_state);
> }
>
> -void intel_disable_plane(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state)
> +void intel_plane_disable_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> - trace_intel_disable_plane(&plane->base, crtc);
> - plane->disable_plane(plane, crtc_state);
> + trace_intel_plane_disable_arm(&plane->base, crtc);
> + plane->disable_arm(plane, crtc_state);
> }
>
> -void skl_update_planes_on_crtc(struct intel_atomic_state *state,
> - struct intel_crtc *crtc)
> +void intel_update_planes_on_crtc(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> +{
> + struct intel_crtc_state *new_crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + u32 update_mask = new_crtc_state->update_planes;
> + struct intel_plane_state *new_plane_state;
> + struct intel_plane *plane;
> + int i;
> +
> + if (new_crtc_state->uapi.async_flip)
> + return;
> +
> + /*
> + * Since we only write non-arming registers here,
> + * the order does not matter even for skl+.
> + */
> + for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
> + if (crtc->pipe != plane->pipe ||
> + !(update_mask & BIT(plane->id)))
> + continue;
> +
> + /* TODO: for mailbox updates this should be skipped */
> + if (new_plane_state->uapi.visible ||
> + new_plane_state->planar_slave)
> + intel_plane_update_noarm(plane, new_crtc_state, new_plane_state);
> + }
> +}
> +
> +void skl_arm_planes_on_crtc(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> struct intel_crtc_state *old_crtc_state =
> intel_atomic_get_old_crtc_state(state, crtc);
> @@ -515,17 +556,20 @@ void skl_update_planes_on_crtc(struct intel_atomic_state *state,
> struct intel_plane_state *new_plane_state =
> intel_atomic_get_new_plane_state(state, plane);
>
> + /*
> + * TODO: for mailbox updates intel_plane_update_noarm()
> + * would have to be called here as well.
> + */
> if (new_plane_state->uapi.visible ||
> - new_plane_state->planar_slave) {
> - intel_update_plane(plane, new_crtc_state, new_plane_state);
> - } else {
> - intel_disable_plane(plane, new_crtc_state);
> - }
> + new_plane_state->planar_slave)
> + intel_plane_update_arm(plane, new_crtc_state, new_plane_state);
> + else
> + intel_plane_disable_arm(plane, new_crtc_state);
> }
> }
>
> -void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
> - struct intel_crtc *crtc)
> +void i9xx_arm_planes_on_crtc(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> @@ -539,10 +583,14 @@ void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
> !(update_mask & BIT(plane->id)))
> continue;
>
> + /*
> + * TODO: for mailbox updates intel_plane_update_noarm()
> + * would have to be called here as well.
> + */
> if (new_plane_state->uapi.visible)
> - intel_update_plane(plane, new_crtc_state, new_plane_state);
> + intel_plane_update_arm(plane, new_crtc_state, new_plane_state);
> else
> - intel_disable_plane(plane, new_crtc_state);
> + intel_plane_disable_arm(plane, new_crtc_state);
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> index 62e5a2a77fd4..7907f601598e 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> @@ -30,20 +30,25 @@ void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
> struct intel_crtc *crtc);
> void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,
> const struct intel_plane_state *from_plane_state);
> -void intel_update_plane(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state);
> -void intel_disable_plane(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state);
> +void intel_plane_update_noarm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state);
> +void intel_plane_update_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state);
> +void intel_plane_disable_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state);
> struct intel_plane *intel_plane_alloc(void);
> void intel_plane_free(struct intel_plane *plane);
> struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
> void intel_plane_destroy_state(struct drm_plane *plane,
> struct drm_plane_state *state);
> -void skl_update_planes_on_crtc(struct intel_atomic_state *state,
> - struct intel_crtc *crtc);
> -void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
> - struct intel_crtc *crtc);
> +void intel_update_planes_on_crtc(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> +void skl_arm_planes_on_crtc(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> +void i9xx_arm_planes_on_crtc(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
> struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *old_plane_state,
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> index 11842f212613..826337a769b5 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> @@ -253,9 +253,10 @@ static int i845_check_cursor(struct intel_crtc_state *crtc_state,
> return 0;
> }
>
> -static void i845_update_cursor(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state)
> +/* TODO: split into noarm+arm pair */
> +static void i845_cursor_update_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> u32 cntl = 0, base = 0, pos = 0, size = 0;
> @@ -298,10 +299,10 @@ static void i845_update_cursor(struct intel_plane *plane,
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
>
> -static void i845_disable_cursor(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state)
> +static void i845_cursor_disable_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state)
> {
> - i845_update_cursor(plane, crtc_state, NULL);
> + i845_cursor_update_arm(plane, crtc_state, NULL);
> }
>
> static bool i845_cursor_get_hw_state(struct intel_plane *plane,
> @@ -488,9 +489,10 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
> return 0;
> }
>
> -static void i9xx_update_cursor(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state)
> +/* TODO: split into noarm+arm pair */
> +static void i9xx_cursor_update_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
> @@ -562,10 +564,10 @@ static void i9xx_update_cursor(struct intel_plane *plane,
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
>
> -static void i9xx_disable_cursor(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state)
> +static void i9xx_cursor_disable_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state)
> {
> - i9xx_update_cursor(plane, crtc_state, NULL);
> + i9xx_cursor_update_arm(plane, crtc_state, NULL);
> }
>
> static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
> @@ -717,10 +719,12 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
> */
> crtc_state->active_planes = new_crtc_state->active_planes;
>
> - if (new_plane_state->uapi.visible)
> - intel_update_plane(plane, crtc_state, new_plane_state);
> - else
> - intel_disable_plane(plane, crtc_state);
> + if (new_plane_state->uapi.visible) {
> + intel_plane_update_noarm(plane, crtc_state, new_plane_state);
> + intel_plane_update_arm(plane, crtc_state, new_plane_state);
> + } else {
> + intel_plane_disable_arm(plane, crtc_state);
> + }
>
> intel_plane_unpin_fb(old_plane_state);
>
> @@ -766,14 +770,14 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
>
> if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
> cursor->max_stride = i845_cursor_max_stride;
> - cursor->update_plane = i845_update_cursor;
> - cursor->disable_plane = i845_disable_cursor;
> + cursor->update_arm = i845_cursor_update_arm;
> + cursor->disable_arm = i845_cursor_disable_arm;
> cursor->get_hw_state = i845_cursor_get_hw_state;
> cursor->check_plane = i845_check_cursor;
> } else {
> cursor->max_stride = i9xx_cursor_max_stride;
> - cursor->update_plane = i9xx_update_cursor;
> - cursor->disable_plane = i9xx_disable_cursor;
> + cursor->update_arm = i9xx_cursor_update_arm;
> + cursor->disable_arm = i9xx_cursor_disable_arm;
> cursor->get_hw_state = i9xx_cursor_get_hw_state;
> cursor->check_plane = i9xx_check_cursor;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 8bb87e839f4a..a685aad738f3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1126,7 +1126,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
> if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
> intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
>
> - intel_disable_plane(plane, crtc_state);
> + intel_plane_disable_arm(plane, crtc_state);
> intel_wait_for_vblank(dev_priv, crtc->pipe);
> }
>
> @@ -2156,7 +2156,7 @@ static void intel_crtc_disable_planes(struct intel_atomic_state *state,
> !(update_mask & BIT(plane->id)))
> continue;
>
> - intel_disable_plane(plane, new_crtc_state);
> + intel_plane_disable_arm(plane, new_crtc_state);
>
> if (old_plane_state->uapi.visible)
> fb_bits |= plane->frontbuffer_bit;
> @@ -2423,7 +2423,7 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct intel_plane *plane = to_intel_plane(crtc->base.primary);
>
> - plane->disable_plane(plane, crtc_state);
> + plane->disable_arm(plane, crtc_state);
> }
>
> static void ilk_crtc_enable(struct intel_atomic_state *state,
> @@ -9387,15 +9387,17 @@ static void intel_update_crtc(struct intel_atomic_state *state,
>
> intel_fbc_update(state, crtc);
>
> + intel_update_planes_on_crtc(state, crtc);
> +
> /* Perform vblank evasion around commit operation */
> intel_pipe_update_start(new_crtc_state);
>
> commit_pipe_pre_planes(state, crtc);
>
> if (DISPLAY_VER(dev_priv) >= 9)
> - skl_update_planes_on_crtc(state, crtc);
> + skl_arm_planes_on_crtc(state, crtc);
> else
> - i9xx_update_planes_on_crtc(state, crtc);
> + i9xx_arm_planes_on_crtc(state, crtc);
>
> commit_pipe_post_planes(state, crtc);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 39e11eaec1a3..907389fd6f85 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1362,11 +1362,17 @@ struct intel_plane {
> unsigned int (*max_stride)(struct intel_plane *plane,
> u32 pixel_format, u64 modifier,
> unsigned int rotation);
> - void (*update_plane)(struct intel_plane *plane,
> + /* Write all non-self arming plane registers */
> + void (*update_noarm)(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state);
> - void (*disable_plane)(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state);
> + /* Write all self-arming plane registers */
> + void (*update_arm)(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state);
> + /* Disable the plane, must arm */
> + void (*disable_arm)(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state);
> bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
> int (*check_plane)(struct intel_crtc_state *crtc_state,
> struct intel_plane_state *plane_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 1daa3360cf02..9c36c1492b33 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -416,10 +416,11 @@ static void vlv_sprite_update_gamma(const struct intel_plane_state *plane_state)
> gamma[i] << 16 | gamma[i] << 8 | gamma[i]);
> }
>
> +/* TODO: split into noarm+arm pair */
> static void
> -vlv_sprite_update(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state)
> +vlv_sprite_update_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
> @@ -485,8 +486,8 @@ vlv_sprite_update(struct intel_plane *plane,
> }
>
> static void
> -vlv_sprite_disable(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state)
> +vlv_sprite_disable_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
> @@ -834,10 +835,11 @@ static void ivb_sprite_update_gamma(const struct intel_plane_state *plane_state)
> i++;
> }
>
> +/* TODO: split into noarm+arm pair */
> static void
> -ivb_sprite_update(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state)
> +ivb_sprite_update_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
> @@ -908,8 +910,8 @@ ivb_sprite_update(struct intel_plane *plane,
> }
>
> static void
> -ivb_sprite_disable(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state)
> +ivb_sprite_disable_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
> @@ -1163,9 +1165,9 @@ static void ilk_sprite_update_gamma(const struct intel_plane_state *plane_state)
> }
>
> static void
> -g4x_sprite_update(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state)
> +g4x_sprite_update_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
> @@ -1232,8 +1234,8 @@ g4x_sprite_update(struct intel_plane *plane,
> }
>
> static void
> -g4x_sprite_disable(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state)
> +g4x_sprite_disable_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
> @@ -1762,8 +1764,8 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> return plane;
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> - plane->update_plane = vlv_sprite_update;
> - plane->disable_plane = vlv_sprite_disable;
> + plane->update_arm = vlv_sprite_update_arm;
> + plane->disable_arm = vlv_sprite_disable_arm;
> plane->get_hw_state = vlv_sprite_get_hw_state;
> plane->check_plane = vlv_sprite_check;
> plane->max_stride = i965_plane_max_stride;
> @@ -1780,8 +1782,8 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>
> plane_funcs = &vlv_sprite_funcs;
> } else if (DISPLAY_VER(dev_priv) >= 7) {
> - plane->update_plane = ivb_sprite_update;
> - plane->disable_plane = ivb_sprite_disable;
> + plane->update_arm = ivb_sprite_update_arm;
> + plane->disable_arm = ivb_sprite_disable_arm;
> plane->get_hw_state = ivb_sprite_get_hw_state;
> plane->check_plane = g4x_sprite_check;
>
> @@ -1799,8 +1801,8 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>
> plane_funcs = &snb_sprite_funcs;
> } else {
> - plane->update_plane = g4x_sprite_update;
> - plane->disable_plane = g4x_sprite_disable;
> + plane->update_arm = g4x_sprite_update_arm;
> + plane->disable_arm = g4x_sprite_disable_arm;
> plane->get_hw_state = g4x_sprite_get_hw_state;
> plane->check_plane = g4x_sprite_check;
> plane->max_stride = g4x_sprite_max_stride;
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index e2f024449149..74f3870d39b1 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -642,8 +642,8 @@ static u32 skl_plane_stride(const struct intel_plane_state *plane_state,
> }
>
> static void
> -skl_disable_plane(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state)
> +skl_plane_disable_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum plane_id plane_id = plane->id;
> @@ -1199,10 +1199,11 @@ skl_plane_async_flip(struct intel_plane *plane,
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
>
> +/* TODO: split into noarm+arm pair */
> static void
> -skl_update_plane(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state)
> +skl_plane_update_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> {
> int color_plane = 0;
>
> @@ -2158,8 +2159,8 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
> }
>
> plane->max_stride = skl_plane_max_stride;
> - plane->update_plane = skl_update_plane;
> - plane->disable_plane = skl_disable_plane;
> + plane->update_arm = skl_plane_update_arm;
> + plane->disable_arm = skl_plane_disable_arm;
> plane->get_hw_state = skl_plane_get_hw_state;
> plane->check_plane = skl_plane_check;
>
> diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
> index 9795f456cccf..214696d6b270 100644
> --- a/drivers/gpu/drm/i915/i915_trace.h
> +++ b/drivers/gpu/drm/i915/i915_trace.h
> @@ -288,7 +288,7 @@ TRACE_EVENT(vlv_fifo_size,
>
> /* plane updates */
>
> -TRACE_EVENT(intel_update_plane,
> +TRACE_EVENT(intel_plane_update_noarm,
> TP_PROTO(struct drm_plane *plane, struct intel_crtc *crtc),
> TP_ARGS(plane, crtc),
>
> @@ -317,7 +317,36 @@ TRACE_EVENT(intel_update_plane,
> DRM_RECT_ARG((const struct drm_rect *)__entry->dst))
> );
>
> -TRACE_EVENT(intel_disable_plane,
> +TRACE_EVENT(intel_plane_update_arm,
> + TP_PROTO(struct drm_plane *plane, struct intel_crtc *crtc),
> + TP_ARGS(plane, crtc),
> +
> + TP_STRUCT__entry(
> + __field(enum pipe, pipe)
> + __field(u32, frame)
> + __field(u32, scanline)
> + __array(int, src, 4)
> + __array(int, dst, 4)
> + __string(name, plane->name)
> + ),
> +
> + TP_fast_assign(
> + __assign_str(name, plane->name);
> + __entry->pipe = crtc->pipe;
> + __entry->frame = intel_crtc_get_vblank_counter(crtc);
> + __entry->scanline = intel_get_crtc_scanline(crtc);
> + memcpy(__entry->src, &plane->state->src, sizeof(__entry->src));
> + memcpy(__entry->dst, &plane->state->dst, sizeof(__entry->dst));
> + ),
> +
> + TP_printk("pipe %c, plane %s, frame=%u, scanline=%u, " DRM_RECT_FP_FMT " -> " DRM_RECT_FMT,
> + pipe_name(__entry->pipe), __get_str(name),
> + __entry->frame, __entry->scanline,
> + DRM_RECT_FP_ARG((const struct drm_rect *)__entry->src),
> + DRM_RECT_ARG((const struct drm_rect *)__entry->dst))
> +);
> +
> +TRACE_EVENT(intel_plane_disable_arm,
> TP_PROTO(struct drm_plane *plane, struct intel_crtc *crtc),
> TP_ARGS(plane, crtc),
>
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Intel-gfx] [PATCH 5/9] drm/i915: Split skl+ plane update into noarm+arm pair
2021-10-18 11:50 ` [Intel-gfx] [PATCH 5/9] drm/i915: Split skl+ plane update into noarm+arm pair Ville Syrjala
2021-10-18 12:06 ` Lisovskiy, Stanislav
@ 2021-10-27 17:11 ` Lisovskiy, Stanislav
2021-10-28 13:03 ` Ville Syrjälä
2021-11-03 18:46 ` Lisovskiy, Stanislav
2 siblings, 1 reply; 38+ messages in thread
From: Lisovskiy, Stanislav @ 2021-10-27 17:11 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Mon, Oct 18, 2021 at 02:50:26PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Chop skl_program_plane() into two halves. Fist half becomes
> the _noarm() variant, second part the _arm() variant.
>
> Fortunately I have already previously grouped the register
> writes into roughtly the correct order, so the split looks
> surprisingly clean.
>
> A few notable oddities I did not realize were self arming
> are AUX_DIST and COLOR_CTL.
>
> i915_update_info doesn't look too terrible on my cfl running
> kms_atomic_transition --r plane-all-transition --extended:
> w/o patch w/ patch
> Updates: 2178 Updates: 2018
> | |
> 1us | 1us |
> | |
> 4us | 4us |*****
> |********* |**********
> 16us |********** 16us |*******
> |*** |
> 66us | 66us |
> | |
> 262us | 262us |
> | |
> 1ms | 1ms |
> | |
> 4ms | 4ms |
> | |
> 17ms | 17ms |
> | |
> Min update: 8332ns Min update: 6164ns
> Max update: 48758ns Max update: 31808ns
> Average update: 19959ns Average update: 13159ns
> Overruns > 100us: 0 Overruns > 100us: 0
>
> And with lockdep enabled:
> w/o patch w/ patch
> Updates: 2177 Updates: 2172
> | |
> 1us | 1us |
> | |
> 4us | 4us |
> |******* |*********
> 16us |********** 16us |**********
> |******* |*
> 66us | 66us |
> | |
> 262us | 262us |
> | |
> 1ms | 1ms |
> | |
> 4ms | 4ms |
> | |
> 17ms | 17ms |
> | |
> Min update: 12645ns Min update: 9980ns
> Max update: 50153ns Max update: 33533ns
> Average update: 25337ns Average update: 18245ns
> Overruns > 250us: 0 Overruns > 250us: 0
>
> TODO: On icl+ everything seems to be armed by PLANE_SURF, so we
> can optimize this even further on modern platforms. But I
> think there's a bit of refactoring to be done first to
> figure out the best way to go about it (eg. just reusing
> the current skl+ functions, or doing a lower level split).
>
> TODO: Split scaler programming as well, but IIRC the scaler
> has some oddball double buffering behaviour on some
> platforms, so needs proper reverse engineering
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> .../drm/i915/display/skl_universal_plane.c | 113 +++++++++++-------
> 1 file changed, 72 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 74f3870d39b1..2a822e1e465e 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -1050,60 +1050,32 @@ static void icl_plane_csc_load_black(struct intel_plane *plane)
> }
>
> static void
> -skl_program_plane(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state,
> - int color_plane)
> +skl_program_plane_noarm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state,
> + int color_plane)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum plane_id plane_id = plane->id;
> enum pipe pipe = plane->pipe;
> - const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> u32 stride = skl_plane_stride(plane_state, color_plane);
> const struct drm_framebuffer *fb = plane_state->hw.fb;
> - int aux_plane = skl_main_to_aux_plane(fb, color_plane);
> int crtc_x = plane_state->uapi.dst.x1;
> int crtc_y = plane_state->uapi.dst.y1;
> - u32 x = plane_state->view.color_plane[color_plane].x;
> - u32 y = plane_state->view.color_plane[color_plane].y;
> u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
> u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
> - u8 alpha = plane_state->hw.alpha >> 8;
> - u32 plane_color_ctl = 0, aux_dist = 0;
> unsigned long irqflags;
> - u32 keymsk, keymax;
> - u32 plane_ctl = plane_state->ctl;
> -
> - plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> -
> - if (DISPLAY_VER(dev_priv) >= 10)
> - plane_color_ctl = plane_state->color_ctl |
> - glk_plane_color_ctl_crtc(crtc_state);
>
> /* Sizes are 0 based */
> src_w--;
> src_h--;
>
> - keymax = (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
> -
> - keymsk = key->channel_mask & 0x7ffffff;
> - if (alpha < 0xff)
> - keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
> -
> /* The scaler will handle the output position */
> if (plane_state->scaler_id >= 0) {
> crtc_x = 0;
> crtc_y = 0;
> }
>
> - if (aux_plane) {
> - aux_dist = skl_surf_address(plane_state, aux_plane) -
> - skl_surf_address(plane_state, color_plane);
> -
> - if (DISPLAY_VER(dev_priv) < 12)
> - aux_dist |= skl_plane_stride(plane_state, aux_plane);
> - }
> -
> spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>
> /*
> @@ -1119,16 +1091,10 @@ skl_program_plane(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
> (src_h << 16) | src_w);
>
> - intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);
> -
> if (icl_is_hdr_plane(dev_priv, plane_id))
> intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id),
> plane_state->cus_ctl);
>
> - if (DISPLAY_VER(dev_priv) >= 10)
> - intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id),
> - plane_color_ctl);
> -
> if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
> icl_program_input_csc(plane, crtc_state, plane_state);
>
> @@ -1138,6 +1104,52 @@ skl_program_plane(struct intel_plane *plane,
>
> skl_write_plane_wm(plane, crtc_state);
>
> + intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane);
> +
> + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> +}
> +
> +static void
> +skl_program_plane_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state,
> + int color_plane)
> +{
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + enum plane_id plane_id = plane->id;
> + enum pipe pipe = plane->pipe;
> + const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> + const struct drm_framebuffer *fb = plane_state->hw.fb;
> + int aux_plane = skl_main_to_aux_plane(fb, color_plane);
> + u32 x = plane_state->view.color_plane[color_plane].x;
> + u32 y = plane_state->view.color_plane[color_plane].y;
> + u32 keymsk, keymax, aux_dist = 0, plane_color_ctl = 0;
> + u8 alpha = plane_state->hw.alpha >> 8;
> + u32 plane_ctl = plane_state->ctl;
> + unsigned long irqflags;
> +
> + plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> +
> + if (DISPLAY_VER(dev_priv) >= 10)
> + plane_color_ctl = plane_state->color_ctl |
> + glk_plane_color_ctl_crtc(crtc_state);
> +
> + keymax = (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
> +
> + keymsk = key->channel_mask & 0x7ffffff;
> + if (alpha < 0xff)
> + keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
> +
> + if (aux_plane) {
> + aux_dist = skl_surf_address(plane_state, aux_plane) -
> + skl_surf_address(plane_state, color_plane);
> +
> + if (DISPLAY_VER(dev_priv) < 12)
> + aux_dist |= skl_plane_stride(plane_state, aux_plane);
> + }
> +
> + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> +
> intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id),
> key->min_value);
> intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), keymsk);
> @@ -1146,17 +1158,22 @@ skl_program_plane(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
> (y << 16) | x);
Wondering, if we could also move PLANE_OFFSET register to non-arming
section. BSpec states, that it is not arming and being armed by
writing PLANE_SURF. I think we even agreed to check if that was true,
so I made some tests with DG2, I think and writes to PLANE_OFFSET
didn't anyhow affect the hw until PLANE_SURF was written(was checking
it by reading the crcs...)
>
> + intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);
> +
> if (DISPLAY_VER(dev_priv) < 11)
> intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
> (plane_state->view.color_plane[1].y << 16) |
> plane_state->view.color_plane[1].x);
>
> - intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane);
> + if (DISPLAY_VER(dev_priv) >= 10)
> + intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
>
> /*
> * Enable the scaler before the plane so that we don't
> * get a catastrophic underrun even if the two operations
> * end up happening in two different frames.
> + *
> + * TODO: split into noarm+arm pair
> */
> if (plane_state->scaler_id >= 0)
> skl_program_plane_scaler(plane, crtc_state, plane_state);
> @@ -1199,7 +1216,20 @@ skl_plane_async_flip(struct intel_plane *plane,
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
>
> -/* TODO: split into noarm+arm pair */
> +static void
> +skl_plane_update_noarm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> +{
> + int color_plane = 0;
> +
> + if (plane_state->planar_linked_plane && !plane_state->planar_slave)
> + /* Program the UV plane on planar master */
> + color_plane = 1;
> +
> + skl_program_plane_noarm(plane, crtc_state, plane_state, color_plane);
> +}
> +
> static void
> skl_plane_update_arm(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> @@ -1211,7 +1241,7 @@ skl_plane_update_arm(struct intel_plane *plane,
> /* Program the UV plane on planar master */
> color_plane = 1;
>
> - skl_program_plane(plane, crtc_state, plane_state, color_plane);
> + skl_program_plane_arm(plane, crtc_state, plane_state, color_plane);
> }
>
> static bool intel_format_is_p01x(u32 format)
> @@ -2159,6 +2189,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
> }
>
> plane->max_stride = skl_plane_max_stride;
> + plane->update_noarm = skl_plane_update_noarm;
> plane->update_arm = skl_plane_update_arm;
> plane->disable_arm = skl_plane_disable_arm;
> plane->get_hw_state = skl_plane_get_hw_state;
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Intel-gfx] [PATCH 5/9] drm/i915: Split skl+ plane update into noarm+arm pair
2021-10-27 17:11 ` Lisovskiy, Stanislav
@ 2021-10-28 13:03 ` Ville Syrjälä
2021-10-28 13:54 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 38+ messages in thread
From: Ville Syrjälä @ 2021-10-28 13:03 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
On Wed, Oct 27, 2021 at 08:11:37PM +0300, Lisovskiy, Stanislav wrote:
> On Mon, Oct 18, 2021 at 02:50:26PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Chop skl_program_plane() into two halves. Fist half becomes
> > the _noarm() variant, second part the _arm() variant.
> >
> > Fortunately I have already previously grouped the register
> > writes into roughtly the correct order, so the split looks
> > surprisingly clean.
> >
> > A few notable oddities I did not realize were self arming
> > are AUX_DIST and COLOR_CTL.
> >
> > i915_update_info doesn't look too terrible on my cfl running
> > kms_atomic_transition --r plane-all-transition --extended:
> > w/o patch w/ patch
> > Updates: 2178 Updates: 2018
> > | |
> > 1us | 1us |
> > | |
> > 4us | 4us |*****
> > |********* |**********
> > 16us |********** 16us |*******
> > |*** |
> > 66us | 66us |
> > | |
> > 262us | 262us |
> > | |
> > 1ms | 1ms |
> > | |
> > 4ms | 4ms |
> > | |
> > 17ms | 17ms |
> > | |
> > Min update: 8332ns Min update: 6164ns
> > Max update: 48758ns Max update: 31808ns
> > Average update: 19959ns Average update: 13159ns
> > Overruns > 100us: 0 Overruns > 100us: 0
> >
> > And with lockdep enabled:
> > w/o patch w/ patch
> > Updates: 2177 Updates: 2172
> > | |
> > 1us | 1us |
> > | |
> > 4us | 4us |
> > |******* |*********
> > 16us |********** 16us |**********
> > |******* |*
> > 66us | 66us |
> > | |
> > 262us | 262us |
> > | |
> > 1ms | 1ms |
> > | |
> > 4ms | 4ms |
> > | |
> > 17ms | 17ms |
> > | |
> > Min update: 12645ns Min update: 9980ns
> > Max update: 50153ns Max update: 33533ns
> > Average update: 25337ns Average update: 18245ns
> > Overruns > 250us: 0 Overruns > 250us: 0
> >
> > TODO: On icl+ everything seems to be armed by PLANE_SURF, so we
> > can optimize this even further on modern platforms. But I
> > think there's a bit of refactoring to be done first to
> > figure out the best way to go about it (eg. just reusing
> > the current skl+ functions, or doing a lower level split).
> >
> > TODO: Split scaler programming as well, but IIRC the scaler
> > has some oddball double buffering behaviour on some
> > platforms, so needs proper reverse engineering
> >
> > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > .../drm/i915/display/skl_universal_plane.c | 113 +++++++++++-------
> > 1 file changed, 72 insertions(+), 41 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 74f3870d39b1..2a822e1e465e 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -1050,60 +1050,32 @@ static void icl_plane_csc_load_black(struct intel_plane *plane)
> > }
> >
> > static void
> > -skl_program_plane(struct intel_plane *plane,
> > - const struct intel_crtc_state *crtc_state,
> > - const struct intel_plane_state *plane_state,
> > - int color_plane)
> > +skl_program_plane_noarm(struct intel_plane *plane,
> > + const struct intel_crtc_state *crtc_state,
> > + const struct intel_plane_state *plane_state,
> > + int color_plane)
> > {
> > struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > enum plane_id plane_id = plane->id;
> > enum pipe pipe = plane->pipe;
> > - const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> > u32 stride = skl_plane_stride(plane_state, color_plane);
> > const struct drm_framebuffer *fb = plane_state->hw.fb;
> > - int aux_plane = skl_main_to_aux_plane(fb, color_plane);
> > int crtc_x = plane_state->uapi.dst.x1;
> > int crtc_y = plane_state->uapi.dst.y1;
> > - u32 x = plane_state->view.color_plane[color_plane].x;
> > - u32 y = plane_state->view.color_plane[color_plane].y;
> > u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
> > u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
> > - u8 alpha = plane_state->hw.alpha >> 8;
> > - u32 plane_color_ctl = 0, aux_dist = 0;
> > unsigned long irqflags;
> > - u32 keymsk, keymax;
> > - u32 plane_ctl = plane_state->ctl;
> > -
> > - plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> > -
> > - if (DISPLAY_VER(dev_priv) >= 10)
> > - plane_color_ctl = plane_state->color_ctl |
> > - glk_plane_color_ctl_crtc(crtc_state);
> >
> > /* Sizes are 0 based */
> > src_w--;
> > src_h--;
> >
> > - keymax = (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
> > -
> > - keymsk = key->channel_mask & 0x7ffffff;
> > - if (alpha < 0xff)
> > - keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
> > -
> > /* The scaler will handle the output position */
> > if (plane_state->scaler_id >= 0) {
> > crtc_x = 0;
> > crtc_y = 0;
> > }
> >
> > - if (aux_plane) {
> > - aux_dist = skl_surf_address(plane_state, aux_plane) -
> > - skl_surf_address(plane_state, color_plane);
> > -
> > - if (DISPLAY_VER(dev_priv) < 12)
> > - aux_dist |= skl_plane_stride(plane_state, aux_plane);
> > - }
> > -
> > spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> >
> > /*
> > @@ -1119,16 +1091,10 @@ skl_program_plane(struct intel_plane *plane,
> > intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
> > (src_h << 16) | src_w);
> >
> > - intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);
> > -
> > if (icl_is_hdr_plane(dev_priv, plane_id))
> > intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id),
> > plane_state->cus_ctl);
> >
> > - if (DISPLAY_VER(dev_priv) >= 10)
> > - intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id),
> > - plane_color_ctl);
> > -
> > if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
> > icl_program_input_csc(plane, crtc_state, plane_state);
> >
> > @@ -1138,6 +1104,52 @@ skl_program_plane(struct intel_plane *plane,
> >
> > skl_write_plane_wm(plane, crtc_state);
> >
> > + intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane);
> > +
> > + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> > +}
> > +
> > +static void
> > +skl_program_plane_arm(struct intel_plane *plane,
> > + const struct intel_crtc_state *crtc_state,
> > + const struct intel_plane_state *plane_state,
> > + int color_plane)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > + enum plane_id plane_id = plane->id;
> > + enum pipe pipe = plane->pipe;
> > + const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> > + const struct drm_framebuffer *fb = plane_state->hw.fb;
> > + int aux_plane = skl_main_to_aux_plane(fb, color_plane);
> > + u32 x = plane_state->view.color_plane[color_plane].x;
> > + u32 y = plane_state->view.color_plane[color_plane].y;
> > + u32 keymsk, keymax, aux_dist = 0, plane_color_ctl = 0;
> > + u8 alpha = plane_state->hw.alpha >> 8;
> > + u32 plane_ctl = plane_state->ctl;
> > + unsigned long irqflags;
> > +
> > + plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> > +
> > + if (DISPLAY_VER(dev_priv) >= 10)
> > + plane_color_ctl = plane_state->color_ctl |
> > + glk_plane_color_ctl_crtc(crtc_state);
> > +
> > + keymax = (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
> > +
> > + keymsk = key->channel_mask & 0x7ffffff;
> > + if (alpha < 0xff)
> > + keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
> > +
> > + if (aux_plane) {
> > + aux_dist = skl_surf_address(plane_state, aux_plane) -
> > + skl_surf_address(plane_state, color_plane);
> > +
> > + if (DISPLAY_VER(dev_priv) < 12)
> > + aux_dist |= skl_plane_stride(plane_state, aux_plane);
> > + }
> > +
> > + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> > +
> > intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id),
> > key->min_value);
> > intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), keymsk);
> > @@ -1146,17 +1158,22 @@ skl_program_plane(struct intel_plane *plane,
> > intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
> > (y << 16) | x);
>
> Wondering, if we could also move PLANE_OFFSET register to non-arming
> section.
No. It is self arming.
> BSpec states, that it is not arming and being armed by
> writing PLANE_SURF. I think we even agreed to check if that was true,
> so I made some tests with DG2, I think and writes to PLANE_OFFSET
> didn't anyhow affect the hw until PLANE_SURF was written(was checking
> it by reading the crcs...)
Your test was invalid since it was done on icl+ where everything is
armed by PLANE_SURF.
>
> >
> > + intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);
> > +
> > if (DISPLAY_VER(dev_priv) < 11)
> > intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
> > (plane_state->view.color_plane[1].y << 16) |
> > plane_state->view.color_plane[1].x);
> >
> > - intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane);
> > + if (DISPLAY_VER(dev_priv) >= 10)
> > + intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
> >
> > /*
> > * Enable the scaler before the plane so that we don't
> > * get a catastrophic underrun even if the two operations
> > * end up happening in two different frames.
> > + *
> > + * TODO: split into noarm+arm pair
> > */
> > if (plane_state->scaler_id >= 0)
> > skl_program_plane_scaler(plane, crtc_state, plane_state);
> > @@ -1199,7 +1216,20 @@ skl_plane_async_flip(struct intel_plane *plane,
> > spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> > }
> >
> > -/* TODO: split into noarm+arm pair */
> > +static void
> > +skl_plane_update_noarm(struct intel_plane *plane,
> > + const struct intel_crtc_state *crtc_state,
> > + const struct intel_plane_state *plane_state)
> > +{
> > + int color_plane = 0;
> > +
> > + if (plane_state->planar_linked_plane && !plane_state->planar_slave)
> > + /* Program the UV plane on planar master */
> > + color_plane = 1;
> > +
> > + skl_program_plane_noarm(plane, crtc_state, plane_state, color_plane);
> > +}
> > +
> > static void
> > skl_plane_update_arm(struct intel_plane *plane,
> > const struct intel_crtc_state *crtc_state,
> > @@ -1211,7 +1241,7 @@ skl_plane_update_arm(struct intel_plane *plane,
> > /* Program the UV plane on planar master */
> > color_plane = 1;
> >
> > - skl_program_plane(plane, crtc_state, plane_state, color_plane);
> > + skl_program_plane_arm(plane, crtc_state, plane_state, color_plane);
> > }
> >
> > static bool intel_format_is_p01x(u32 format)
> > @@ -2159,6 +2189,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
> > }
> >
> > plane->max_stride = skl_plane_max_stride;
> > + plane->update_noarm = skl_plane_update_noarm;
> > plane->update_arm = skl_plane_update_arm;
> > plane->disable_arm = skl_plane_disable_arm;
> > plane->get_hw_state = skl_plane_get_hw_state;
> > --
> > 2.32.0
> >
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Intel-gfx] [PATCH 5/9] drm/i915: Split skl+ plane update into noarm+arm pair
2021-10-28 13:03 ` Ville Syrjälä
@ 2021-10-28 13:54 ` Lisovskiy, Stanislav
2021-10-28 13:59 ` Ville Syrjälä
0 siblings, 1 reply; 38+ messages in thread
From: Lisovskiy, Stanislav @ 2021-10-28 13:54 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, Oct 28, 2021 at 04:03:32PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 27, 2021 at 08:11:37PM +0300, Lisovskiy, Stanislav wrote:
> > On Mon, Oct 18, 2021 at 02:50:26PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Chop skl_program_plane() into two halves. Fist half becomes
> > > the _noarm() variant, second part the _arm() variant.
> > >
> > > Fortunately I have already previously grouped the register
> > > writes into roughtly the correct order, so the split looks
> > > surprisingly clean.
> > >
> > > A few notable oddities I did not realize were self arming
> > > are AUX_DIST and COLOR_CTL.
> > >
> > > i915_update_info doesn't look too terrible on my cfl running
> > > kms_atomic_transition --r plane-all-transition --extended:
> > > w/o patch w/ patch
> > > Updates: 2178 Updates: 2018
> > > | |
> > > 1us | 1us |
> > > | |
> > > 4us | 4us |*****
> > > |********* |**********
> > > 16us |********** 16us |*******
> > > |*** |
> > > 66us | 66us |
> > > | |
> > > 262us | 262us |
> > > | |
> > > 1ms | 1ms |
> > > | |
> > > 4ms | 4ms |
> > > | |
> > > 17ms | 17ms |
> > > | |
> > > Min update: 8332ns Min update: 6164ns
> > > Max update: 48758ns Max update: 31808ns
> > > Average update: 19959ns Average update: 13159ns
> > > Overruns > 100us: 0 Overruns > 100us: 0
> > >
> > > And with lockdep enabled:
> > > w/o patch w/ patch
> > > Updates: 2177 Updates: 2172
> > > | |
> > > 1us | 1us |
> > > | |
> > > 4us | 4us |
> > > |******* |*********
> > > 16us |********** 16us |**********
> > > |******* |*
> > > 66us | 66us |
> > > | |
> > > 262us | 262us |
> > > | |
> > > 1ms | 1ms |
> > > | |
> > > 4ms | 4ms |
> > > | |
> > > 17ms | 17ms |
> > > | |
> > > Min update: 12645ns Min update: 9980ns
> > > Max update: 50153ns Max update: 33533ns
> > > Average update: 25337ns Average update: 18245ns
> > > Overruns > 250us: 0 Overruns > 250us: 0
> > >
> > > TODO: On icl+ everything seems to be armed by PLANE_SURF, so we
> > > can optimize this even further on modern platforms. But I
> > > think there's a bit of refactoring to be done first to
> > > figure out the best way to go about it (eg. just reusing
> > > the current skl+ functions, or doing a lower level split).
> > >
> > > TODO: Split scaler programming as well, but IIRC the scaler
> > > has some oddball double buffering behaviour on some
> > > platforms, so needs proper reverse engineering
> > >
> > > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > > .../drm/i915/display/skl_universal_plane.c | 113 +++++++++++-------
> > > 1 file changed, 72 insertions(+), 41 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > index 74f3870d39b1..2a822e1e465e 100644
> > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > @@ -1050,60 +1050,32 @@ static void icl_plane_csc_load_black(struct intel_plane *plane)
> > > }
> > >
> > > static void
> > > -skl_program_plane(struct intel_plane *plane,
> > > - const struct intel_crtc_state *crtc_state,
> > > - const struct intel_plane_state *plane_state,
> > > - int color_plane)
> > > +skl_program_plane_noarm(struct intel_plane *plane,
> > > + const struct intel_crtc_state *crtc_state,
> > > + const struct intel_plane_state *plane_state,
> > > + int color_plane)
> > > {
> > > struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > > enum plane_id plane_id = plane->id;
> > > enum pipe pipe = plane->pipe;
> > > - const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> > > u32 stride = skl_plane_stride(plane_state, color_plane);
> > > const struct drm_framebuffer *fb = plane_state->hw.fb;
> > > - int aux_plane = skl_main_to_aux_plane(fb, color_plane);
> > > int crtc_x = plane_state->uapi.dst.x1;
> > > int crtc_y = plane_state->uapi.dst.y1;
> > > - u32 x = plane_state->view.color_plane[color_plane].x;
> > > - u32 y = plane_state->view.color_plane[color_plane].y;
> > > u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
> > > u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
> > > - u8 alpha = plane_state->hw.alpha >> 8;
> > > - u32 plane_color_ctl = 0, aux_dist = 0;
> > > unsigned long irqflags;
> > > - u32 keymsk, keymax;
> > > - u32 plane_ctl = plane_state->ctl;
> > > -
> > > - plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> > > -
> > > - if (DISPLAY_VER(dev_priv) >= 10)
> > > - plane_color_ctl = plane_state->color_ctl |
> > > - glk_plane_color_ctl_crtc(crtc_state);
> > >
> > > /* Sizes are 0 based */
> > > src_w--;
> > > src_h--;
> > >
> > > - keymax = (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
> > > -
> > > - keymsk = key->channel_mask & 0x7ffffff;
> > > - if (alpha < 0xff)
> > > - keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
> > > -
> > > /* The scaler will handle the output position */
> > > if (plane_state->scaler_id >= 0) {
> > > crtc_x = 0;
> > > crtc_y = 0;
> > > }
> > >
> > > - if (aux_plane) {
> > > - aux_dist = skl_surf_address(plane_state, aux_plane) -
> > > - skl_surf_address(plane_state, color_plane);
> > > -
> > > - if (DISPLAY_VER(dev_priv) < 12)
> > > - aux_dist |= skl_plane_stride(plane_state, aux_plane);
> > > - }
> > > -
> > > spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> > >
> > > /*
> > > @@ -1119,16 +1091,10 @@ skl_program_plane(struct intel_plane *plane,
> > > intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
> > > (src_h << 16) | src_w);
> > >
> > > - intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);
> > > -
> > > if (icl_is_hdr_plane(dev_priv, plane_id))
> > > intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id),
> > > plane_state->cus_ctl);
> > >
> > > - if (DISPLAY_VER(dev_priv) >= 10)
> > > - intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id),
> > > - plane_color_ctl);
> > > -
> > > if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
> > > icl_program_input_csc(plane, crtc_state, plane_state);
> > >
> > > @@ -1138,6 +1104,52 @@ skl_program_plane(struct intel_plane *plane,
> > >
> > > skl_write_plane_wm(plane, crtc_state);
> > >
> > > + intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane);
> > > +
> > > + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> > > +}
> > > +
> > > +static void
> > > +skl_program_plane_arm(struct intel_plane *plane,
> > > + const struct intel_crtc_state *crtc_state,
> > > + const struct intel_plane_state *plane_state,
> > > + int color_plane)
> > > +{
> > > + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > > + enum plane_id plane_id = plane->id;
> > > + enum pipe pipe = plane->pipe;
> > > + const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> > > + const struct drm_framebuffer *fb = plane_state->hw.fb;
> > > + int aux_plane = skl_main_to_aux_plane(fb, color_plane);
> > > + u32 x = plane_state->view.color_plane[color_plane].x;
> > > + u32 y = plane_state->view.color_plane[color_plane].y;
> > > + u32 keymsk, keymax, aux_dist = 0, plane_color_ctl = 0;
> > > + u8 alpha = plane_state->hw.alpha >> 8;
> > > + u32 plane_ctl = plane_state->ctl;
> > > + unsigned long irqflags;
> > > +
> > > + plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> > > +
> > > + if (DISPLAY_VER(dev_priv) >= 10)
> > > + plane_color_ctl = plane_state->color_ctl |
> > > + glk_plane_color_ctl_crtc(crtc_state);
> > > +
> > > + keymax = (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
> > > +
> > > + keymsk = key->channel_mask & 0x7ffffff;
> > > + if (alpha < 0xff)
> > > + keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
> > > +
> > > + if (aux_plane) {
> > > + aux_dist = skl_surf_address(plane_state, aux_plane) -
> > > + skl_surf_address(plane_state, color_plane);
> > > +
> > > + if (DISPLAY_VER(dev_priv) < 12)
> > > + aux_dist |= skl_plane_stride(plane_state, aux_plane);
> > > + }
> > > +
> > > + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> > > +
> > > intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id),
> > > key->min_value);
> > > intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), keymsk);
> > > @@ -1146,17 +1158,22 @@ skl_program_plane(struct intel_plane *plane,
> > > intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
> > > (y << 16) | x);
> >
> > Wondering, if we could also move PLANE_OFFSET register to non-arming
> > section.
>
> No. It is self arming.
>
> > BSpec states, that it is not arming and being armed by
> > writing PLANE_SURF. I think we even agreed to check if that was true,
> > so I made some tests with DG2, I think and writes to PLANE_OFFSET
> > didn't anyhow affect the hw until PLANE_SURF was written(was checking
> > it by reading the crcs...)
>
> Your test was invalid since it was done on icl+ where everything is
> armed by PLANE_SURF.
Well, at that moment the main question was about DG2/ADL, so I tested
it with that particular platform(we had atomic update issues mostly there)
Also I guess it means PLANE_OFFSET can be moved to non-arming section
for icl+ at least.
Or was it done somewhere later in your series?
Didn't walk through all of the patches yet.
>
> >
> > >
> > > + intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);
> > > +
> > > if (DISPLAY_VER(dev_priv) < 11)
> > > intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
> > > (plane_state->view.color_plane[1].y << 16) |
> > > plane_state->view.color_plane[1].x);
> > >
> > > - intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane);
> > > + if (DISPLAY_VER(dev_priv) >= 10)
> > > + intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
> > >
> > > /*
> > > * Enable the scaler before the plane so that we don't
> > > * get a catastrophic underrun even if the two operations
> > > * end up happening in two different frames.
> > > + *
> > > + * TODO: split into noarm+arm pair
> > > */
> > > if (plane_state->scaler_id >= 0)
> > > skl_program_plane_scaler(plane, crtc_state, plane_state);
> > > @@ -1199,7 +1216,20 @@ skl_plane_async_flip(struct intel_plane *plane,
> > > spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> > > }
> > >
> > > -/* TODO: split into noarm+arm pair */
> > > +static void
> > > +skl_plane_update_noarm(struct intel_plane *plane,
> > > + const struct intel_crtc_state *crtc_state,
> > > + const struct intel_plane_state *plane_state)
> > > +{
> > > + int color_plane = 0;
> > > +
> > > + if (plane_state->planar_linked_plane && !plane_state->planar_slave)
> > > + /* Program the UV plane on planar master */
> > > + color_plane = 1;
> > > +
> > > + skl_program_plane_noarm(plane, crtc_state, plane_state, color_plane);
> > > +}
> > > +
> > > static void
> > > skl_plane_update_arm(struct intel_plane *plane,
> > > const struct intel_crtc_state *crtc_state,
> > > @@ -1211,7 +1241,7 @@ skl_plane_update_arm(struct intel_plane *plane,
> > > /* Program the UV plane on planar master */
> > > color_plane = 1;
> > >
> > > - skl_program_plane(plane, crtc_state, plane_state, color_plane);
> > > + skl_program_plane_arm(plane, crtc_state, plane_state, color_plane);
> > > }
> > >
> > > static bool intel_format_is_p01x(u32 format)
> > > @@ -2159,6 +2189,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
> > > }
> > >
> > > plane->max_stride = skl_plane_max_stride;
> > > + plane->update_noarm = skl_plane_update_noarm;
> > > plane->update_arm = skl_plane_update_arm;
> > > plane->disable_arm = skl_plane_disable_arm;
> > > plane->get_hw_state = skl_plane_get_hw_state;
> > > --
> > > 2.32.0
> > >
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Intel-gfx] [PATCH 5/9] drm/i915: Split skl+ plane update into noarm+arm pair
2021-10-28 13:54 ` Lisovskiy, Stanislav
@ 2021-10-28 13:59 ` Ville Syrjälä
2021-10-28 14:05 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 38+ messages in thread
From: Ville Syrjälä @ 2021-10-28 13:59 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
On Thu, Oct 28, 2021 at 04:54:19PM +0300, Lisovskiy, Stanislav wrote:
> On Thu, Oct 28, 2021 at 04:03:32PM +0300, Ville Syrjälä wrote:
> > On Wed, Oct 27, 2021 at 08:11:37PM +0300, Lisovskiy, Stanislav wrote:
> > > On Mon, Oct 18, 2021 at 02:50:26PM +0300, Ville Syrjala wrote:
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > >
> > > > Chop skl_program_plane() into two halves. Fist half becomes
> > > > the _noarm() variant, second part the _arm() variant.
> > > >
> > > > Fortunately I have already previously grouped the register
> > > > writes into roughtly the correct order, so the split looks
> > > > surprisingly clean.
> > > >
> > > > A few notable oddities I did not realize were self arming
> > > > are AUX_DIST and COLOR_CTL.
> > > >
> > > > i915_update_info doesn't look too terrible on my cfl running
> > > > kms_atomic_transition --r plane-all-transition --extended:
> > > > w/o patch w/ patch
> > > > Updates: 2178 Updates: 2018
> > > > | |
> > > > 1us | 1us |
> > > > | |
> > > > 4us | 4us |*****
> > > > |********* |**********
> > > > 16us |********** 16us |*******
> > > > |*** |
> > > > 66us | 66us |
> > > > | |
> > > > 262us | 262us |
> > > > | |
> > > > 1ms | 1ms |
> > > > | |
> > > > 4ms | 4ms |
> > > > | |
> > > > 17ms | 17ms |
> > > > | |
> > > > Min update: 8332ns Min update: 6164ns
> > > > Max update: 48758ns Max update: 31808ns
> > > > Average update: 19959ns Average update: 13159ns
> > > > Overruns > 100us: 0 Overruns > 100us: 0
> > > >
> > > > And with lockdep enabled:
> > > > w/o patch w/ patch
> > > > Updates: 2177 Updates: 2172
> > > > | |
> > > > 1us | 1us |
> > > > | |
> > > > 4us | 4us |
> > > > |******* |*********
> > > > 16us |********** 16us |**********
> > > > |******* |*
> > > > 66us | 66us |
> > > > | |
> > > > 262us | 262us |
> > > > | |
> > > > 1ms | 1ms |
> > > > | |
> > > > 4ms | 4ms |
> > > > | |
> > > > 17ms | 17ms |
> > > > | |
> > > > Min update: 12645ns Min update: 9980ns
> > > > Max update: 50153ns Max update: 33533ns
> > > > Average update: 25337ns Average update: 18245ns
> > > > Overruns > 250us: 0 Overruns > 250us: 0
> > > >
> > > > TODO: On icl+ everything seems to be armed by PLANE_SURF, so we
> > > > can optimize this even further on modern platforms. But I
> > > > think there's a bit of refactoring to be done first to
> > > > figure out the best way to go about it (eg. just reusing
> > > > the current skl+ functions, or doing a lower level split).
> > > >
> > > > TODO: Split scaler programming as well, but IIRC the scaler
> > > > has some oddball double buffering behaviour on some
> > > > platforms, so needs proper reverse engineering
> > > >
> > > > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > ---
> > > > .../drm/i915/display/skl_universal_plane.c | 113 +++++++++++-------
> > > > 1 file changed, 72 insertions(+), 41 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > index 74f3870d39b1..2a822e1e465e 100644
> > > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > @@ -1050,60 +1050,32 @@ static void icl_plane_csc_load_black(struct intel_plane *plane)
> > > > }
> > > >
> > > > static void
> > > > -skl_program_plane(struct intel_plane *plane,
> > > > - const struct intel_crtc_state *crtc_state,
> > > > - const struct intel_plane_state *plane_state,
> > > > - int color_plane)
> > > > +skl_program_plane_noarm(struct intel_plane *plane,
> > > > + const struct intel_crtc_state *crtc_state,
> > > > + const struct intel_plane_state *plane_state,
> > > > + int color_plane)
> > > > {
> > > > struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > > > enum plane_id plane_id = plane->id;
> > > > enum pipe pipe = plane->pipe;
> > > > - const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> > > > u32 stride = skl_plane_stride(plane_state, color_plane);
> > > > const struct drm_framebuffer *fb = plane_state->hw.fb;
> > > > - int aux_plane = skl_main_to_aux_plane(fb, color_plane);
> > > > int crtc_x = plane_state->uapi.dst.x1;
> > > > int crtc_y = plane_state->uapi.dst.y1;
> > > > - u32 x = plane_state->view.color_plane[color_plane].x;
> > > > - u32 y = plane_state->view.color_plane[color_plane].y;
> > > > u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
> > > > u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
> > > > - u8 alpha = plane_state->hw.alpha >> 8;
> > > > - u32 plane_color_ctl = 0, aux_dist = 0;
> > > > unsigned long irqflags;
> > > > - u32 keymsk, keymax;
> > > > - u32 plane_ctl = plane_state->ctl;
> > > > -
> > > > - plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> > > > -
> > > > - if (DISPLAY_VER(dev_priv) >= 10)
> > > > - plane_color_ctl = plane_state->color_ctl |
> > > > - glk_plane_color_ctl_crtc(crtc_state);
> > > >
> > > > /* Sizes are 0 based */
> > > > src_w--;
> > > > src_h--;
> > > >
> > > > - keymax = (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
> > > > -
> > > > - keymsk = key->channel_mask & 0x7ffffff;
> > > > - if (alpha < 0xff)
> > > > - keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
> > > > -
> > > > /* The scaler will handle the output position */
> > > > if (plane_state->scaler_id >= 0) {
> > > > crtc_x = 0;
> > > > crtc_y = 0;
> > > > }
> > > >
> > > > - if (aux_plane) {
> > > > - aux_dist = skl_surf_address(plane_state, aux_plane) -
> > > > - skl_surf_address(plane_state, color_plane);
> > > > -
> > > > - if (DISPLAY_VER(dev_priv) < 12)
> > > > - aux_dist |= skl_plane_stride(plane_state, aux_plane);
> > > > - }
> > > > -
> > > > spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> > > >
> > > > /*
> > > > @@ -1119,16 +1091,10 @@ skl_program_plane(struct intel_plane *plane,
> > > > intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
> > > > (src_h << 16) | src_w);
> > > >
> > > > - intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);
> > > > -
> > > > if (icl_is_hdr_plane(dev_priv, plane_id))
> > > > intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id),
> > > > plane_state->cus_ctl);
> > > >
> > > > - if (DISPLAY_VER(dev_priv) >= 10)
> > > > - intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id),
> > > > - plane_color_ctl);
> > > > -
> > > > if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
> > > > icl_program_input_csc(plane, crtc_state, plane_state);
> > > >
> > > > @@ -1138,6 +1104,52 @@ skl_program_plane(struct intel_plane *plane,
> > > >
> > > > skl_write_plane_wm(plane, crtc_state);
> > > >
> > > > + intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane);
> > > > +
> > > > + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> > > > +}
> > > > +
> > > > +static void
> > > > +skl_program_plane_arm(struct intel_plane *plane,
> > > > + const struct intel_crtc_state *crtc_state,
> > > > + const struct intel_plane_state *plane_state,
> > > > + int color_plane)
> > > > +{
> > > > + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > > > + enum plane_id plane_id = plane->id;
> > > > + enum pipe pipe = plane->pipe;
> > > > + const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> > > > + const struct drm_framebuffer *fb = plane_state->hw.fb;
> > > > + int aux_plane = skl_main_to_aux_plane(fb, color_plane);
> > > > + u32 x = plane_state->view.color_plane[color_plane].x;
> > > > + u32 y = plane_state->view.color_plane[color_plane].y;
> > > > + u32 keymsk, keymax, aux_dist = 0, plane_color_ctl = 0;
> > > > + u8 alpha = plane_state->hw.alpha >> 8;
> > > > + u32 plane_ctl = plane_state->ctl;
> > > > + unsigned long irqflags;
> > > > +
> > > > + plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> > > > +
> > > > + if (DISPLAY_VER(dev_priv) >= 10)
> > > > + plane_color_ctl = plane_state->color_ctl |
> > > > + glk_plane_color_ctl_crtc(crtc_state);
> > > > +
> > > > + keymax = (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
> > > > +
> > > > + keymsk = key->channel_mask & 0x7ffffff;
> > > > + if (alpha < 0xff)
> > > > + keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
> > > > +
> > > > + if (aux_plane) {
> > > > + aux_dist = skl_surf_address(plane_state, aux_plane) -
> > > > + skl_surf_address(plane_state, color_plane);
> > > > +
> > > > + if (DISPLAY_VER(dev_priv) < 12)
> > > > + aux_dist |= skl_plane_stride(plane_state, aux_plane);
> > > > + }
> > > > +
> > > > + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> > > > +
> > > > intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id),
> > > > key->min_value);
> > > > intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), keymsk);
> > > > @@ -1146,17 +1158,22 @@ skl_program_plane(struct intel_plane *plane,
> > > > intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
> > > > (y << 16) | x);
> > >
> > > Wondering, if we could also move PLANE_OFFSET register to non-arming
> > > section.
> >
> > No. It is self arming.
> >
> > > BSpec states, that it is not arming and being armed by
> > > writing PLANE_SURF. I think we even agreed to check if that was true,
> > > so I made some tests with DG2, I think and writes to PLANE_OFFSET
> > > didn't anyhow affect the hw until PLANE_SURF was written(was checking
> > > it by reading the crcs...)
> >
> > Your test was invalid since it was done on icl+ where everything is
> > armed by PLANE_SURF.
>
> Well, at that moment the main question was about DG2/ADL, so I tested
> it with that particular platform(we had atomic update issues mostly there)
>
> Also I guess it means PLANE_OFFSET can be moved to non-arming section
> for icl+ at least.
>
> Or was it done somewhere later in your series?
> Didn't walk through all of the patches yet.
Quoting from the commit message of this very patch:
"TODO: On icl+ everything seems to be armed by PLANE_SURF, so we
can optimize this even further on modern platforms. But I
think there's a bit of refactoring to be done first to
figure out the best way to go about it (eg. just reusing
the current skl+ functions, or doing a lower level split). "
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Intel-gfx] [PATCH 5/9] drm/i915: Split skl+ plane update into noarm+arm pair
2021-10-28 13:59 ` Ville Syrjälä
@ 2021-10-28 14:05 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 38+ messages in thread
From: Lisovskiy, Stanislav @ 2021-10-28 14:05 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, Oct 28, 2021 at 04:59:28PM +0300, Ville Syrjälä wrote:
> On Thu, Oct 28, 2021 at 04:54:19PM +0300, Lisovskiy, Stanislav wrote:
> > On Thu, Oct 28, 2021 at 04:03:32PM +0300, Ville Syrjälä wrote:
> > > On Wed, Oct 27, 2021 at 08:11:37PM +0300, Lisovskiy, Stanislav wrote:
> > > > On Mon, Oct 18, 2021 at 02:50:26PM +0300, Ville Syrjala wrote:
> > > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > >
> > > > > Chop skl_program_plane() into two halves. Fist half becomes
> > > > > the _noarm() variant, second part the _arm() variant.
> > > > >
> > > > > Fortunately I have already previously grouped the register
> > > > > writes into roughtly the correct order, so the split looks
> > > > > surprisingly clean.
> > > > >
> > > > > A few notable oddities I did not realize were self arming
> > > > > are AUX_DIST and COLOR_CTL.
> > > > >
> > > > > i915_update_info doesn't look too terrible on my cfl running
> > > > > kms_atomic_transition --r plane-all-transition --extended:
> > > > > w/o patch w/ patch
> > > > > Updates: 2178 Updates: 2018
> > > > > | |
> > > > > 1us | 1us |
> > > > > | |
> > > > > 4us | 4us |*****
> > > > > |********* |**********
> > > > > 16us |********** 16us |*******
> > > > > |*** |
> > > > > 66us | 66us |
> > > > > | |
> > > > > 262us | 262us |
> > > > > | |
> > > > > 1ms | 1ms |
> > > > > | |
> > > > > 4ms | 4ms |
> > > > > | |
> > > > > 17ms | 17ms |
> > > > > | |
> > > > > Min update: 8332ns Min update: 6164ns
> > > > > Max update: 48758ns Max update: 31808ns
> > > > > Average update: 19959ns Average update: 13159ns
> > > > > Overruns > 100us: 0 Overruns > 100us: 0
> > > > >
> > > > > And with lockdep enabled:
> > > > > w/o patch w/ patch
> > > > > Updates: 2177 Updates: 2172
> > > > > | |
> > > > > 1us | 1us |
> > > > > | |
> > > > > 4us | 4us |
> > > > > |******* |*********
> > > > > 16us |********** 16us |**********
> > > > > |******* |*
> > > > > 66us | 66us |
> > > > > | |
> > > > > 262us | 262us |
> > > > > | |
> > > > > 1ms | 1ms |
> > > > > | |
> > > > > 4ms | 4ms |
> > > > > | |
> > > > > 17ms | 17ms |
> > > > > | |
> > > > > Min update: 12645ns Min update: 9980ns
> > > > > Max update: 50153ns Max update: 33533ns
> > > > > Average update: 25337ns Average update: 18245ns
> > > > > Overruns > 250us: 0 Overruns > 250us: 0
> > > > >
> > > > > TODO: On icl+ everything seems to be armed by PLANE_SURF, so we
> > > > > can optimize this even further on modern platforms. But I
> > > > > think there's a bit of refactoring to be done first to
> > > > > figure out the best way to go about it (eg. just reusing
> > > > > the current skl+ functions, or doing a lower level split).
> > > > >
> > > > > TODO: Split scaler programming as well, but IIRC the scaler
> > > > > has some oddball double buffering behaviour on some
> > > > > platforms, so needs proper reverse engineering
> > > > >
> > > > > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > ---
> > > > > .../drm/i915/display/skl_universal_plane.c | 113 +++++++++++-------
> > > > > 1 file changed, 72 insertions(+), 41 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > index 74f3870d39b1..2a822e1e465e 100644
> > > > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > @@ -1050,60 +1050,32 @@ static void icl_plane_csc_load_black(struct intel_plane *plane)
> > > > > }
> > > > >
> > > > > static void
> > > > > -skl_program_plane(struct intel_plane *plane,
> > > > > - const struct intel_crtc_state *crtc_state,
> > > > > - const struct intel_plane_state *plane_state,
> > > > > - int color_plane)
> > > > > +skl_program_plane_noarm(struct intel_plane *plane,
> > > > > + const struct intel_crtc_state *crtc_state,
> > > > > + const struct intel_plane_state *plane_state,
> > > > > + int color_plane)
> > > > > {
> > > > > struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > > > > enum plane_id plane_id = plane->id;
> > > > > enum pipe pipe = plane->pipe;
> > > > > - const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> > > > > u32 stride = skl_plane_stride(plane_state, color_plane);
> > > > > const struct drm_framebuffer *fb = plane_state->hw.fb;
> > > > > - int aux_plane = skl_main_to_aux_plane(fb, color_plane);
> > > > > int crtc_x = plane_state->uapi.dst.x1;
> > > > > int crtc_y = plane_state->uapi.dst.y1;
> > > > > - u32 x = plane_state->view.color_plane[color_plane].x;
> > > > > - u32 y = plane_state->view.color_plane[color_plane].y;
> > > > > u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
> > > > > u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
> > > > > - u8 alpha = plane_state->hw.alpha >> 8;
> > > > > - u32 plane_color_ctl = 0, aux_dist = 0;
> > > > > unsigned long irqflags;
> > > > > - u32 keymsk, keymax;
> > > > > - u32 plane_ctl = plane_state->ctl;
> > > > > -
> > > > > - plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> > > > > -
> > > > > - if (DISPLAY_VER(dev_priv) >= 10)
> > > > > - plane_color_ctl = plane_state->color_ctl |
> > > > > - glk_plane_color_ctl_crtc(crtc_state);
> > > > >
> > > > > /* Sizes are 0 based */
> > > > > src_w--;
> > > > > src_h--;
> > > > >
> > > > > - keymax = (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
> > > > > -
> > > > > - keymsk = key->channel_mask & 0x7ffffff;
> > > > > - if (alpha < 0xff)
> > > > > - keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
> > > > > -
> > > > > /* The scaler will handle the output position */
> > > > > if (plane_state->scaler_id >= 0) {
> > > > > crtc_x = 0;
> > > > > crtc_y = 0;
> > > > > }
> > > > >
> > > > > - if (aux_plane) {
> > > > > - aux_dist = skl_surf_address(plane_state, aux_plane) -
> > > > > - skl_surf_address(plane_state, color_plane);
> > > > > -
> > > > > - if (DISPLAY_VER(dev_priv) < 12)
> > > > > - aux_dist |= skl_plane_stride(plane_state, aux_plane);
> > > > > - }
> > > > > -
> > > > > spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> > > > >
> > > > > /*
> > > > > @@ -1119,16 +1091,10 @@ skl_program_plane(struct intel_plane *plane,
> > > > > intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
> > > > > (src_h << 16) | src_w);
> > > > >
> > > > > - intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);
> > > > > -
> > > > > if (icl_is_hdr_plane(dev_priv, plane_id))
> > > > > intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id),
> > > > > plane_state->cus_ctl);
> > > > >
> > > > > - if (DISPLAY_VER(dev_priv) >= 10)
> > > > > - intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id),
> > > > > - plane_color_ctl);
> > > > > -
> > > > > if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
> > > > > icl_program_input_csc(plane, crtc_state, plane_state);
> > > > >
> > > > > @@ -1138,6 +1104,52 @@ skl_program_plane(struct intel_plane *plane,
> > > > >
> > > > > skl_write_plane_wm(plane, crtc_state);
> > > > >
> > > > > + intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane);
> > > > > +
> > > > > + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> > > > > +}
> > > > > +
> > > > > +static void
> > > > > +skl_program_plane_arm(struct intel_plane *plane,
> > > > > + const struct intel_crtc_state *crtc_state,
> > > > > + const struct intel_plane_state *plane_state,
> > > > > + int color_plane)
> > > > > +{
> > > > > + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > > > > + enum plane_id plane_id = plane->id;
> > > > > + enum pipe pipe = plane->pipe;
> > > > > + const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> > > > > + const struct drm_framebuffer *fb = plane_state->hw.fb;
> > > > > + int aux_plane = skl_main_to_aux_plane(fb, color_plane);
> > > > > + u32 x = plane_state->view.color_plane[color_plane].x;
> > > > > + u32 y = plane_state->view.color_plane[color_plane].y;
> > > > > + u32 keymsk, keymax, aux_dist = 0, plane_color_ctl = 0;
> > > > > + u8 alpha = plane_state->hw.alpha >> 8;
> > > > > + u32 plane_ctl = plane_state->ctl;
> > > > > + unsigned long irqflags;
> > > > > +
> > > > > + plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> > > > > +
> > > > > + if (DISPLAY_VER(dev_priv) >= 10)
> > > > > + plane_color_ctl = plane_state->color_ctl |
> > > > > + glk_plane_color_ctl_crtc(crtc_state);
> > > > > +
> > > > > + keymax = (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
> > > > > +
> > > > > + keymsk = key->channel_mask & 0x7ffffff;
> > > > > + if (alpha < 0xff)
> > > > > + keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
> > > > > +
> > > > > + if (aux_plane) {
> > > > > + aux_dist = skl_surf_address(plane_state, aux_plane) -
> > > > > + skl_surf_address(plane_state, color_plane);
> > > > > +
> > > > > + if (DISPLAY_VER(dev_priv) < 12)
> > > > > + aux_dist |= skl_plane_stride(plane_state, aux_plane);
> > > > > + }
> > > > > +
> > > > > + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> > > > > +
> > > > > intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id),
> > > > > key->min_value);
> > > > > intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), keymsk);
> > > > > @@ -1146,17 +1158,22 @@ skl_program_plane(struct intel_plane *plane,
> > > > > intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
> > > > > (y << 16) | x);
> > > >
> > > > Wondering, if we could also move PLANE_OFFSET register to non-arming
> > > > section.
> > >
> > > No. It is self arming.
> > >
> > > > BSpec states, that it is not arming and being armed by
> > > > writing PLANE_SURF. I think we even agreed to check if that was true,
> > > > so I made some tests with DG2, I think and writes to PLANE_OFFSET
> > > > didn't anyhow affect the hw until PLANE_SURF was written(was checking
> > > > it by reading the crcs...)
> > >
> > > Your test was invalid since it was done on icl+ where everything is
> > > armed by PLANE_SURF.
> >
> > Well, at that moment the main question was about DG2/ADL, so I tested
> > it with that particular platform(we had atomic update issues mostly there)
> >
> > Also I guess it means PLANE_OFFSET can be moved to non-arming section
> > for icl+ at least.
> >
> > Or was it done somewhere later in your series?
> > Didn't walk through all of the patches yet.
>
> Quoting from the commit message of this very patch:
> "TODO: On icl+ everything seems to be armed by PLANE_SURF, so we
> can optimize this even further on modern platforms. But I
> think there's a bit of refactoring to be done first to
> figure out the best way to go about it (eg. just reusing
> the current skl+ functions, or doing a lower level split). "
Sorry, missed that part, as it was after the timing info in the long commit
text :)
I think thats where the most of what we gain
from this optimizarion will be on icl+
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Intel-gfx] [PATCH 2/9] drm/i915: Fix async flip with decryption and/or DPT
2021-10-18 11:50 ` [Intel-gfx] [PATCH 2/9] drm/i915: Fix async flip with decryption and/or DPT Ville Syrjala
@ 2021-11-03 18:39 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 38+ messages in thread
From: Lisovskiy, Stanislav @ 2021-11-03 18:39 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Mon, Oct 18, 2021 at 02:50:23PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We're currently forgetting to set the PLANE_SURF_DECRYPT
> flag in the async flip path. So if the hardware were to
> latch that bit despite this being an async flip we'd start
> scanning out garbage. And if it doesn't latch it then I
> guess we'd just end up with a weird register value that
> doesn't actually match the hardware state, which isn't
> great for anyone starting at register dumps.
>
> Similarly the async flip path also forgets to call
> skl_surf_address() which means the DPT address space to
> GGTT address space downshift is not being applied to
> the offset. Which means we are pointing PLANE_SURF
> at some random location in GGTT instead of the correct
> DPT page.
>
> So let's fix two birds with one stone and extract the
> PLANE_SURF calculation from skl_program_plane() into
> a small helper and use it in the async flip path as well.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Juston Li <juston.li@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Uma Shankar <uma.shankar@intel.com>
> Cc: Karthik B S <karthik.b.s@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> .../drm/i915/display/skl_universal_plane.c | 30 ++++++++++++-------
> 1 file changed, 20 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 7444b88829ea..e2f024449149 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -1011,6 +1011,20 @@ static u32 skl_surf_address(const struct intel_plane_state *plane_state,
> }
> }
>
> +static u32 skl_plane_surf(const struct intel_plane_state *plane_state,
> + int color_plane)
> +{
> + u32 plane_surf;
> +
> + plane_surf = intel_plane_ggtt_offset(plane_state) +
> + skl_surf_address(plane_state, color_plane);
> +
> + if (plane_state->decrypt)
> + plane_surf |= PLANE_SURF_DECRYPT;
> +
> + return plane_surf;
> +}
> +
> static void icl_plane_csc_load_black(struct intel_plane *plane)
> {
> struct drm_i915_private *i915 = to_i915(plane->base.dev);
> @@ -1045,7 +1059,6 @@ skl_program_plane(struct intel_plane *plane,
> enum plane_id plane_id = plane->id;
> enum pipe pipe = plane->pipe;
> const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> - u32 surf_addr = skl_surf_address(plane_state, color_plane);
> u32 stride = skl_plane_stride(plane_state, color_plane);
> const struct drm_framebuffer *fb = plane_state->hw.fb;
> int aux_plane = skl_main_to_aux_plane(fb, color_plane);
> @@ -1058,7 +1071,7 @@ skl_program_plane(struct intel_plane *plane,
> u8 alpha = plane_state->hw.alpha >> 8;
> u32 plane_color_ctl = 0, aux_dist = 0;
> unsigned long irqflags;
> - u32 keymsk, keymax, plane_surf;
> + u32 keymsk, keymax;
> u32 plane_ctl = plane_state->ctl;
>
> plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> @@ -1084,16 +1097,13 @@ skl_program_plane(struct intel_plane *plane,
> }
>
> if (aux_plane) {
> - aux_dist = skl_surf_address(plane_state, aux_plane) - surf_addr;
> + aux_dist = skl_surf_address(plane_state, aux_plane) -
> + skl_surf_address(plane_state, color_plane);
>
> if (DISPLAY_VER(dev_priv) < 12)
> aux_dist |= skl_plane_stride(plane_state, aux_plane);
> }
>
> - plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
> - if (plane_state->decrypt)
> - plane_surf |= PLANE_SURF_DECRYPT;
> -
> spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>
> /*
> @@ -1157,7 +1167,8 @@ skl_program_plane(struct intel_plane *plane,
> * the control register just before the surface register.
> */
> intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
> + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> + skl_plane_surf(plane_state, color_plane));
>
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
> @@ -1172,7 +1183,6 @@ skl_plane_async_flip(struct intel_plane *plane,
> unsigned long irqflags;
> enum plane_id plane_id = plane->id;
> enum pipe pipe = plane->pipe;
> - u32 surf_addr = plane_state->view.color_plane[0].offset;
> u32 plane_ctl = plane_state->ctl;
>
> plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> @@ -1184,7 +1194,7 @@ skl_plane_async_flip(struct intel_plane *plane,
>
> intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> - intel_plane_ggtt_offset(plane_state) + surf_addr);
> + skl_plane_surf(plane_state, 0));
>
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Intel-gfx] [PATCH 9/9] drm/i915: Split vlv/chv sprite plane update into noarm+arm pair
2021-10-18 11:50 ` [Intel-gfx] [PATCH 9/9] drm/i915: Split vlv/chv " Ville Syrjala
@ 2021-11-03 18:44 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 38+ messages in thread
From: Lisovskiy, Stanislav @ 2021-11-03 18:44 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Mon, Oct 18, 2021 at 02:50:30PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Chop vlv_sprite_update() into two halves. Fist half becomes
> the _noarm() variant, second part the _arm() variant.
>
> Fortunately I have already previously grouped the register
> writes into roughtly the correct order, so the split looks
> surprisingly clean.
>
> Looks like most of the hardware logic wa scopied from the
> pre-ctg sprite C, so SPSTRIDE/POS/SIZE are armed by SPSURF,
> while the rest are self arming. SPCONSTALPHA is the one
> entirely new register that didn't exist in the old sprite C,
> and looks like that one is self arming. The CHV pipe B CSC
> is also self arming, like the rest of the CHV pipe B
> additions.
>
> I didn't have time to capture i915_update_info numbers for
> these, but since all the other platforms generally showed
> improvements, and crucially no regression, I am fairly
> confident this should behave similarly.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 45 ++++++++++++++-------
> 1 file changed, 30 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 4e5f95aebeca..fc6ecb41a40e 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -416,35 +416,24 @@ static void vlv_sprite_update_gamma(const struct intel_plane_state *plane_state)
> gamma[i] << 16 | gamma[i] << 8 | gamma[i]);
> }
>
> -/* TODO: split into noarm+arm pair */
> static void
> -vlv_sprite_update_arm(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state)
> +vlv_sprite_update_noarm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
> enum plane_id plane_id = plane->id;
> - u32 sprsurf_offset = plane_state->view.color_plane[0].offset;
> - u32 linear_offset;
> - const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> int crtc_x = plane_state->uapi.dst.x1;
> int crtc_y = plane_state->uapi.dst.y1;
> u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
> u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
> - u32 x = plane_state->view.color_plane[0].x;
> - u32 y = plane_state->view.color_plane[0].y;
> unsigned long irqflags;
> - u32 sprctl;
> -
> - sprctl = plane_state->ctl | vlv_sprite_ctl_crtc(crtc_state);
>
> /* Sizes are 0 based */
> crtc_w--;
> crtc_h--;
>
> - linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
> -
> spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>
> intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id),
> @@ -453,7 +442,30 @@ vlv_sprite_update_arm(struct intel_plane *plane,
> (crtc_y << 16) | crtc_x);
> intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id),
> (crtc_h << 16) | crtc_w);
> - intel_de_write_fw(dev_priv, SPCONSTALPHA(pipe, plane_id), 0);
> +
> + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> +}
> +
> +static void
> +vlv_sprite_update_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + enum pipe pipe = plane->pipe;
> + enum plane_id plane_id = plane->id;
> + const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> + u32 sprsurf_offset = plane_state->view.color_plane[0].offset;
> + u32 x = plane_state->view.color_plane[0].x;
> + u32 y = plane_state->view.color_plane[0].y;
> + u32 sprctl, linear_offset;
> + unsigned long irqflags;
> +
> + sprctl = plane_state->ctl | vlv_sprite_ctl_crtc(crtc_state);
> +
> + linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
> +
> + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>
> if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
> chv_sprite_update_csc(plane_state);
> @@ -467,6 +479,8 @@ vlv_sprite_update_arm(struct intel_plane *plane,
> key->max_value);
> }
>
> + intel_de_write_fw(dev_priv, SPCONSTALPHA(pipe, plane_id), 0);
> +
> intel_de_write_fw(dev_priv, SPLINOFF(pipe, plane_id), linear_offset);
> intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id), (y << 16) | x);
>
> @@ -1791,6 +1805,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> return plane;
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> + plane->update_noarm = vlv_sprite_update_noarm;
> plane->update_arm = vlv_sprite_update_arm;
> plane->disable_arm = vlv_sprite_disable_arm;
> plane->get_hw_state = vlv_sprite_get_hw_state;
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Intel-gfx] [PATCH 8/9] drm/i915: Split ivb+ sprite plane update into noarm+arm pair
2021-10-18 11:50 ` [Intel-gfx] [PATCH 8/9] drm/i915: Split ivb+ " Ville Syrjala
@ 2021-11-03 18:45 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 38+ messages in thread
From: Lisovskiy, Stanislav @ 2021-11-03 18:45 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Mon, Oct 18, 2021 at 02:50:29PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Chop ivb_sprite_update() into two halves. Fist half becomes
> the _noarm() variant, second part the _arm() variant.
>
> Fortunately I have already previously grouped the register
> writes into roughtly the correct order, so the split looks
> surprisingly clean.
>
> Didn't bother with i915_update_info numbers for this one.
> I expect the results to be pretty much identical to the snb
> numbers from the corresponding g4x+ sprite modification.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 42 ++++++++++++++-------
> 1 file changed, 28 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 03e3bf890ce9..4e5f95aebeca 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -835,30 +835,22 @@ static void ivb_sprite_update_gamma(const struct intel_plane_state *plane_state)
> i++;
> }
>
> -/* TODO: split into noarm+arm pair */
> static void
> -ivb_sprite_update_arm(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state)
> +ivb_sprite_update_noarm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
> - u32 sprsurf_offset = plane_state->view.color_plane[0].offset;
> - u32 linear_offset;
> - const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> int crtc_x = plane_state->uapi.dst.x1;
> int crtc_y = plane_state->uapi.dst.y1;
> u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
> u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
> - u32 x = plane_state->view.color_plane[0].x;
> - u32 y = plane_state->view.color_plane[0].y;
> u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
> u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
> - u32 sprctl, sprscale = 0;
> + u32 sprscale = 0;
> unsigned long irqflags;
>
> - sprctl = plane_state->ctl | ivb_sprite_ctl_crtc(crtc_state);
> -
> /* Sizes are 0 based */
> src_w--;
> src_h--;
> @@ -868,8 +860,6 @@ ivb_sprite_update_arm(struct intel_plane *plane,
> if (crtc_w != src_w || crtc_h != src_h)
> sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
>
> - linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
> -
> spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>
> intel_de_write_fw(dev_priv, SPRSTRIDE(pipe),
> @@ -879,6 +869,29 @@ ivb_sprite_update_arm(struct intel_plane *plane,
> if (IS_IVYBRIDGE(dev_priv))
> intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale);
>
> + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> +}
> +
> +static void
> +ivb_sprite_update_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + enum pipe pipe = plane->pipe;
> + const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> + u32 sprsurf_offset = plane_state->view.color_plane[0].offset;
> + u32 x = plane_state->view.color_plane[0].x;
> + u32 y = plane_state->view.color_plane[0].y;
> + u32 sprctl, linear_offset;
> + unsigned long irqflags;
> +
> + sprctl = plane_state->ctl | ivb_sprite_ctl_crtc(crtc_state);
> +
> + linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
> +
> + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> +
> if (key->flags) {
> intel_de_write_fw(dev_priv, SPRKEYVAL(pipe), key->min_value);
> intel_de_write_fw(dev_priv, SPRKEYMSK(pipe),
> @@ -1796,6 +1809,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>
> plane_funcs = &vlv_sprite_funcs;
> } else if (DISPLAY_VER(dev_priv) >= 7) {
> + plane->update_noarm = ivb_sprite_update_noarm;
> plane->update_arm = ivb_sprite_update_arm;
> plane->disable_arm = ivb_sprite_disable_arm;
> plane->get_hw_state = ivb_sprite_get_hw_state;
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Intel-gfx] [PATCH 7/9] drm/i915: Split g4x+ sprite plane update into noarm+arm pair
2021-10-18 11:50 ` [Intel-gfx] [PATCH 7/9] drm/i915: Split g4x+ sprite " Ville Syrjala
@ 2021-11-03 18:46 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 38+ messages in thread
From: Lisovskiy, Stanislav @ 2021-11-03 18:46 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Mon, Oct 18, 2021 at 02:50:28PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Chop g4x_sprite_update() into two halves. Fist half becomes
> the _noarm() variant, second part the _arm() variant.
>
> Fortunately I have already previously grouped the register
> writes into roughtly the correct order, so the split looks
> surprisingly clean.
>
> Not much of a change in i915_update_info on these older
> platforms that don't have so many planes or registers to
> begin with. Here are the numbers from snb (totally unpatched
> vs. both primary plane and sprite patched applied) running
> kms_atomic_transition --r plane-all-transition --extended:
> w/o patch w/ patch
> Updates: 5404 Updates: 5405
> | |
> 1us |****** 1us |******
> |********* |*********
> 4us |*********** 4us |***********
> |********** |**********
> 16us |** 16us |**
> | |
> 66us | 66us |
> | |
> 262us | 262us |
> | |
> 1ms | 1ms |
> | |
> 4ms | 4ms |
> | |
> 17ms | 17ms |
> | |
> Min update: 1400ns Min update: 1307ns
> Max update: 19809ns Max update: 20194ns
> Average update: 6957ns Average update: 6432ns
> Overruns > 100us: 0 Overruns > 100us: 0
>
> But there seems to be a slight improvement with
> lockdep enabled:
> w/o patch w/ patch
> Updates: 17612 Updates: 16364
> | |
> 1us | 1us |
> |****** |******
> 4us |********** 4us |**********
> |************ |*************
> 16us |************* 16us |************
> |*** |*
> 66us | 66us |
> | |
> 262us | 262us |
> | |
> 1ms | 1ms |
> | |
> 4ms | 4ms |
> | |
> 17ms | 17ms |
> | |
> Min update: 3141ns Min update: 3562ns
> Max update: 126450ns Max update: 73354ns
> Average update: 16373ns Average update: 15153ns
> Overruns > 250us: 0 Overruns > 250us: 0
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 41 ++++++++++++++-------
> 1 file changed, 28 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 9c36c1492b33..03e3bf890ce9 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -1165,28 +1165,21 @@ static void ilk_sprite_update_gamma(const struct intel_plane_state *plane_state)
> }
>
> static void
> -g4x_sprite_update_arm(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state)
> +g4x_sprite_update_noarm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
> - u32 dvssurf_offset = plane_state->view.color_plane[0].offset;
> - u32 linear_offset;
> - const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> int crtc_x = plane_state->uapi.dst.x1;
> int crtc_y = plane_state->uapi.dst.y1;
> u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
> u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
> - u32 x = plane_state->view.color_plane[0].x;
> - u32 y = plane_state->view.color_plane[0].y;
> u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
> u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
> - u32 dvscntr, dvsscale = 0;
> + u32 dvsscale = 0;
> unsigned long irqflags;
>
> - dvscntr = plane_state->ctl | g4x_sprite_ctl_crtc(crtc_state);
> -
> /* Sizes are 0 based */
> src_w--;
> src_h--;
> @@ -1196,8 +1189,6 @@ g4x_sprite_update_arm(struct intel_plane *plane,
> if (crtc_w != src_w || crtc_h != src_h)
> dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
>
> - linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
> -
> spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>
> intel_de_write_fw(dev_priv, DVSSTRIDE(pipe),
> @@ -1206,6 +1197,29 @@ g4x_sprite_update_arm(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
> intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale);
>
> + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> +}
> +
> +static void
> +g4x_sprite_update_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + enum pipe pipe = plane->pipe;
> + const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> + u32 dvssurf_offset = plane_state->view.color_plane[0].offset;
> + u32 x = plane_state->view.color_plane[0].x;
> + u32 y = plane_state->view.color_plane[0].y;
> + u32 dvscntr, linear_offset;
> + unsigned long irqflags;
> +
> + dvscntr = plane_state->ctl | g4x_sprite_ctl_crtc(crtc_state);
> +
> + linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
> +
> + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> +
> if (key->flags) {
> intel_de_write_fw(dev_priv, DVSKEYVAL(pipe), key->min_value);
> intel_de_write_fw(dev_priv, DVSKEYMSK(pipe),
> @@ -1801,6 +1815,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>
> plane_funcs = &snb_sprite_funcs;
> } else {
> + plane->update_noarm = g4x_sprite_update_noarm;
> plane->update_arm = g4x_sprite_update_arm;
> plane->disable_arm = g4x_sprite_disable_arm;
> plane->get_hw_state = g4x_sprite_get_hw_state;
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Intel-gfx] [PATCH 5/9] drm/i915: Split skl+ plane update into noarm+arm pair
2021-10-18 11:50 ` [Intel-gfx] [PATCH 5/9] drm/i915: Split skl+ plane update into noarm+arm pair Ville Syrjala
2021-10-18 12:06 ` Lisovskiy, Stanislav
2021-10-27 17:11 ` Lisovskiy, Stanislav
@ 2021-11-03 18:46 ` Lisovskiy, Stanislav
2 siblings, 0 replies; 38+ messages in thread
From: Lisovskiy, Stanislav @ 2021-11-03 18:46 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Mon, Oct 18, 2021 at 02:50:26PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Chop skl_program_plane() into two halves. Fist half becomes
> the _noarm() variant, second part the _arm() variant.
>
> Fortunately I have already previously grouped the register
> writes into roughtly the correct order, so the split looks
> surprisingly clean.
>
> A few notable oddities I did not realize were self arming
> are AUX_DIST and COLOR_CTL.
>
> i915_update_info doesn't look too terrible on my cfl running
> kms_atomic_transition --r plane-all-transition --extended:
> w/o patch w/ patch
> Updates: 2178 Updates: 2018
> | |
> 1us | 1us |
> | |
> 4us | 4us |*****
> |********* |**********
> 16us |********** 16us |*******
> |*** |
> 66us | 66us |
> | |
> 262us | 262us |
> | |
> 1ms | 1ms |
> | |
> 4ms | 4ms |
> | |
> 17ms | 17ms |
> | |
> Min update: 8332ns Min update: 6164ns
> Max update: 48758ns Max update: 31808ns
> Average update: 19959ns Average update: 13159ns
> Overruns > 100us: 0 Overruns > 100us: 0
>
> And with lockdep enabled:
> w/o patch w/ patch
> Updates: 2177 Updates: 2172
> | |
> 1us | 1us |
> | |
> 4us | 4us |
> |******* |*********
> 16us |********** 16us |**********
> |******* |*
> 66us | 66us |
> | |
> 262us | 262us |
> | |
> 1ms | 1ms |
> | |
> 4ms | 4ms |
> | |
> 17ms | 17ms |
> | |
> Min update: 12645ns Min update: 9980ns
> Max update: 50153ns Max update: 33533ns
> Average update: 25337ns Average update: 18245ns
> Overruns > 250us: 0 Overruns > 250us: 0
>
> TODO: On icl+ everything seems to be armed by PLANE_SURF, so we
> can optimize this even further on modern platforms. But I
> think there's a bit of refactoring to be done first to
> figure out the best way to go about it (eg. just reusing
> the current skl+ functions, or doing a lower level split).
>
> TODO: Split scaler programming as well, but IIRC the scaler
> has some oddball double buffering behaviour on some
> platforms, so needs proper reverse engineering
>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> .../drm/i915/display/skl_universal_plane.c | 113 +++++++++++-------
> 1 file changed, 72 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 74f3870d39b1..2a822e1e465e 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -1050,60 +1050,32 @@ static void icl_plane_csc_load_black(struct intel_plane *plane)
> }
>
> static void
> -skl_program_plane(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state,
> - int color_plane)
> +skl_program_plane_noarm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state,
> + int color_plane)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum plane_id plane_id = plane->id;
> enum pipe pipe = plane->pipe;
> - const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> u32 stride = skl_plane_stride(plane_state, color_plane);
> const struct drm_framebuffer *fb = plane_state->hw.fb;
> - int aux_plane = skl_main_to_aux_plane(fb, color_plane);
> int crtc_x = plane_state->uapi.dst.x1;
> int crtc_y = plane_state->uapi.dst.y1;
> - u32 x = plane_state->view.color_plane[color_plane].x;
> - u32 y = plane_state->view.color_plane[color_plane].y;
> u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
> u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
> - u8 alpha = plane_state->hw.alpha >> 8;
> - u32 plane_color_ctl = 0, aux_dist = 0;
> unsigned long irqflags;
> - u32 keymsk, keymax;
> - u32 plane_ctl = plane_state->ctl;
> -
> - plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> -
> - if (DISPLAY_VER(dev_priv) >= 10)
> - plane_color_ctl = plane_state->color_ctl |
> - glk_plane_color_ctl_crtc(crtc_state);
>
> /* Sizes are 0 based */
> src_w--;
> src_h--;
>
> - keymax = (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
> -
> - keymsk = key->channel_mask & 0x7ffffff;
> - if (alpha < 0xff)
> - keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
> -
> /* The scaler will handle the output position */
> if (plane_state->scaler_id >= 0) {
> crtc_x = 0;
> crtc_y = 0;
> }
>
> - if (aux_plane) {
> - aux_dist = skl_surf_address(plane_state, aux_plane) -
> - skl_surf_address(plane_state, color_plane);
> -
> - if (DISPLAY_VER(dev_priv) < 12)
> - aux_dist |= skl_plane_stride(plane_state, aux_plane);
> - }
> -
> spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>
> /*
> @@ -1119,16 +1091,10 @@ skl_program_plane(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
> (src_h << 16) | src_w);
>
> - intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);
> -
> if (icl_is_hdr_plane(dev_priv, plane_id))
> intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id),
> plane_state->cus_ctl);
>
> - if (DISPLAY_VER(dev_priv) >= 10)
> - intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id),
> - plane_color_ctl);
> -
> if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
> icl_program_input_csc(plane, crtc_state, plane_state);
>
> @@ -1138,6 +1104,52 @@ skl_program_plane(struct intel_plane *plane,
>
> skl_write_plane_wm(plane, crtc_state);
>
> + intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane);
> +
> + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> +}
> +
> +static void
> +skl_program_plane_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state,
> + int color_plane)
> +{
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + enum plane_id plane_id = plane->id;
> + enum pipe pipe = plane->pipe;
> + const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> + const struct drm_framebuffer *fb = plane_state->hw.fb;
> + int aux_plane = skl_main_to_aux_plane(fb, color_plane);
> + u32 x = plane_state->view.color_plane[color_plane].x;
> + u32 y = plane_state->view.color_plane[color_plane].y;
> + u32 keymsk, keymax, aux_dist = 0, plane_color_ctl = 0;
> + u8 alpha = plane_state->hw.alpha >> 8;
> + u32 plane_ctl = plane_state->ctl;
> + unsigned long irqflags;
> +
> + plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> +
> + if (DISPLAY_VER(dev_priv) >= 10)
> + plane_color_ctl = plane_state->color_ctl |
> + glk_plane_color_ctl_crtc(crtc_state);
> +
> + keymax = (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
> +
> + keymsk = key->channel_mask & 0x7ffffff;
> + if (alpha < 0xff)
> + keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
> +
> + if (aux_plane) {
> + aux_dist = skl_surf_address(plane_state, aux_plane) -
> + skl_surf_address(plane_state, color_plane);
> +
> + if (DISPLAY_VER(dev_priv) < 12)
> + aux_dist |= skl_plane_stride(plane_state, aux_plane);
> + }
> +
> + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> +
> intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id),
> key->min_value);
> intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), keymsk);
> @@ -1146,17 +1158,22 @@ skl_program_plane(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
> (y << 16) | x);
>
> + intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);
> +
> if (DISPLAY_VER(dev_priv) < 11)
> intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
> (plane_state->view.color_plane[1].y << 16) |
> plane_state->view.color_plane[1].x);
>
> - intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane);
> + if (DISPLAY_VER(dev_priv) >= 10)
> + intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
>
> /*
> * Enable the scaler before the plane so that we don't
> * get a catastrophic underrun even if the two operations
> * end up happening in two different frames.
> + *
> + * TODO: split into noarm+arm pair
> */
> if (plane_state->scaler_id >= 0)
> skl_program_plane_scaler(plane, crtc_state, plane_state);
> @@ -1199,7 +1216,20 @@ skl_plane_async_flip(struct intel_plane *plane,
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
>
> -/* TODO: split into noarm+arm pair */
> +static void
> +skl_plane_update_noarm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> +{
> + int color_plane = 0;
> +
> + if (plane_state->planar_linked_plane && !plane_state->planar_slave)
> + /* Program the UV plane on planar master */
> + color_plane = 1;
> +
> + skl_program_plane_noarm(plane, crtc_state, plane_state, color_plane);
> +}
> +
> static void
> skl_plane_update_arm(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> @@ -1211,7 +1241,7 @@ skl_plane_update_arm(struct intel_plane *plane,
> /* Program the UV plane on planar master */
> color_plane = 1;
>
> - skl_program_plane(plane, crtc_state, plane_state, color_plane);
> + skl_program_plane_arm(plane, crtc_state, plane_state, color_plane);
> }
>
> static bool intel_format_is_p01x(u32 format)
> @@ -2159,6 +2189,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
> }
>
> plane->max_stride = skl_plane_max_stride;
> + plane->update_noarm = skl_plane_update_noarm;
> plane->update_arm = skl_plane_update_arm;
> plane->disable_arm = skl_plane_disable_arm;
> plane->get_hw_state = skl_plane_get_hw_state;
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Intel-gfx] [PATCH 6/9] drm/i915: Split pre-skl primary plane update into noarm+arm pair
2021-10-18 11:50 ` [Intel-gfx] [PATCH 6/9] drm/i915: Split pre-skl primary " Ville Syrjala
2021-10-20 21:27 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
@ 2021-11-03 18:47 ` Lisovskiy, Stanislav
1 sibling, 0 replies; 38+ messages in thread
From: Lisovskiy, Stanislav @ 2021-11-03 18:47 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Mon, Oct 18, 2021 at 02:50:27PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Chop i9xx_plane_update() into two halves. Fist half becomes
> the _noarm() variant, second part the _arm() variant.
>
> Fortunately I have already previously grouped the register
> writes into roughtly the correct order, so the split looks
> surprisingly clean.
>
> One slightly surprising fact was that the CHV pipe B PRIMPOS/SIZE
> registers are self arming unlike their pre-ctg DSPPOS/SIZE
> counterparts. In fact all the new CHV pipe B registers are
> self arming.
>
> I didn't do any i915_update_info measurements for this one
> alone. I'll get total numbers with the corrsponding sprite
> plane changes.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c | 61 +++++++++++++++--------
> 1 file changed, 40 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index 93163f9100a8..9dfd0a53e0ee 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -418,23 +418,49 @@ static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
> return DIV_ROUND_UP(pixel_rate * num, den);
> }
>
> -/* TODO: split into noarm+arm pair */
> +static void i9xx_plane_update_noarm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> + unsigned long irqflags;
> +
> + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> +
> + intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),
> + plane_state->view.color_plane[0].stride);
> +
> + if (DISPLAY_VER(dev_priv) < 4) {
> + int crtc_x = plane_state->uapi.dst.x1;
> + int crtc_y = plane_state->uapi.dst.y1;
> + int crtc_w = drm_rect_width(&plane_state->uapi.dst);
> + int crtc_h = drm_rect_height(&plane_state->uapi.dst);
> +
> + /*
> + * PLANE_A doesn't actually have a full window
> + * generator but let's assume we still need to
> + * program whatever is there.
> + */
> + intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
> + (crtc_y << 16) | crtc_x);
> + intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
> + ((crtc_h - 1) << 16) | (crtc_w - 1));
> + }
> +
> + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> +}
> +
> static void i9xx_plane_update_arm(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> - u32 linear_offset;
> int x = plane_state->view.color_plane[0].x;
> int y = plane_state->view.color_plane[0].y;
> - int crtc_x = plane_state->uapi.dst.x1;
> - int crtc_y = plane_state->uapi.dst.y1;
> - int crtc_w = drm_rect_width(&plane_state->uapi.dst);
> - int crtc_h = drm_rect_height(&plane_state->uapi.dst);
> + u32 dspcntr, dspaddr_offset, linear_offset;
> unsigned long irqflags;
> - u32 dspaddr_offset;
> - u32 dspcntr;
>
> dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
>
> @@ -447,20 +473,12 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
>
> spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>
> - intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),
> - plane_state->view.color_plane[0].stride);
> + if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
> + int crtc_x = plane_state->uapi.dst.x1;
> + int crtc_y = plane_state->uapi.dst.y1;
> + int crtc_w = drm_rect_width(&plane_state->uapi.dst);
> + int crtc_h = drm_rect_height(&plane_state->uapi.dst);
>
> - if (DISPLAY_VER(dev_priv) < 4) {
> - /*
> - * PLANE_A doesn't actually have a full window
> - * generator but let's assume we still need to
> - * program whatever is there.
> - */
> - intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
> - (crtc_y << 16) | crtc_x);
> - intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
> - ((crtc_h - 1) << 16) | (crtc_w - 1));
> - } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
> intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane),
> (crtc_y << 16) | crtc_x);
> intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane),
> @@ -852,6 +870,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> plane->max_stride = ilk_primary_max_stride;
> }
>
> + plane->update_noarm = i9xx_plane_update_noarm;
> plane->update_arm = i9xx_plane_update_arm;
> plane->disable_arm = i9xx_plane_disable_arm;
> plane->get_hw_state = i9xx_plane_get_hw_state;
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Intel-gfx] [PATCH 4/9] drm/i915: Split update_plane() into update_noarm() + update_arm()
2021-10-18 11:50 ` [Intel-gfx] [PATCH 4/9] drm/i915: Split update_plane() into update_noarm() + update_arm() Ville Syrjala
2021-10-27 16:35 ` Lisovskiy, Stanislav
@ 2021-11-03 18:47 ` Lisovskiy, Stanislav
1 sibling, 0 replies; 38+ messages in thread
From: Lisovskiy, Stanislav @ 2021-11-03 18:47 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Mon, Oct 18, 2021 at 02:50:25PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The amount of plane registers we have to write has been steadily
> increasing, putting more pressure on the vblank evasion mechanism
> and forcing us to increase its time budget. Let's try to take some
> of the pressure off by splitting plane updates into two parts:
> 1) write all non-self arming plane registers, ie. the registers
> where the write actually does nothing until a separate arming
> register is also written which will cause the hardware to latch
> the new register values at the next start of vblank
> 2) write all self arming plane registers, ie. registers which always
> just latch at the next start of vblank, and registers which also
> arm other registers to do so
>
> Here we just provide the mechanism, but don't actually implement
> the split on any platform yet. so everything stays now in the _arm()
> hooks. Subsequently we can move a whole bunch of stuff into the
> _noarm() part, especially in more modern platforms where the number
> of registers we have to write is also the greatest. On older
> platforms this is less beneficial probably, but no real reason
> to deviate from a common behaviour.
>
> And let's sprinkle some TODOs around the areas that will need
> adapting.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c | 15 ++--
> .../gpu/drm/i915/display/intel_atomic_plane.c | 88 ++++++++++++++-----
> .../gpu/drm/i915/display/intel_atomic_plane.h | 23 +++--
> drivers/gpu/drm/i915/display/intel_cursor.c | 44 +++++-----
> drivers/gpu/drm/i915/display/intel_display.c | 12 +--
> .../drm/i915/display/intel_display_types.h | 12 ++-
> drivers/gpu/drm/i915/display/intel_sprite.c | 44 +++++-----
> .../drm/i915/display/skl_universal_plane.c | 15 ++--
> drivers/gpu/drm/i915/i915_trace.h | 33 ++++++-
> 9 files changed, 192 insertions(+), 94 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index b1439ba78f67..93163f9100a8 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -418,9 +418,10 @@ static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
> return DIV_ROUND_UP(pixel_rate * num, den);
> }
>
> -static void i9xx_update_plane(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state)
> +/* TODO: split into noarm+arm pair */
> +static void i9xx_plane_update_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> @@ -493,8 +494,8 @@ static void i9xx_update_plane(struct intel_plane *plane,
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
>
> -static void i9xx_disable_plane(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state)
> +static void i9xx_plane_disable_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> @@ -851,8 +852,8 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> plane->max_stride = ilk_primary_max_stride;
> }
>
> - plane->update_plane = i9xx_update_plane;
> - plane->disable_plane = i9xx_disable_plane;
> + plane->update_arm = i9xx_plane_update_arm;
> + plane->disable_arm = i9xx_plane_disable_arm;
> plane->get_hw_state = i9xx_plane_get_hw_state;
> plane->check_plane = i9xx_plane_check;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 0be8c00e3db9..ae21770fc321 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -469,31 +469,72 @@ skl_next_plane_to_commit(struct intel_atomic_state *state,
> return NULL;
> }
>
> -void intel_update_plane(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state)
> +void intel_plane_update_noarm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> - trace_intel_update_plane(&plane->base, crtc);
> + trace_intel_plane_update_noarm(&plane->base, crtc);
> +
> + if (plane->update_noarm)
> + plane->update_noarm(plane, crtc_state, plane_state);
> +}
> +
> +void intel_plane_update_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +
> + trace_intel_plane_update_arm(&plane->base, crtc);
>
> if (crtc_state->uapi.async_flip && plane->async_flip)
> plane->async_flip(plane, crtc_state, plane_state, true);
> else
> - plane->update_plane(plane, crtc_state, plane_state);
> + plane->update_arm(plane, crtc_state, plane_state);
> }
>
> -void intel_disable_plane(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state)
> +void intel_plane_disable_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> - trace_intel_disable_plane(&plane->base, crtc);
> - plane->disable_plane(plane, crtc_state);
> + trace_intel_plane_disable_arm(&plane->base, crtc);
> + plane->disable_arm(plane, crtc_state);
> }
>
> -void skl_update_planes_on_crtc(struct intel_atomic_state *state,
> - struct intel_crtc *crtc)
> +void intel_update_planes_on_crtc(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> +{
> + struct intel_crtc_state *new_crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + u32 update_mask = new_crtc_state->update_planes;
> + struct intel_plane_state *new_plane_state;
> + struct intel_plane *plane;
> + int i;
> +
> + if (new_crtc_state->uapi.async_flip)
> + return;
> +
> + /*
> + * Since we only write non-arming registers here,
> + * the order does not matter even for skl+.
> + */
> + for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
> + if (crtc->pipe != plane->pipe ||
> + !(update_mask & BIT(plane->id)))
> + continue;
> +
> + /* TODO: for mailbox updates this should be skipped */
> + if (new_plane_state->uapi.visible ||
> + new_plane_state->planar_slave)
> + intel_plane_update_noarm(plane, new_crtc_state, new_plane_state);
> + }
> +}
> +
> +void skl_arm_planes_on_crtc(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> struct intel_crtc_state *old_crtc_state =
> intel_atomic_get_old_crtc_state(state, crtc);
> @@ -515,17 +556,20 @@ void skl_update_planes_on_crtc(struct intel_atomic_state *state,
> struct intel_plane_state *new_plane_state =
> intel_atomic_get_new_plane_state(state, plane);
>
> + /*
> + * TODO: for mailbox updates intel_plane_update_noarm()
> + * would have to be called here as well.
> + */
> if (new_plane_state->uapi.visible ||
> - new_plane_state->planar_slave) {
> - intel_update_plane(plane, new_crtc_state, new_plane_state);
> - } else {
> - intel_disable_plane(plane, new_crtc_state);
> - }
> + new_plane_state->planar_slave)
> + intel_plane_update_arm(plane, new_crtc_state, new_plane_state);
> + else
> + intel_plane_disable_arm(plane, new_crtc_state);
> }
> }
>
> -void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
> - struct intel_crtc *crtc)
> +void i9xx_arm_planes_on_crtc(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> @@ -539,10 +583,14 @@ void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
> !(update_mask & BIT(plane->id)))
> continue;
>
> + /*
> + * TODO: for mailbox updates intel_plane_update_noarm()
> + * would have to be called here as well.
> + */
> if (new_plane_state->uapi.visible)
> - intel_update_plane(plane, new_crtc_state, new_plane_state);
> + intel_plane_update_arm(plane, new_crtc_state, new_plane_state);
> else
> - intel_disable_plane(plane, new_crtc_state);
> + intel_plane_disable_arm(plane, new_crtc_state);
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> index 62e5a2a77fd4..7907f601598e 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> @@ -30,20 +30,25 @@ void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
> struct intel_crtc *crtc);
> void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,
> const struct intel_plane_state *from_plane_state);
> -void intel_update_plane(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state);
> -void intel_disable_plane(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state);
> +void intel_plane_update_noarm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state);
> +void intel_plane_update_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state);
> +void intel_plane_disable_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state);
> struct intel_plane *intel_plane_alloc(void);
> void intel_plane_free(struct intel_plane *plane);
> struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
> void intel_plane_destroy_state(struct drm_plane *plane,
> struct drm_plane_state *state);
> -void skl_update_planes_on_crtc(struct intel_atomic_state *state,
> - struct intel_crtc *crtc);
> -void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
> - struct intel_crtc *crtc);
> +void intel_update_planes_on_crtc(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> +void skl_arm_planes_on_crtc(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> +void i9xx_arm_planes_on_crtc(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
> struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *old_plane_state,
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> index 11842f212613..826337a769b5 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> @@ -253,9 +253,10 @@ static int i845_check_cursor(struct intel_crtc_state *crtc_state,
> return 0;
> }
>
> -static void i845_update_cursor(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state)
> +/* TODO: split into noarm+arm pair */
> +static void i845_cursor_update_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> u32 cntl = 0, base = 0, pos = 0, size = 0;
> @@ -298,10 +299,10 @@ static void i845_update_cursor(struct intel_plane *plane,
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
>
> -static void i845_disable_cursor(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state)
> +static void i845_cursor_disable_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state)
> {
> - i845_update_cursor(plane, crtc_state, NULL);
> + i845_cursor_update_arm(plane, crtc_state, NULL);
> }
>
> static bool i845_cursor_get_hw_state(struct intel_plane *plane,
> @@ -488,9 +489,10 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
> return 0;
> }
>
> -static void i9xx_update_cursor(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state)
> +/* TODO: split into noarm+arm pair */
> +static void i9xx_cursor_update_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
> @@ -562,10 +564,10 @@ static void i9xx_update_cursor(struct intel_plane *plane,
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
>
> -static void i9xx_disable_cursor(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state)
> +static void i9xx_cursor_disable_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state)
> {
> - i9xx_update_cursor(plane, crtc_state, NULL);
> + i9xx_cursor_update_arm(plane, crtc_state, NULL);
> }
>
> static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
> @@ -717,10 +719,12 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
> */
> crtc_state->active_planes = new_crtc_state->active_planes;
>
> - if (new_plane_state->uapi.visible)
> - intel_update_plane(plane, crtc_state, new_plane_state);
> - else
> - intel_disable_plane(plane, crtc_state);
> + if (new_plane_state->uapi.visible) {
> + intel_plane_update_noarm(plane, crtc_state, new_plane_state);
> + intel_plane_update_arm(plane, crtc_state, new_plane_state);
> + } else {
> + intel_plane_disable_arm(plane, crtc_state);
> + }
>
> intel_plane_unpin_fb(old_plane_state);
>
> @@ -766,14 +770,14 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
>
> if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
> cursor->max_stride = i845_cursor_max_stride;
> - cursor->update_plane = i845_update_cursor;
> - cursor->disable_plane = i845_disable_cursor;
> + cursor->update_arm = i845_cursor_update_arm;
> + cursor->disable_arm = i845_cursor_disable_arm;
> cursor->get_hw_state = i845_cursor_get_hw_state;
> cursor->check_plane = i845_check_cursor;
> } else {
> cursor->max_stride = i9xx_cursor_max_stride;
> - cursor->update_plane = i9xx_update_cursor;
> - cursor->disable_plane = i9xx_disable_cursor;
> + cursor->update_arm = i9xx_cursor_update_arm;
> + cursor->disable_arm = i9xx_cursor_disable_arm;
> cursor->get_hw_state = i9xx_cursor_get_hw_state;
> cursor->check_plane = i9xx_check_cursor;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 8bb87e839f4a..a685aad738f3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1126,7 +1126,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
> if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
> intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
>
> - intel_disable_plane(plane, crtc_state);
> + intel_plane_disable_arm(plane, crtc_state);
> intel_wait_for_vblank(dev_priv, crtc->pipe);
> }
>
> @@ -2156,7 +2156,7 @@ static void intel_crtc_disable_planes(struct intel_atomic_state *state,
> !(update_mask & BIT(plane->id)))
> continue;
>
> - intel_disable_plane(plane, new_crtc_state);
> + intel_plane_disable_arm(plane, new_crtc_state);
>
> if (old_plane_state->uapi.visible)
> fb_bits |= plane->frontbuffer_bit;
> @@ -2423,7 +2423,7 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct intel_plane *plane = to_intel_plane(crtc->base.primary);
>
> - plane->disable_plane(plane, crtc_state);
> + plane->disable_arm(plane, crtc_state);
> }
>
> static void ilk_crtc_enable(struct intel_atomic_state *state,
> @@ -9387,15 +9387,17 @@ static void intel_update_crtc(struct intel_atomic_state *state,
>
> intel_fbc_update(state, crtc);
>
> + intel_update_planes_on_crtc(state, crtc);
> +
> /* Perform vblank evasion around commit operation */
> intel_pipe_update_start(new_crtc_state);
>
> commit_pipe_pre_planes(state, crtc);
>
> if (DISPLAY_VER(dev_priv) >= 9)
> - skl_update_planes_on_crtc(state, crtc);
> + skl_arm_planes_on_crtc(state, crtc);
> else
> - i9xx_update_planes_on_crtc(state, crtc);
> + i9xx_arm_planes_on_crtc(state, crtc);
>
> commit_pipe_post_planes(state, crtc);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 39e11eaec1a3..907389fd6f85 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1362,11 +1362,17 @@ struct intel_plane {
> unsigned int (*max_stride)(struct intel_plane *plane,
> u32 pixel_format, u64 modifier,
> unsigned int rotation);
> - void (*update_plane)(struct intel_plane *plane,
> + /* Write all non-self arming plane registers */
> + void (*update_noarm)(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state);
> - void (*disable_plane)(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state);
> + /* Write all self-arming plane registers */
> + void (*update_arm)(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state);
> + /* Disable the plane, must arm */
> + void (*disable_arm)(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state);
> bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
> int (*check_plane)(struct intel_crtc_state *crtc_state,
> struct intel_plane_state *plane_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 1daa3360cf02..9c36c1492b33 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -416,10 +416,11 @@ static void vlv_sprite_update_gamma(const struct intel_plane_state *plane_state)
> gamma[i] << 16 | gamma[i] << 8 | gamma[i]);
> }
>
> +/* TODO: split into noarm+arm pair */
> static void
> -vlv_sprite_update(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state)
> +vlv_sprite_update_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
> @@ -485,8 +486,8 @@ vlv_sprite_update(struct intel_plane *plane,
> }
>
> static void
> -vlv_sprite_disable(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state)
> +vlv_sprite_disable_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
> @@ -834,10 +835,11 @@ static void ivb_sprite_update_gamma(const struct intel_plane_state *plane_state)
> i++;
> }
>
> +/* TODO: split into noarm+arm pair */
> static void
> -ivb_sprite_update(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state)
> +ivb_sprite_update_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
> @@ -908,8 +910,8 @@ ivb_sprite_update(struct intel_plane *plane,
> }
>
> static void
> -ivb_sprite_disable(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state)
> +ivb_sprite_disable_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
> @@ -1163,9 +1165,9 @@ static void ilk_sprite_update_gamma(const struct intel_plane_state *plane_state)
> }
>
> static void
> -g4x_sprite_update(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state)
> +g4x_sprite_update_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
> @@ -1232,8 +1234,8 @@ g4x_sprite_update(struct intel_plane *plane,
> }
>
> static void
> -g4x_sprite_disable(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state)
> +g4x_sprite_disable_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
> @@ -1762,8 +1764,8 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> return plane;
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> - plane->update_plane = vlv_sprite_update;
> - plane->disable_plane = vlv_sprite_disable;
> + plane->update_arm = vlv_sprite_update_arm;
> + plane->disable_arm = vlv_sprite_disable_arm;
> plane->get_hw_state = vlv_sprite_get_hw_state;
> plane->check_plane = vlv_sprite_check;
> plane->max_stride = i965_plane_max_stride;
> @@ -1780,8 +1782,8 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>
> plane_funcs = &vlv_sprite_funcs;
> } else if (DISPLAY_VER(dev_priv) >= 7) {
> - plane->update_plane = ivb_sprite_update;
> - plane->disable_plane = ivb_sprite_disable;
> + plane->update_arm = ivb_sprite_update_arm;
> + plane->disable_arm = ivb_sprite_disable_arm;
> plane->get_hw_state = ivb_sprite_get_hw_state;
> plane->check_plane = g4x_sprite_check;
>
> @@ -1799,8 +1801,8 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>
> plane_funcs = &snb_sprite_funcs;
> } else {
> - plane->update_plane = g4x_sprite_update;
> - plane->disable_plane = g4x_sprite_disable;
> + plane->update_arm = g4x_sprite_update_arm;
> + plane->disable_arm = g4x_sprite_disable_arm;
> plane->get_hw_state = g4x_sprite_get_hw_state;
> plane->check_plane = g4x_sprite_check;
> plane->max_stride = g4x_sprite_max_stride;
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index e2f024449149..74f3870d39b1 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -642,8 +642,8 @@ static u32 skl_plane_stride(const struct intel_plane_state *plane_state,
> }
>
> static void
> -skl_disable_plane(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state)
> +skl_plane_disable_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum plane_id plane_id = plane->id;
> @@ -1199,10 +1199,11 @@ skl_plane_async_flip(struct intel_plane *plane,
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
>
> +/* TODO: split into noarm+arm pair */
> static void
> -skl_update_plane(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state)
> +skl_plane_update_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> {
> int color_plane = 0;
>
> @@ -2158,8 +2159,8 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
> }
>
> plane->max_stride = skl_plane_max_stride;
> - plane->update_plane = skl_update_plane;
> - plane->disable_plane = skl_disable_plane;
> + plane->update_arm = skl_plane_update_arm;
> + plane->disable_arm = skl_plane_disable_arm;
> plane->get_hw_state = skl_plane_get_hw_state;
> plane->check_plane = skl_plane_check;
>
> diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
> index 9795f456cccf..214696d6b270 100644
> --- a/drivers/gpu/drm/i915/i915_trace.h
> +++ b/drivers/gpu/drm/i915/i915_trace.h
> @@ -288,7 +288,7 @@ TRACE_EVENT(vlv_fifo_size,
>
> /* plane updates */
>
> -TRACE_EVENT(intel_update_plane,
> +TRACE_EVENT(intel_plane_update_noarm,
> TP_PROTO(struct drm_plane *plane, struct intel_crtc *crtc),
> TP_ARGS(plane, crtc),
>
> @@ -317,7 +317,36 @@ TRACE_EVENT(intel_update_plane,
> DRM_RECT_ARG((const struct drm_rect *)__entry->dst))
> );
>
> -TRACE_EVENT(intel_disable_plane,
> +TRACE_EVENT(intel_plane_update_arm,
> + TP_PROTO(struct drm_plane *plane, struct intel_crtc *crtc),
> + TP_ARGS(plane, crtc),
> +
> + TP_STRUCT__entry(
> + __field(enum pipe, pipe)
> + __field(u32, frame)
> + __field(u32, scanline)
> + __array(int, src, 4)
> + __array(int, dst, 4)
> + __string(name, plane->name)
> + ),
> +
> + TP_fast_assign(
> + __assign_str(name, plane->name);
> + __entry->pipe = crtc->pipe;
> + __entry->frame = intel_crtc_get_vblank_counter(crtc);
> + __entry->scanline = intel_get_crtc_scanline(crtc);
> + memcpy(__entry->src, &plane->state->src, sizeof(__entry->src));
> + memcpy(__entry->dst, &plane->state->dst, sizeof(__entry->dst));
> + ),
> +
> + TP_printk("pipe %c, plane %s, frame=%u, scanline=%u, " DRM_RECT_FP_FMT " -> " DRM_RECT_FMT,
> + pipe_name(__entry->pipe), __get_str(name),
> + __entry->frame, __entry->scanline,
> + DRM_RECT_FP_ARG((const struct drm_rect *)__entry->src),
> + DRM_RECT_ARG((const struct drm_rect *)__entry->dst))
> +);
> +
> +TRACE_EVENT(intel_plane_disable_arm,
> TP_PROTO(struct drm_plane *plane, struct intel_crtc *crtc),
> TP_ARGS(plane, crtc),
>
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Intel-gfx] [PATCH 3/9] drm/i915: Fix up the sprite namespacing
2021-10-18 11:50 ` [Intel-gfx] [PATCH 3/9] drm/i915: Fix up the sprite namespacing Ville Syrjala
@ 2021-11-03 18:47 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 38+ messages in thread
From: Lisovskiy, Stanislav @ 2021-11-03 18:47 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Mon, Oct 18, 2021 at 02:50:24PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Give all sprite exclusive functions/etc. a proper namespace.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 106 ++++++++++----------
> 1 file changed, 53 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 08116f41da26..1daa3360cf02 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -118,7 +118,7 @@ static void i9xx_plane_linear_gamma(u16 gamma[8])
> }
>
> static void
> -chv_update_csc(const struct intel_plane_state *plane_state)
> +chv_sprite_update_csc(const struct intel_plane_state *plane_state)
> {
> struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> @@ -190,7 +190,7 @@ chv_update_csc(const struct intel_plane_state *plane_state)
> #define COS_0 1
>
> static void
> -vlv_update_clrc(const struct intel_plane_state *plane_state)
> +vlv_sprite_update_clrc(const struct intel_plane_state *plane_state)
> {
> struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> @@ -393,7 +393,7 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
> return sprctl;
> }
>
> -static void vlv_update_gamma(const struct intel_plane_state *plane_state)
> +static void vlv_sprite_update_gamma(const struct intel_plane_state *plane_state)
> {
> struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> @@ -417,9 +417,9 @@ static void vlv_update_gamma(const struct intel_plane_state *plane_state)
> }
>
> static void
> -vlv_update_plane(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state)
> +vlv_sprite_update(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
> @@ -455,7 +455,7 @@ vlv_update_plane(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, SPCONSTALPHA(pipe, plane_id), 0);
>
> if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
> - chv_update_csc(plane_state);
> + chv_sprite_update_csc(plane_state);
>
> if (key->flags) {
> intel_de_write_fw(dev_priv, SPKEYMINVAL(pipe, plane_id),
> @@ -478,15 +478,15 @@ vlv_update_plane(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id),
> intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
>
> - vlv_update_clrc(plane_state);
> - vlv_update_gamma(plane_state);
> + vlv_sprite_update_clrc(plane_state);
> + vlv_sprite_update_gamma(plane_state);
>
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
>
> static void
> -vlv_disable_plane(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state)
> +vlv_sprite_disable(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
> @@ -502,8 +502,8 @@ vlv_disable_plane(struct intel_plane *plane,
> }
>
> static bool
> -vlv_plane_get_hw_state(struct intel_plane *plane,
> - enum pipe *pipe)
> +vlv_sprite_get_hw_state(struct intel_plane *plane,
> + enum pipe *pipe)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum intel_display_power_domain power_domain;
> @@ -805,7 +805,7 @@ static void ivb_sprite_linear_gamma(const struct intel_plane_state *plane_state,
> i++;
> }
>
> -static void ivb_update_gamma(const struct intel_plane_state *plane_state)
> +static void ivb_sprite_update_gamma(const struct intel_plane_state *plane_state)
> {
> struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> @@ -835,9 +835,9 @@ static void ivb_update_gamma(const struct intel_plane_state *plane_state)
> }
>
> static void
> -ivb_update_plane(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state)
> +ivb_sprite_update(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
> @@ -902,14 +902,14 @@ ivb_update_plane(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, SPRSURF(pipe),
> intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
>
> - ivb_update_gamma(plane_state);
> + ivb_sprite_update_gamma(plane_state);
>
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
>
> static void
> -ivb_disable_plane(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state)
> +ivb_sprite_disable(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
> @@ -927,8 +927,8 @@ ivb_disable_plane(struct intel_plane *plane,
> }
>
> static bool
> -ivb_plane_get_hw_state(struct intel_plane *plane,
> - enum pipe *pipe)
> +ivb_sprite_get_hw_state(struct intel_plane *plane,
> + enum pipe *pipe)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum intel_display_power_domain power_domain;
> @@ -1106,7 +1106,7 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
> return dvscntr;
> }
>
> -static void g4x_update_gamma(const struct intel_plane_state *plane_state)
> +static void g4x_sprite_update_gamma(const struct intel_plane_state *plane_state)
> {
> struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> @@ -1136,7 +1136,7 @@ static void ilk_sprite_linear_gamma(u16 gamma[17])
> gamma[i] = (i << 10) / 16;
> }
>
> -static void ilk_update_gamma(const struct intel_plane_state *plane_state)
> +static void ilk_sprite_update_gamma(const struct intel_plane_state *plane_state)
> {
> struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> @@ -1163,9 +1163,9 @@ static void ilk_update_gamma(const struct intel_plane_state *plane_state)
> }
>
> static void
> -g4x_update_plane(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state)
> +g4x_sprite_update(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
> @@ -1224,16 +1224,16 @@ g4x_update_plane(struct intel_plane *plane,
> intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
>
> if (IS_G4X(dev_priv))
> - g4x_update_gamma(plane_state);
> + g4x_sprite_update_gamma(plane_state);
> else
> - ilk_update_gamma(plane_state);
> + ilk_sprite_update_gamma(plane_state);
>
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
>
> static void
> -g4x_disable_plane(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state)
> +g4x_sprite_disable(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
> @@ -1250,8 +1250,8 @@ g4x_disable_plane(struct intel_plane *plane,
> }
>
> static bool
> -g4x_plane_get_hw_state(struct intel_plane *plane,
> - enum pipe *pipe)
> +g4x_sprite_get_hw_state(struct intel_plane *plane,
> + enum pipe *pipe)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum intel_display_power_domain power_domain;
> @@ -1567,7 +1567,7 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
> return ret;
> }
>
> -static const u32 g4x_plane_formats[] = {
> +static const u32 g4x_sprite_formats[] = {
> DRM_FORMAT_XRGB8888,
> DRM_FORMAT_YUYV,
> DRM_FORMAT_YVYU,
> @@ -1581,7 +1581,7 @@ static const u64 i9xx_plane_format_modifiers[] = {
> DRM_FORMAT_MOD_INVALID
> };
>
> -static const u32 snb_plane_formats[] = {
> +static const u32 snb_sprite_formats[] = {
> DRM_FORMAT_XRGB8888,
> DRM_FORMAT_XBGR8888,
> DRM_FORMAT_XRGB2101010,
> @@ -1594,7 +1594,7 @@ static const u32 snb_plane_formats[] = {
> DRM_FORMAT_VYUY,
> };
>
> -static const u32 vlv_plane_formats[] = {
> +static const u32 vlv_sprite_formats[] = {
> DRM_FORMAT_C8,
> DRM_FORMAT_RGB565,
> DRM_FORMAT_XRGB8888,
> @@ -1762,9 +1762,9 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> return plane;
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> - plane->update_plane = vlv_update_plane;
> - plane->disable_plane = vlv_disable_plane;
> - plane->get_hw_state = vlv_plane_get_hw_state;
> + plane->update_plane = vlv_sprite_update;
> + plane->disable_plane = vlv_sprite_disable;
> + plane->get_hw_state = vlv_sprite_get_hw_state;
> plane->check_plane = vlv_sprite_check;
> plane->max_stride = i965_plane_max_stride;
> plane->min_cdclk = vlv_plane_min_cdclk;
> @@ -1773,16 +1773,16 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> formats = chv_pipe_b_sprite_formats;
> num_formats = ARRAY_SIZE(chv_pipe_b_sprite_formats);
> } else {
> - formats = vlv_plane_formats;
> - num_formats = ARRAY_SIZE(vlv_plane_formats);
> + formats = vlv_sprite_formats;
> + num_formats = ARRAY_SIZE(vlv_sprite_formats);
> }
> modifiers = i9xx_plane_format_modifiers;
>
> plane_funcs = &vlv_sprite_funcs;
> } else if (DISPLAY_VER(dev_priv) >= 7) {
> - plane->update_plane = ivb_update_plane;
> - plane->disable_plane = ivb_disable_plane;
> - plane->get_hw_state = ivb_plane_get_hw_state;
> + plane->update_plane = ivb_sprite_update;
> + plane->disable_plane = ivb_sprite_disable;
> + plane->get_hw_state = ivb_sprite_get_hw_state;
> plane->check_plane = g4x_sprite_check;
>
> if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> @@ -1793,28 +1793,28 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> plane->min_cdclk = ivb_sprite_min_cdclk;
> }
>
> - formats = snb_plane_formats;
> - num_formats = ARRAY_SIZE(snb_plane_formats);
> + formats = snb_sprite_formats;
> + num_formats = ARRAY_SIZE(snb_sprite_formats);
> modifiers = i9xx_plane_format_modifiers;
>
> plane_funcs = &snb_sprite_funcs;
> } else {
> - plane->update_plane = g4x_update_plane;
> - plane->disable_plane = g4x_disable_plane;
> - plane->get_hw_state = g4x_plane_get_hw_state;
> + plane->update_plane = g4x_sprite_update;
> + plane->disable_plane = g4x_sprite_disable;
> + plane->get_hw_state = g4x_sprite_get_hw_state;
> plane->check_plane = g4x_sprite_check;
> plane->max_stride = g4x_sprite_max_stride;
> plane->min_cdclk = g4x_sprite_min_cdclk;
>
> modifiers = i9xx_plane_format_modifiers;
> if (IS_SANDYBRIDGE(dev_priv)) {
> - formats = snb_plane_formats;
> - num_formats = ARRAY_SIZE(snb_plane_formats);
> + formats = snb_sprite_formats;
> + num_formats = ARRAY_SIZE(snb_sprite_formats);
>
> plane_funcs = &snb_sprite_funcs;
> } else {
> - formats = g4x_plane_formats;
> - num_formats = ARRAY_SIZE(g4x_plane_formats);
> + formats = g4x_sprite_formats;
> + num_formats = ARRAY_SIZE(g4x_sprite_formats);
>
> plane_funcs = &g4x_sprite_funcs;
> }
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Intel-gfx] [PATCH v2 6/9] drm/i915: Split pre-skl primary plane update into noarm+arm pair
2021-10-20 21:27 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
@ 2021-11-03 18:49 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 38+ messages in thread
From: Lisovskiy, Stanislav @ 2021-11-03 18:49 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Thu, Oct 21, 2021 at 12:27:57AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Chop i9xx_plane_update() into two halves. Fist half becomes
> the _noarm() variant, second part the _arm() variant.
>
> Fortunately I have already previously grouped the register
> writes into roughtly the correct order, so the split looks
> surprisingly clean.
>
> One slightly surprising fact was that the CHV pipe B PRIMPOS/SIZE
> registers are self arming unlike their pre-ctg DSPPOS/SIZE
> counterparts. In fact all the new CHV pipe B registers are
> self arming.
>
> Also we must remind ourselves that i830/i845 are a bit borked
> in that all of their plane registers are self-arming.
>
> I didn't do any i915_update_info measurements for this one
> alone. I'll get total numbers with the corrsponding sprite
> plane changes.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> v2: Don't break my precious i830/i845
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c | 85 ++++++++++++++++-------
> 1 file changed, 61 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index 93163f9100a8..66aa79abe71c 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -418,32 +418,13 @@ static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
> return DIV_ROUND_UP(pixel_rate * num, den);
> }
>
> -/* TODO: split into noarm+arm pair */
> -static void i9xx_plane_update_arm(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state)
> +static void i9xx_plane_update_noarm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> - u32 linear_offset;
> - int x = plane_state->view.color_plane[0].x;
> - int y = plane_state->view.color_plane[0].y;
> - int crtc_x = plane_state->uapi.dst.x1;
> - int crtc_y = plane_state->uapi.dst.y1;
> - int crtc_w = drm_rect_width(&plane_state->uapi.dst);
> - int crtc_h = drm_rect_height(&plane_state->uapi.dst);
> unsigned long irqflags;
> - u32 dspaddr_offset;
> - u32 dspcntr;
> -
> - dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
> -
> - linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
> -
> - if (DISPLAY_VER(dev_priv) >= 4)
> - dspaddr_offset = plane_state->view.color_plane[0].offset;
> - else
> - dspaddr_offset = linear_offset;
>
> spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>
> @@ -451,6 +432,11 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
> plane_state->view.color_plane[0].stride);
>
> if (DISPLAY_VER(dev_priv) < 4) {
> + int crtc_x = plane_state->uapi.dst.x1;
> + int crtc_y = plane_state->uapi.dst.y1;
> + int crtc_w = drm_rect_width(&plane_state->uapi.dst);
> + int crtc_h = drm_rect_height(&plane_state->uapi.dst);
> +
> /*
> * PLANE_A doesn't actually have a full window
> * generator but let's assume we still need to
> @@ -460,7 +446,39 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
> (crtc_y << 16) | crtc_x);
> intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
> ((crtc_h - 1) << 16) | (crtc_w - 1));
> - } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
> + }
> +
> + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> +}
> +
> +static void i9xx_plane_update_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> + int x = plane_state->view.color_plane[0].x;
> + int y = plane_state->view.color_plane[0].y;
> + u32 dspcntr, dspaddr_offset, linear_offset;
> + unsigned long irqflags;
> +
> + dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
> +
> + linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
> +
> + if (DISPLAY_VER(dev_priv) >= 4)
> + dspaddr_offset = plane_state->view.color_plane[0].offset;
> + else
> + dspaddr_offset = linear_offset;
> +
> + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> +
> + if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
> + int crtc_x = plane_state->uapi.dst.x1;
> + int crtc_y = plane_state->uapi.dst.y1;
> + int crtc_w = drm_rect_width(&plane_state->uapi.dst);
> + int crtc_h = drm_rect_height(&plane_state->uapi.dst);
> +
> intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane),
> (crtc_y << 16) | crtc_x);
> intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane),
> @@ -494,6 +512,20 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
>
> +static void i830_plane_update_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> +{
> + /*
> + * On i830/i845 all registers are self-arming [ALM040].
> + *
> + * Additional breakage on i830 causes register reads to return
> + * the last latched value instead of the last written value [ALM026].
> + */
> + i9xx_plane_update_noarm(plane, crtc_state, plane_state);
> + i9xx_plane_update_arm(plane, crtc_state, plane_state);
> +}
> +
> static void i9xx_plane_disable_arm(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state)
> {
> @@ -852,7 +884,12 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> plane->max_stride = ilk_primary_max_stride;
> }
>
> - plane->update_arm = i9xx_plane_update_arm;
> + if (IS_I830(dev_priv) || IS_I845G(dev_priv)) {
> + plane->update_arm = i830_plane_update_arm;
> + } else {
> + plane->update_noarm = i9xx_plane_update_noarm;
> + plane->update_arm = i9xx_plane_update_arm;
> + }
> plane->disable_arm = i9xx_plane_disable_arm;
> plane->get_hw_state = i9xx_plane_get_hw_state;
> plane->check_plane = i9xx_plane_check;
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 38+ messages in thread
end of thread, other threads:[~2021-11-03 18:49 UTC | newest]
Thread overview: 38+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-18 11:50 [Intel-gfx] [PATCH 0/9] drm/i915: Split plane updates to noarm+arm phases Ville Syrjala
2021-10-18 11:50 ` [Intel-gfx] [PATCH 1/9] drm/i915: Reject planar formats when doing async flips Ville Syrjala
2021-10-27 16:12 ` Lisovskiy, Stanislav
2021-10-18 11:50 ` [Intel-gfx] [PATCH 2/9] drm/i915: Fix async flip with decryption and/or DPT Ville Syrjala
2021-11-03 18:39 ` Lisovskiy, Stanislav
2021-10-18 11:50 ` [Intel-gfx] [PATCH 3/9] drm/i915: Fix up the sprite namespacing Ville Syrjala
2021-11-03 18:47 ` Lisovskiy, Stanislav
2021-10-18 11:50 ` [Intel-gfx] [PATCH 4/9] drm/i915: Split update_plane() into update_noarm() + update_arm() Ville Syrjala
2021-10-27 16:35 ` Lisovskiy, Stanislav
2021-11-03 18:47 ` Lisovskiy, Stanislav
2021-10-18 11:50 ` [Intel-gfx] [PATCH 5/9] drm/i915: Split skl+ plane update into noarm+arm pair Ville Syrjala
2021-10-18 12:06 ` Lisovskiy, Stanislav
2021-10-18 17:14 ` Ville Syrjälä
2021-10-18 17:22 ` Ville Syrjälä
2021-10-27 17:11 ` Lisovskiy, Stanislav
2021-10-28 13:03 ` Ville Syrjälä
2021-10-28 13:54 ` Lisovskiy, Stanislav
2021-10-28 13:59 ` Ville Syrjälä
2021-10-28 14:05 ` Lisovskiy, Stanislav
2021-11-03 18:46 ` Lisovskiy, Stanislav
2021-10-18 11:50 ` [Intel-gfx] [PATCH 6/9] drm/i915: Split pre-skl primary " Ville Syrjala
2021-10-20 21:27 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2021-11-03 18:49 ` Lisovskiy, Stanislav
2021-11-03 18:47 ` [Intel-gfx] [PATCH " Lisovskiy, Stanislav
2021-10-18 11:50 ` [Intel-gfx] [PATCH 7/9] drm/i915: Split g4x+ sprite " Ville Syrjala
2021-11-03 18:46 ` Lisovskiy, Stanislav
2021-10-18 11:50 ` [Intel-gfx] [PATCH 8/9] drm/i915: Split ivb+ " Ville Syrjala
2021-11-03 18:45 ` Lisovskiy, Stanislav
2021-10-18 11:50 ` [Intel-gfx] [PATCH 9/9] drm/i915: Split vlv/chv " Ville Syrjala
2021-11-03 18:44 ` Lisovskiy, Stanislav
2021-10-18 13:06 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Split plane updates to noarm+arm phases Patchwork
2021-10-18 13:08 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-10-18 13:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-18 16:43 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-10-20 22:39 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Split plane updates to noarm+arm phases (rev2) Patchwork
2021-10-20 22:40 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-10-20 23:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-21 3:19 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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