From: Vandita Kulkarni <vandita.kulkarni@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com, imre.deak@intel.com,
matthew.d.roper@intel.com, ville.syrjala@linux.intel.com,
Vandita Kulkarni <vandita.kulkarni@intel.com>
Subject: [Intel-gfx] [V2 4/4] drm/i915/dsi: Ungate clock before enabling the phy
Date: Tue, 19 Oct 2021 20:44:35 +0530 [thread overview]
Message-ID: <20211019151435.20477-5-vandita.kulkarni@intel.com> (raw)
In-Reply-To: <20211019151435.20477-1-vandita.kulkarni@intel.com>
For the PHY enable/disable signalling to propagate
between Dispaly and PHY, DDI clocks need to be running when
enabling the PHY.
Bspec: 49188 says gate the clocks after enabling the
DDI Buffer.
We also have a commit 991d9557b0c4 ("drm/i915/tgl/dsi: Gate the ddi
clocks after pll mapping") which gates the clocks much before,
as per the older spec. This commit nullifies its effect and makes
sure that the clocks are not gated while we enable the DDI
buffer.
v2: Bspec ref, add a comment wrt earlier clock gating sequence (Jani)
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 63dd75c6448a..e5ef5c4a32d7 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1135,8 +1135,6 @@ static void
gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-
/* step 4a: power up all lanes of the DDI used by DSI */
gen11_dsi_power_up_lanes(encoder);
@@ -1146,6 +1144,8 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
/* step 4c: configure voltage swing and skew */
gen11_dsi_voltage_swing_program_seq(encoder);
+ gen11_dsi_ungate_clocks(encoder);
+
/* enable DDI buffer */
gen11_dsi_enable_ddi_buffer(encoder);
@@ -1161,9 +1161,7 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
/* Step (4h, 4i, 4j, 4k): Configure transcoder */
gen11_dsi_configure_transcoder(encoder, crtc_state);
- /* Step 4l: Gate DDI clocks */
- if (DISPLAY_VER(dev_priv) == 11)
- gen11_dsi_gate_clocks(encoder);
+ gen11_dsi_gate_clocks(encoder);
}
static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
--
2.32.0
next prev parent reply other threads:[~2021-10-19 15:14 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-19 15:14 [Intel-gfx] [V2 0/4] Enable MIPI DSI video mode on ADLP Vandita Kulkarni
2021-10-19 15:14 ` [Intel-gfx] [V2 1/4] drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB Vandita Kulkarni
2021-10-19 15:40 ` Jani Nikula
2021-10-19 15:14 ` [Intel-gfx] [V2 2/4] drm/i915/dsi/xelpd: Add DSI transcoder support Vandita Kulkarni
2021-10-19 15:41 ` Jani Nikula
2021-10-19 15:14 ` [Intel-gfx] [V2 3/4] drm/i915/dsi/xelpd: Disable DC states in Video mode Vandita Kulkarni
2021-10-22 20:23 ` Imre Deak
2021-10-28 13:53 ` Kulkarni, Vandita
2021-10-28 15:05 ` Imre Deak
2021-10-19 15:14 ` Vandita Kulkarni [this message]
2021-10-28 11:43 ` [Intel-gfx] [V2 4/4] drm/i915/dsi: Ungate clock before enabling the phy Jani Nikula
2021-10-28 12:58 ` Kulkarni, Vandita
2021-10-28 14:35 ` Jani Nikula
2021-10-28 14:46 ` Kulkarni, Vandita
2021-11-01 12:06 ` Jani Nikula
2021-11-02 6:14 ` Kulkarni, Vandita
2021-11-02 9:42 ` Jani Nikula
2021-11-02 11:42 ` Kulkarni, Vandita
2021-11-09 12:14 ` Kulkarni, Vandita
2021-10-19 18:36 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable MIPI DSI video mode on ADLP (rev2) Patchwork
2021-10-19 19:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-19 23:38 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-10-28 11:33 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable MIPI DSI video mode on ADLP (rev3) Patchwork
2021-10-28 12:03 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-28 16:36 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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