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[123.193.74.252]) by smtp.gmail.com with ESMTPSA id j9sm5963155pgn.24.2021.10.21.09.29.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Oct 2021 09:29:59 -0700 (PDT) From: frank.chang@sifive.com To: qemu-riscv@nongnu.org Cc: Frank Chang Subject: [PATCH v5 0/8] target/riscv: support Zfh, Zfhmin extension v0.1 Date: Fri, 22 Oct 2021 00:29:46 +0800 Message-Id: <20211021162956.2772656-1-frank.chang@sifive.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Oct 2021 16:30:04 -0000 From: Frank Chang Zfh - Half width floating point Zfhmin - Subset of half width floating point Zfh, Zfhmin v0.1 is now in public review period and is required by RVV extension: https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/63gDCinXTwE/m/871Wm9XIBQAJ Zfh, Zfhmin can be enabled with -cpu option: Zfh=true and Zfhmin=true respectively. The port is available at: https://github.com/sifive/qemu/tree/zfh-upstream-v5 Note: This patchset depends on another patchset listed in Based-on section below so it is not able to be built unless the patchset is applied. Changelog: v5: * Rebase on riscv-to-apply.next. v4: * Spilt Zfh, Zfhmin cpu properties related changes into individual patches. v3: * Use the renamed softfloat min/max APIs: *_minimum_number() and *_maximum_number(). * Pick softfloat min/max APIs based on CPU privilege spec version. * Add braces for if statements in REQUIRE_ZFH() and REQUIRE_ZFH_OR_ZFHMIN(). * Rearrange the positions of Zfh and Zfhmin cpu properties. v2: * Use {get,dest}_gpr APIs. * Add Zfhmin extension. Based-on: <20211021160847.2748577-1-frank.chang@sifive.com> Frank Chang (3): target/riscv: zfh: add Zfh cpu property target/riscv: zfh: implement zfhmin extension target/riscv: zfh: add Zfhmin cpu property Kito Cheng (5): target/riscv: zfh: half-precision load and store target/riscv: zfh: half-precision computational target/riscv: zfh: half-precision convert and move target/riscv: zfh: half-precision floating-point compare target/riscv: zfh: half-precision floating-point classify target/riscv/cpu.c | 2 + target/riscv/cpu.h | 2 + target/riscv/fpu_helper.c | 180 ++++++++ target/riscv/helper.h | 29 ++ target/riscv/insn32.decode | 38 ++ target/riscv/insn_trans/trans_rvzfh.c.inc | 537 ++++++++++++++++++++++ target/riscv/internals.h | 16 + target/riscv/translate.c | 20 + 8 files changed, 824 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvzfh.c.inc -- 2.25.1