From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0C7BC433EF for ; Thu, 21 Oct 2021 16:47:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9583660FD8 for ; Thu, 21 Oct 2021 16:47:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232084AbhJUQt5 (ORCPT ); Thu, 21 Oct 2021 12:49:57 -0400 Received: from mail.kernel.org ([198.145.29.99]:51858 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232003AbhJUQtw (ORCPT ); Thu, 21 Oct 2021 12:49:52 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id F17D4610FF; Thu, 21 Oct 2021 16:47:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634834856; bh=2FrlGWhPzbQdm3nWu5dT4nZdmTWgLzYZsWQnLrS6wpQ=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=XHUeCjpKZjFljafYHogeGMUhC+p0v33kG/0Ao7tZdROcacMyp/dR5D03NIhPjpb+k pLhD8ZLK3GCBn00lrJc0v3W5PEi5tM9oInAaLYWnCIjQh6GoWW4roibKKcQNoTiHPT giOIy2bleqD08oaK3gciYJyHesI976Ik8bUfs4WUmTw3Fexwy2GEsy/VIRBgTuaZ7P MEDLdwK30eMcFO5+FSS/YEB3g9G7DQYL2mdltkBbcbb9HBD3/MkfzGoErQLVubadoX Hx8uiATcwnQj+K5dLzBqyX3H3L+E8cK0wrIpvRLYJj3br8ANfuTqq4mFO3KdnNu2vF M8ALpXEqJFCtg== Date: Thu, 21 Oct 2021 17:47:31 +0100 From: Will Deacon To: Mathieu Poirier Cc: Suzuki K Poulose , catalin.marinas@arm.com, anshuman.khandual@arm.com, mike.leach@linaro.org, leo.yan@linaro.org, maz@kernel.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, gregkh@linuxfoundation.org Subject: Re: [PATCH v6 00/15] arm64: Self-hosted trace related errata workarounds Message-ID: <20211021164730.GA16889@willie-the-truck> References: <20211019163153.3692640-1-suzuki.poulose@arm.com> <20211020154207.GA3456574@p14s> <20211021085313.GA15622@willie-the-truck> <20211021163531.GA3561043@p14s> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20211021163531.GA3561043@p14s> User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Mathieu, [CC Greg] On Thu, Oct 21, 2021 at 10:35:31AM -0600, Mathieu Poirier wrote: > On Thu, Oct 21, 2021 at 09:53:14AM +0100, Will Deacon wrote: > > On Wed, Oct 20, 2021 at 09:42:07AM -0600, Mathieu Poirier wrote: > > > On Tue, Oct 19, 2021 at 05:31:38PM +0100, Suzuki K Poulose wrote: > > > > Suzuki K Poulose (15): > > > > arm64: Add Neoverse-N2, Cortex-A710 CPU part definition > > > > arm64: errata: Add detection for TRBE overwrite in FILL mode > > > > arm64: errata: Add workaround for TSB flush failures > > > > arm64: errata: Add detection for TRBE write to out-of-range > > > > coresight: trbe: Add a helper to calculate the trace generated > > > > coresight: trbe: Add a helper to pad a given buffer area > > > > coresight: trbe: Decouple buffer base from the hardware base > > > > coresight: trbe: Allow driver to choose a different alignment > > > > coresight: trbe: Add infrastructure for Errata handling > > > > coresight: trbe: Workaround TRBE errata overwrite in FILL mode > > > > coresight: trbe: Add a helper to determine the minimum buffer size > > > > coresight: trbe: Make sure we have enough space > > > > coresight: trbe: Work around write to out of range > > > > arm64: errata: Enable workaround for TRBE overwrite in FILL mode > > > > arm64: errata: Enable TRBE workaround for write to out-of-range > > > > address > > > > > > > > Documentation/arm64/silicon-errata.rst | 12 + > > > > arch/arm64/Kconfig | 111 ++++++ > > > > arch/arm64/include/asm/barrier.h | 16 +- > > > > arch/arm64/include/asm/cputype.h | 4 + > > > > arch/arm64/kernel/cpu_errata.c | 64 +++ > > > > arch/arm64/tools/cpucaps | 3 + > > > > drivers/hwtracing/coresight/coresight-trbe.c | 394 +++++++++++++++++-- > > > > 7 files changed, 567 insertions(+), 37 deletions(-) > > > > > > I have applied this set. > > > > Mathieu -- the plan here (which we have discussed on the list [1]) is > > for the first four patches to be shared with arm64. Since you've gone > > ahead and applied the whole series, please can you provide me a stable > > branch with the first four patches only so that I can include them in > > the arm64 tree? > > > > Failing that, I can create a branch for you to pull and apply the remaining > > patches on top. > > > > Please let me know. > > Coresight patches flow through Greg's tree and as such the coresight-next tree > gets rebased anyway. I will remove the first 4 patches and push again. By the > way do you also want to pick up patches 14 and 16 since they are concerned with > "arch/arm64/Kconfig" or should I keep them? I'll take the first 4 and put them on a stable branch, which you can choose to pull if you like (but please don't rebase it or we'll end up with duplicate commits). The rest of the patches, including the later Kconfig changes, are yours but I doubt they'll apply cleanly without the initial changes. Are you sure Greg rebases everything? That sounds a bit weird to me, as it means it's impossible to share branches with other trees. How do you usually handle this situation? Will From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6224C433EF for ; Thu, 21 Oct 2021 16:49:11 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 74BBF60FD8 for ; Thu, 21 Oct 2021 16:49:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 74BBF60FD8 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=0E6Ae77unE4XkhrfptcC/E8QQz65H4X7W9YzJbg2toQ=; b=HKee7HS2HRDfRd ecmp1yprXsL7hN4ESaiIMndPYvW6GJ5dymugwkSzOZo7nrJNwJAZvcNNj8UpUd7jW71Pc1qOAmxvd JLKwc037MRrcGFf8n7kOZa/IjuuEgeFiN9KwC7aAgZL3pNfUPQWo+pg43vkihxjnpEt/2VGiGO3V1 E5zDSRcUZmPHz34S3PaQHzpdzCD0zMybImlwomJ654PnXgv/NTDaXXaRyPHTIB1hOZm/zLrbb3Gi4 g+YcUkbye/kDWG+dCaApZ/E3BZ41xGFexqFwmQwdpLY9gVQ/bRPPb14WWjRO5uU+x95I9kMxpywRL XJOkzLH3Wa4+MO3vGzDQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mdbEC-008PiD-Uz; Thu, 21 Oct 2021 16:47:41 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mdbE9-008PhD-7T for linux-arm-kernel@lists.infradead.org; Thu, 21 Oct 2021 16:47:38 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id F17D4610FF; Thu, 21 Oct 2021 16:47:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634834856; bh=2FrlGWhPzbQdm3nWu5dT4nZdmTWgLzYZsWQnLrS6wpQ=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=XHUeCjpKZjFljafYHogeGMUhC+p0v33kG/0Ao7tZdROcacMyp/dR5D03NIhPjpb+k pLhD8ZLK3GCBn00lrJc0v3W5PEi5tM9oInAaLYWnCIjQh6GoWW4roibKKcQNoTiHPT giOIy2bleqD08oaK3gciYJyHesI976Ik8bUfs4WUmTw3Fexwy2GEsy/VIRBgTuaZ7P MEDLdwK30eMcFO5+FSS/YEB3g9G7DQYL2mdltkBbcbb9HBD3/MkfzGoErQLVubadoX Hx8uiATcwnQj+K5dLzBqyX3H3L+E8cK0wrIpvRLYJj3br8ANfuTqq4mFO3KdnNu2vF M8ALpXEqJFCtg== Date: Thu, 21 Oct 2021 17:47:31 +0100 From: Will Deacon To: Mathieu Poirier Cc: Suzuki K Poulose , catalin.marinas@arm.com, anshuman.khandual@arm.com, mike.leach@linaro.org, leo.yan@linaro.org, maz@kernel.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, gregkh@linuxfoundation.org Subject: Re: [PATCH v6 00/15] arm64: Self-hosted trace related errata workarounds Message-ID: <20211021164730.GA16889@willie-the-truck> References: <20211019163153.3692640-1-suzuki.poulose@arm.com> <20211020154207.GA3456574@p14s> <20211021085313.GA15622@willie-the-truck> <20211021163531.GA3561043@p14s> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20211021163531.GA3561043@p14s> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211021_094737_334266_EAEA3B5F X-CRM114-Status: GOOD ( 26.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Mathieu, [CC Greg] On Thu, Oct 21, 2021 at 10:35:31AM -0600, Mathieu Poirier wrote: > On Thu, Oct 21, 2021 at 09:53:14AM +0100, Will Deacon wrote: > > On Wed, Oct 20, 2021 at 09:42:07AM -0600, Mathieu Poirier wrote: > > > On Tue, Oct 19, 2021 at 05:31:38PM +0100, Suzuki K Poulose wrote: > > > > Suzuki K Poulose (15): > > > > arm64: Add Neoverse-N2, Cortex-A710 CPU part definition > > > > arm64: errata: Add detection for TRBE overwrite in FILL mode > > > > arm64: errata: Add workaround for TSB flush failures > > > > arm64: errata: Add detection for TRBE write to out-of-range > > > > coresight: trbe: Add a helper to calculate the trace generated > > > > coresight: trbe: Add a helper to pad a given buffer area > > > > coresight: trbe: Decouple buffer base from the hardware base > > > > coresight: trbe: Allow driver to choose a different alignment > > > > coresight: trbe: Add infrastructure for Errata handling > > > > coresight: trbe: Workaround TRBE errata overwrite in FILL mode > > > > coresight: trbe: Add a helper to determine the minimum buffer size > > > > coresight: trbe: Make sure we have enough space > > > > coresight: trbe: Work around write to out of range > > > > arm64: errata: Enable workaround for TRBE overwrite in FILL mode > > > > arm64: errata: Enable TRBE workaround for write to out-of-range > > > > address > > > > > > > > Documentation/arm64/silicon-errata.rst | 12 + > > > > arch/arm64/Kconfig | 111 ++++++ > > > > arch/arm64/include/asm/barrier.h | 16 +- > > > > arch/arm64/include/asm/cputype.h | 4 + > > > > arch/arm64/kernel/cpu_errata.c | 64 +++ > > > > arch/arm64/tools/cpucaps | 3 + > > > > drivers/hwtracing/coresight/coresight-trbe.c | 394 +++++++++++++++++-- > > > > 7 files changed, 567 insertions(+), 37 deletions(-) > > > > > > I have applied this set. > > > > Mathieu -- the plan here (which we have discussed on the list [1]) is > > for the first four patches to be shared with arm64. Since you've gone > > ahead and applied the whole series, please can you provide me a stable > > branch with the first four patches only so that I can include them in > > the arm64 tree? > > > > Failing that, I can create a branch for you to pull and apply the remaining > > patches on top. > > > > Please let me know. > > Coresight patches flow through Greg's tree and as such the coresight-next tree > gets rebased anyway. I will remove the first 4 patches and push again. By the > way do you also want to pick up patches 14 and 16 since they are concerned with > "arch/arm64/Kconfig" or should I keep them? I'll take the first 4 and put them on a stable branch, which you can choose to pull if you like (but please don't rebase it or we'll end up with duplicate commits). The rest of the patches, including the later Kconfig changes, are yours but I doubt they'll apply cleanly without the initial changes. Are you sure Greg rebases everything? That sounds a bit weird to me, as it means it's impossible to share branches with other trees. How do you usually handle this situation? Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel