From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>
Subject: [PULL 24/33] hw/intc: Remove the Ibex PLIC
Date: Fri, 22 Oct 2021 23:38:03 +1000 [thread overview]
Message-ID: <20211022133812.3972903-25-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20211022133812.3972903-1-alistair.francis@opensource.wdc.com>
From: Alistair Francis <alistair.francis@wdc.com>
The Ibex PLIC is now spec compliant. Let's remove the Ibex PLIC and
instead use the SiFive PLIC.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 5557935c2660c5e6281b6d21e6514e019593662e.1634524691.git.alistair.francis@wdc.com
---
hw/intc/ibex_plic.c | 307 --------------------------------------------
hw/intc/meson.build | 1 -
2 files changed, 308 deletions(-)
delete mode 100644 hw/intc/ibex_plic.c
diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
deleted file mode 100644
index ff430356f8..0000000000
--- a/hw/intc/ibex_plic.c
+++ /dev/null
@@ -1,307 +0,0 @@
-/*
- * QEMU RISC-V lowRISC Ibex PLIC
- *
- * Copyright (c) 2020 Western Digital
- *
- * Documentation avaliable: https://docs.opentitan.org/hw/ip/rv_plic/doc/
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include "qemu/osdep.h"
-#include "qemu/log.h"
-#include "hw/qdev-properties.h"
-#include "hw/core/cpu.h"
-#include "hw/boards.h"
-#include "hw/pci/msi.h"
-#include "target/riscv/cpu_bits.h"
-#include "target/riscv/cpu.h"
-#include "hw/intc/ibex_plic.h"
-#include "hw/irq.h"
-
-static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
-{
- uint32_t end = base + (num * 0x04);
-
- if (addr >= base && addr < end) {
- return true;
- }
-
- return false;
-}
-
-static void ibex_plic_irqs_set_pending(IbexPlicState *s, int irq, bool level)
-{
- int pending_num = irq / 32;
-
- if (!level) {
- /*
- * If the level is low make sure we clear the hidden_pending.
- */
- s->hidden_pending[pending_num] &= ~(1 << (irq % 32));
- }
-
- if (s->claimed[pending_num] & 1 << (irq % 32)) {
- /*
- * The interrupt has been claimed, but not completed.
- * The pending bit can't be set.
- * Save the pending level for after the interrupt is completed.
- */
- s->hidden_pending[pending_num] |= level << (irq % 32);
- } else {
- s->pending[pending_num] |= level << (irq % 32);
- }
-}
-
-static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context)
-{
- int i;
- uint32_t max_irq = 0;
- uint32_t max_prio = s->threshold;
-
- for (i = 0; i < s->pending_num; i++) {
- uint32_t irq_num = ctz64(s->pending[i]) + (i * 32);
-
- if (!(s->pending[i] & s->enable[i])) {
- /* No pending and enabled IRQ */
- continue;
- }
-
- if (s->priority[irq_num] > max_prio) {
- max_irq = irq_num;
- max_prio = s->priority[irq_num];
- }
- }
-
- if (max_irq) {
- s->claim = max_irq;
- return true;
- }
-
- return false;
-}
-
-static void ibex_plic_update(IbexPlicState *s)
-{
- int i;
-
- for (i = 0; i < s->num_cpus; i++) {
- qemu_set_irq(s->external_irqs[i], ibex_plic_irqs_pending(s, 0));
- }
-}
-
-static void ibex_plic_reset(DeviceState *dev)
-{
- IbexPlicState *s = IBEX_PLIC(dev);
-
- s->threshold = 0x00000000;
- s->claim = 0x00000000;
-}
-
-static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
- unsigned int size)
-{
- IbexPlicState *s = opaque;
- int offset;
- uint32_t ret = 0;
-
- if (addr_between(addr, s->pending_base, s->pending_num)) {
- offset = (addr - s->pending_base) / 4;
- ret = s->pending[offset];
- } else if (addr_between(addr, s->source_base, s->source_num)) {
- qemu_log_mask(LOG_UNIMP,
- "%s: Interrupt source mode not supported\n", __func__);
- } else if (addr_between(addr, s->priority_base, s->priority_num)) {
- offset = (addr - s->priority_base) / 4;
- ret = s->priority[offset];
- } else if (addr_between(addr, s->enable_base, s->enable_num)) {
- offset = (addr - s->enable_base) / 4;
- ret = s->enable[offset];
- } else if (addr_between(addr, s->threshold_base, 1)) {
- ret = s->threshold;
- } else if (addr_between(addr, s->claim_base, 1)) {
- int pending_num = s->claim / 32;
- s->pending[pending_num] &= ~(1 << (s->claim % 32));
-
- /* Set the interrupt as claimed, but not completed */
- s->claimed[pending_num] |= 1 << (s->claim % 32);
-
- /* Return the current claimed interrupt */
- ret = s->claim;
-
- /* Clear the claimed interrupt */
- s->claim = 0x00000000;
-
- /* Update the interrupt status after the claim */
- ibex_plic_update(s);
- }
-
- return ret;
-}
-
-static void ibex_plic_write(void *opaque, hwaddr addr,
- uint64_t value, unsigned int size)
-{
- IbexPlicState *s = opaque;
-
- if (addr_between(addr, s->pending_base, s->pending_num)) {
- qemu_log_mask(LOG_GUEST_ERROR,
- "%s: Pending registers are read only\n", __func__);
- } else if (addr_between(addr, s->source_base, s->source_num)) {
- qemu_log_mask(LOG_UNIMP,
- "%s: Interrupt source mode not supported\n", __func__);
- } else if (addr_between(addr, s->priority_base, s->priority_num)) {
- uint32_t irq = ((addr - s->priority_base) >> 2) + 1;
- s->priority[irq] = value & 7;
- ibex_plic_update(s);
- } else if (addr_between(addr, s->enable_base, s->enable_num)) {
- uint32_t enable_reg = (addr - s->enable_base) / 4;
-
- s->enable[enable_reg] = value;
- } else if (addr_between(addr, s->threshold_base, 1)) {
- s->threshold = value & 3;
- } else if (addr_between(addr, s->claim_base, 1)) {
- if (s->claim == value) {
- /* Interrupt was completed */
- s->claim = 0;
- }
- if (s->claimed[value / 32] & 1 << (value % 32)) {
- int pending_num = value / 32;
-
- /* This value was already claimed, clear it. */
- s->claimed[pending_num] &= ~(1 << (value % 32));
-
- if (s->hidden_pending[pending_num] & (1 << (value % 32))) {
- /*
- * If the bit in hidden_pending is set then that means we
- * received an interrupt between claiming and completing
- * the interrupt that hasn't since been de-asserted.
- * On hardware this would trigger an interrupt, so let's
- * trigger one here as well.
- */
- s->pending[pending_num] |= 1 << (value % 32);
- }
- }
- }
-
- ibex_plic_update(s);
-}
-
-static const MemoryRegionOps ibex_plic_ops = {
- .read = ibex_plic_read,
- .write = ibex_plic_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
- .valid = {
- .min_access_size = 4,
- .max_access_size = 4
- }
-};
-
-static void ibex_plic_irq_request(void *opaque, int irq, int level)
-{
- IbexPlicState *s = opaque;
-
- ibex_plic_irqs_set_pending(s, irq, level > 0);
- ibex_plic_update(s);
-}
-
-static Property ibex_plic_properties[] = {
- DEFINE_PROP_UINT32("num-cpus", IbexPlicState, num_cpus, 1),
- DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 176),
-
- DEFINE_PROP_UINT32("pending-base", IbexPlicState, pending_base, 0),
- DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 6),
-
- DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x18),
- DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 6),
-
- DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x30),
- DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 177),
-
- DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x300),
- DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 6),
-
- DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x318),
-
- DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x31c),
- DEFINE_PROP_END_OF_LIST(),
-};
-
-static void ibex_plic_init(Object *obj)
-{
- IbexPlicState *s = IBEX_PLIC(obj);
-
- memory_region_init_io(&s->mmio, obj, &ibex_plic_ops, s,
- TYPE_IBEX_PLIC, 0x400);
- sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
-}
-
-static void ibex_plic_realize(DeviceState *dev, Error **errp)
-{
- IbexPlicState *s = IBEX_PLIC(dev);
- int i;
-
- s->pending = g_new0(uint32_t, s->pending_num);
- s->hidden_pending = g_new0(uint32_t, s->pending_num);
- s->claimed = g_new0(uint32_t, s->pending_num);
- s->source = g_new0(uint32_t, s->source_num);
- s->priority = g_new0(uint32_t, s->priority_num);
- s->enable = g_new0(uint32_t, s->enable_num);
-
- qdev_init_gpio_in(dev, ibex_plic_irq_request, s->num_sources);
-
- s->external_irqs = g_malloc(sizeof(qemu_irq) * s->num_cpus);
- qdev_init_gpio_out(dev, s->external_irqs, s->num_cpus);
-
- /*
- * We can't allow the supervisor to control SEIP as this would allow the
- * supervisor to clear a pending external interrupt which will result in
- * a lost interrupt in the case a PLIC is attached. The SEIP bit must be
- * hardware controlled when a PLIC is attached.
- */
- MachineState *ms = MACHINE(qdev_get_machine());
- unsigned int smp_cpus = ms->smp.cpus;
- for (i = 0; i < smp_cpus; i++) {
- RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(i));
- if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
- error_report("SEIP already claimed");
- exit(1);
- }
- }
-
- msi_nonbroken = true;
-}
-
-static void ibex_plic_class_init(ObjectClass *klass, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(klass);
-
- dc->reset = ibex_plic_reset;
- device_class_set_props(dc, ibex_plic_properties);
- dc->realize = ibex_plic_realize;
-}
-
-static const TypeInfo ibex_plic_info = {
- .name = TYPE_IBEX_PLIC,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(IbexPlicState),
- .instance_init = ibex_plic_init,
- .class_init = ibex_plic_class_init,
-};
-
-static void ibex_plic_register_types(void)
-{
- type_register_static(&ibex_plic_info);
-}
-
-type_init(ibex_plic_register_types)
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index a1d00aa48d..c89d2ca180 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -32,7 +32,6 @@ specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c'))
specific_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_vic.c'))
specific_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_gic.c', 'exynos4210_combiner.c'))
specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_irqmp.c'))
-specific_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_plic.c'))
specific_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic.c'))
specific_ss.add(when: 'CONFIG_LOONGSON_LIOINTC', if_true: files('loongson_liointc.c'))
specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_gic.c'))
--
2.31.1
next prev parent reply other threads:[~2021-10-22 13:56 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-22 13:37 [PULL 00/33] riscv-to-apply queue Alistair Francis
2021-10-22 13:37 ` [PULL 01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v Alistair Francis
2021-10-22 13:37 ` [PULL 02/33] target/riscv: line up all of the registers in the info register dump Alistair Francis
2021-10-22 13:37 ` [PULL 03/33] target/riscv: Fix orc.b implementation Alistair Francis
2021-10-22 13:37 ` [PULL 04/33] hw/riscv: virt: Use machine->ram as the system memory Alistair Francis
2021-10-22 13:37 ` [PULL 05/33] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh Alistair Francis
2021-10-22 13:37 ` [PULL 06/33] target/riscv: Remove some unused macros Alistair Francis
2021-10-22 13:37 ` [PULL 07/33] target/riscv: Organise the CPU properties Alistair Francis
2021-10-22 13:37 ` [PULL 08/33] target/riscv: Move cpu_get_tb_cpu_state out of line Alistair Francis
2021-10-22 13:37 ` [PULL 09/33] target/riscv: Create RISCVMXL enumeration Alistair Francis
2021-10-22 13:37 ` [PULL 10/33] target/riscv: Split misa.mxl and misa.ext Alistair Francis
2021-10-22 13:37 ` [PULL 11/33] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Alistair Francis
2021-10-22 13:37 ` [PULL 12/33] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Alistair Francis
2021-10-22 13:37 ` [PULL 13/33] target/riscv: Use REQUIRE_64BIT in amo_check64 Alistair Francis
2021-10-22 13:37 ` [PULL 14/33] target/riscv: Properly check SEW in amo_op Alistair Francis
2021-10-22 13:37 ` [PULL 15/33] target/riscv: Replace is_32bit with get_xl/get_xlen Alistair Francis
2021-10-22 13:37 ` [PULL 16/33] target/riscv: Replace DisasContext.w with DisasContext.ol Alistair Francis
2021-10-22 13:37 ` [PULL 17/33] target/riscv: Use gen_arith_per_ol for RVM Alistair Francis
2021-10-22 13:37 ` [PULL 18/33] target/riscv: Adjust trans_rev8_32 for riscv64 Alistair Francis
2021-10-22 13:37 ` [PULL 19/33] target/riscv: Use gen_unary_per_ol for RVB Alistair Francis
2021-10-22 13:37 ` [PULL 20/33] target/riscv: Use gen_shift*_per_ol for RVB, RVI Alistair Francis
2021-10-22 13:38 ` [PULL 21/33] target/riscv: Use riscv_csrrw_debug for cpu_dump Alistair Francis
2021-10-22 13:38 ` [PULL 22/33] target/riscv: Compute mstatus.sd on demand Alistair Francis
2021-10-22 13:38 ` [PULL 23/33] hw/riscv: opentitan: Update to the latest build Alistair Francis
2021-10-22 13:38 ` Alistair Francis [this message]
2021-10-22 13:38 ` [PULL 25/33] hw/intc: sifive_plic: Move the properties Alistair Francis
2021-10-22 13:38 ` [PULL 26/33] hw/intc: sifive_plic: Cleanup the realize function Alistair Francis
2021-10-22 13:38 ` [PULL 27/33] hw/intc: sifive_plic: Cleanup the irq_request function Alistair Francis
2021-10-22 13:38 ` [PULL 28/33] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id Alistair Francis
2021-10-22 13:38 ` [PULL 29/33] hw/riscv: opentitan: " Alistair Francis
2021-10-22 13:38 ` [PULL 30/33] hw/riscv: shakti_c: " Alistair Francis
2021-10-22 13:38 ` [PULL 31/33] hw/riscv: sifive_e: " Alistair Francis
2021-10-22 13:38 ` [PULL 32/33] hw/riscv: sifive_u: " Alistair Francis
2021-10-22 13:38 ` [PULL 33/33] hw/riscv: spike: " Alistair Francis
2021-10-22 21:39 ` [PULL 00/33] riscv-to-apply queue Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211022133812.3972903-25-alistair.francis@opensource.wdc.com \
--to=alistair.francis@opensource.wdc.com \
--cc=alistair.francis@wdc.com \
--cc=alistair23@gmail.com \
--cc=bmeng.cn@gmail.com \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.