From: Luo Jie <luoj@codeaurora.org>
To: andrew@lunn.ch, hkallweit1@gmail.com, linux@armlinux.org.uk,
davem@davemloft.net, kuba@kernel.org
Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
sricharan@codeaurora.org, Luo Jie <luoj@codeaurora.org>
Subject: [PATCH v7 03/14] net: phy: at803x: improve the WOL feature
Date: Sun, 24 Oct 2021 16:27:27 +0800 [thread overview]
Message-ID: <20211024082738.849-4-luoj@codeaurora.org> (raw)
In-Reply-To: <20211024082738.849-1-luoj@codeaurora.org>
The wol feature is controlled by the MMD3.8012 bit5,
need to set this bit when the wol function is enabled.
The reg18 bit0 is for enabling WOL interrupt, when wol
occurs, the wol interrupt status reg19 bit0 is set to 1.
Call phy_trigger_machine if there are any other interrupt
pending in the function set_wol.
Signed-off-by: Luo Jie <luoj@codeaurora.org>
---
drivers/net/phy/at803x.c | 45 +++++++++++++++++++++++++++++++++-------
1 file changed, 38 insertions(+), 7 deletions(-)
diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
index cf25cd428ffa..1363f12ba659 100644
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -70,6 +70,8 @@
#define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0)
#define AT803X_LED_CONTROL 0x18
+#define AT803X_PHY_MMD3_WOL_CTRL 0x8012
+#define AT803X_WOL_EN BIT(5)
#define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C
#define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B
#define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A
@@ -335,8 +337,7 @@ static int at803x_set_wol(struct phy_device *phydev,
{
struct net_device *ndev = phydev->attached_dev;
const u8 *mac;
- int ret;
- u32 value;
+ int ret, irq_enabled;
unsigned int i;
const unsigned int offsets[] = {
AT803X_LOC_MAC_ADDR_32_47_OFFSET,
@@ -357,18 +358,45 @@ static int at803x_set_wol(struct phy_device *phydev,
phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i],
mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
+ /* Enable WOL function */
+ ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL,
+ 0, AT803X_WOL_EN);
+ if (ret)
+ return ret;
+ /* Enable WOL interrupt */
ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL);
if (ret)
return ret;
- value = phy_read(phydev, AT803X_INTR_STATUS);
} else {
+ /* Disable WoL function */
+ ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL,
+ AT803X_WOL_EN, 0);
+ if (ret)
+ return ret;
+ /* Disable WOL interrupt */
ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0);
if (ret)
return ret;
- value = phy_read(phydev, AT803X_INTR_STATUS);
}
- return ret;
+ /* Clear WOL status */
+ ret = phy_read(phydev, AT803X_INTR_STATUS);
+ if (ret < 0)
+ return ret;
+
+ /* Check if there are other interrupts except for WOL triggered when PHY is
+ * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can
+ * be passed up to the interrupt PIN.
+ */
+ irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
+ if (irq_enabled < 0)
+ return irq_enabled;
+
+ irq_enabled &= ~AT803X_INTR_ENABLE_WOL;
+ if (ret & irq_enabled && !phy_polling_mode(phydev))
+ phy_trigger_machine(phydev);
+
+ return 0;
}
static void at803x_get_wol(struct phy_device *phydev,
@@ -379,8 +407,11 @@ static void at803x_get_wol(struct phy_device *phydev,
wol->supported = WAKE_MAGIC;
wol->wolopts = 0;
- value = phy_read(phydev, AT803X_INTR_ENABLE);
- if (value & AT803X_INTR_ENABLE_WOL)
+ value = phy_read_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL);
+ if (value < 0)
+ return;
+
+ if (value & AT803X_WOL_EN)
wol->wolopts |= WAKE_MAGIC;
}
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2021-10-24 8:28 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-24 8:27 [PATCH v7 0/14] net: phy: Add qca8081 ethernet phy driver Luo Jie
2021-10-24 8:27 ` [PATCH v7 01/14] net: phy: at803x: replace AT803X_DEVICE_ADDR with MDIO_MMD_PCS Luo Jie
2021-10-24 8:27 ` [PATCH v7 02/14] net: phy: at803x: use phy_modify() Luo Jie
2021-10-24 8:27 ` Luo Jie [this message]
2021-10-24 18:29 ` [PATCH v7 03/14] net: phy: at803x: improve the WOL feature Andrew Lunn
2021-10-24 8:27 ` [PATCH v7 04/14] net: phy: at803x: use GENMASK() for speed status Luo Jie
2021-10-24 8:27 ` [PATCH v7 05/14] net: phy: add qca8081 ethernet phy driver Luo Jie
2021-10-24 18:29 ` Andrew Lunn
2021-10-24 8:27 ` [PATCH v7 06/14] net: phy: add qca8081 read_status Luo Jie
2021-10-24 18:30 ` Andrew Lunn
2021-10-24 8:27 ` [PATCH v7 07/14] net: phy: add qca8081 get_features Luo Jie
2021-10-24 18:31 ` Andrew Lunn
2021-10-24 8:27 ` [PATCH v7 08/14] net: phy: add qca8081 config_aneg Luo Jie
2021-10-24 18:31 ` Andrew Lunn
2021-10-24 8:27 ` [PATCH v7 09/14] net: phy: add constants for fast retrain related register Luo Jie
2021-10-24 18:32 ` Andrew Lunn
2021-10-24 8:27 ` [PATCH v7 10/14] net: phy: add genphy_c45_fast_retrain Luo Jie
2021-10-24 18:33 ` Andrew Lunn
2021-10-24 8:27 ` [PATCH v7 11/14] net: phy: add qca8081 config_init Luo Jie
2021-10-24 18:34 ` Andrew Lunn
2021-10-24 8:27 ` [PATCH v7 12/14] net: phy: add qca8081 soft_reset and enable master/slave seed Luo Jie
2021-10-24 18:40 ` Andrew Lunn
2021-10-24 8:27 ` [PATCH v7 13/14] net: phy: adjust qca8081 master/slave seed value if link down Luo Jie
2021-10-24 18:41 ` Andrew Lunn
2021-10-24 8:27 ` [PATCH v7 14/14] net: phy: add qca8081 cdt feature Luo Jie
2021-10-24 18:43 ` Andrew Lunn
2021-10-25 13:10 ` [PATCH v7 0/14] net: phy: Add qca8081 ethernet phy driver patchwork-bot+netdevbpf
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