From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9CA75C433EF for ; Mon, 25 Oct 2021 06:35:03 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AB0B160E09 for ; Mon, 25 Oct 2021 06:35:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org AB0B160E09 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 68BC9834B9; Mon, 25 Oct 2021 08:35:00 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 4289083521; Mon, 25 Oct 2021 08:34:50 +0200 (CEST) Received: from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 5B99782DC3 for ; Mon, 25 Oct 2021 08:34:44 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=nico.cheng@rock-chips.com Received: from localhost (unknown [192.168.167.225]) by lucky1.263xmail.com (Postfix) with ESMTP id 6E6DED72CF; Mon, 25 Oct 2021 14:34:41 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED: 0 X-SKE-CHECKED: 1 X-ANTISPAM-LEVEL: 2 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P23220T140409479288576S1635143633744474_; Mon, 25 Oct 2021 14:34:40 +0800 (CST) X-IP-DOMAINF: 1 X-RL-SENDER: nico.cheng@rock-chips.com X-SENDER: nico.cheng@rock-chips.com X-LOGIN-NAME: nico.cheng@rock-chips.com X-FST-TO: sjg@chromium.org X-RCPT-COUNT: 10 X-LOCAL-RCPT-COUNT: 5 X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-UNIQUE-TAG: <24ec9257bf9dd8a953e2081de26211a9> X-System-Flag: 0 From: Nico Cheng To: sjg@chromium.org, philipp.tomsich@vrull.eu, kever.yang@rock-chips.com Cc: yamada.masahiro@socionext.com, chenjh@rock-chips.com, jason.zhu@rock-chips.com, trini@konsulko.com, yifeng.zhao@rock-chips.com, nico.cheng@rock-chips.com, u-boot@lists.denx.de Subject: [PATCH v2 3/3] rockchip: rk3568: add arch_cpu_init() Date: Mon, 25 Oct 2021 14:33:43 +0800 Message-Id: <20211025141454.v2.3.Ib0d964f78ba35e91a4bef91d322101768d9fcfbf@changeid> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211025063343.29494-1-nico.cheng@rock-chips.com> References: <20211025063343.29494-1-nico.cheng@rock-chips.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean We configured the drive strength and security of EMMC in arch_cpu_init(). Signed-off-by: Nico Cheng --- Changes in v2: We use the rk_clrreg function instead of the writel to set eMMC sdmmc0 to secure. Modify comments to make them more explicit. arch/arm/mach-rockchip/rk3568/rk3568.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c index 973b4f9dcb..1a62052731 100644 --- a/arch/arm/mach-rockchip/rk3568/rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -13,6 +13,14 @@ #define PMUGRF_BASE 0xfdc20000 #define GRF_BASE 0xfdc60000 +#define GRF_GPIO1B_DS_2 0x218 +#define GRF_GPIO1B_DS_3 0x21c +#define GRF_GPIO1C_DS_0 0x220 +#define GRF_GPIO1C_DS_1 0x224 +#define GRF_GPIO1C_DS_2 0x228 +#define GRF_GPIO1C_DS_3 0x22c +#define SGRF_BASE 0xFDD18000 +#define SGRF_SOC_CON4 0x10 /* PMU_GRF_GPIO0D_IOMUX_L */ enum { @@ -81,5 +89,16 @@ void board_debug_uart_init(void) int arch_cpu_init(void) { +#ifdef CONFIG_SPL_BUILD + /* Set the emmc sdmmc0 to secure */ + rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (0x3 << 11 | 0x1 << 4)); + /* set the emmc driver strength to level 2 */ + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_2); + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_3); + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_0); + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1); + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2); + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3); +#endif return 0; } -- 2.17.1