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From: Nico Cheng <nico.cheng@rock-chips.com>
To: sjg@chromium.org, philipp.tomsich@vrull.eu, kever.yang@rock-chips.com
Cc: yamada.masahiro@socionext.com, chenjh@rock-chips.com,
	jason.zhu@rock-chips.com, trini@konsulko.com,
	yifeng.zhao@rock-chips.com, nico.cheng@rock-chips.com,
	u-boot@lists.denx.de
Subject: [PATCH v3 3/3] rockchip: rk3568: add arch_cpu_init()
Date: Tue, 26 Oct 2021 10:42:21 +0800	[thread overview]
Message-ID: <20211026103650.v3.3.Ib0d964f78ba35e91a4bef91d322101768d9fcfbf@changeid> (raw)
In-Reply-To: <20211026024221.5208-1-nico.cheng@rock-chips.com>

We configured the drive strength and security of EMMC in
arch_cpu_init().

Signed-off-by: Nico Cheng <nico.cheng@rock-chips.com>
---

Changes in v3:
Replace configuration parameters of SGRF_SOC_CON4 with macro
definitions.

Changes in v2:
We use the rk_clrreg function instead of the writel to set eMMC sdmmc0 to
secure.
Modify comments to make them more explicit.

 arch/arm/mach-rockchip/rk3568/rk3568.c | 27 +++++++++++++++++++++++---
 1 file changed, 24 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c
index 973b4f9dcb..22eeb77d41 100644
--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -11,9 +11,18 @@
 #include <asm/arch-rockchip/hardware.h>
 #include <dt-bindings/clock/rk3568-cru.h>
 
-#define PMUGRF_BASE		0xfdc20000
-#define GRF_BASE		0xfdc60000
-
+#define PMUGRF_BASE			0xfdc20000
+#define GRF_BASE			0xfdc60000
+#define GRF_GPIO1B_DS_2			0x218
+#define GRF_GPIO1B_DS_3			0x21c
+#define GRF_GPIO1C_DS_0			0x220
+#define GRF_GPIO1C_DS_1			0x224
+#define GRF_GPIO1C_DS_2			0x228
+#define GRF_GPIO1C_DS_3			0x22c
+#define SGRF_BASE			0xFDD18000
+#define SGRF_SOC_CON4			0x10
+#define EMMC_HPROT_SECURE_CTRL		0x03
+#define SDMMC0_HPROT_SECURE_CTRL	0x01
 /* PMU_GRF_GPIO0D_IOMUX_L */
 enum {
 	GPIO0D1_SHIFT		= 4,
@@ -81,5 +90,17 @@ void board_debug_uart_init(void)
 
 int arch_cpu_init(void)
 {
+#ifdef CONFIG_SPL_BUILD
+	/* Set the emmc sdmmc0 to secure */
+	rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (EMMC_HPROT_SECURE_CTRL << 11
+		| SDMMC0_HPROT_SECURE_CTRL << 4));
+	/* set the emmc driver strength to level 2 */
+	writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_2);
+	writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_3);
+	writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_0);
+	writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1);
+	writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
+	writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
+#endif
 	return 0;
 }
-- 
2.17.1




  parent reply	other threads:[~2021-10-26  2:43 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-26  2:42 [PATCH v3 0/3] Add SPL build support for RK3568 Nico Cheng
2021-10-26  2:42 ` [PATCH v3 1/3] rockchip: Kconfig: Enable SPL support for rk3568 Nico Cheng
2021-12-24  3:04   ` Kever Yang
2022-03-11 19:34   ` Jagan Teki
2021-10-26  2:42 ` [PATCH v3 2/3] arm: dts: rockchip: rk3568: Enable sdhci and sdmmc0 node Nico Cheng
2021-12-24  3:04   ` Kever Yang
2021-10-26  2:42 ` Nico Cheng [this message]
2021-12-24  3:04   ` [PATCH v3 3/3] rockchip: rk3568: add arch_cpu_init() Kever Yang
2021-10-26  8:09 ` [PATCH v3 0/3] Add SPL build support for RK3568 Peter Robinson
2021-10-26 11:24   ` nico.cheng
2021-10-26 13:20   ` Kever Yang

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