From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EA8BC433FE for ; Wed, 27 Oct 2021 07:13:55 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5B30E6109E for ; Wed, 27 Oct 2021 07:13:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 5B30E6109E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 666AB6E542; Wed, 27 Oct 2021 07:13:54 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7EE366E4AB; Wed, 27 Oct 2021 07:13:52 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10149"; a="230365327" X-IronPort-AV: E=Sophos;i="5.87,186,1631602800"; d="scan'208";a="230365327" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2021 00:13:47 -0700 X-IronPort-AV: E=Sophos;i="5.87,186,1631602800"; d="scan'208";a="447426017" Received: from dzhang-mobl2.amr.corp.intel.com (HELO ldmartin-desk2) ([10.251.142.134]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2021 00:13:46 -0700 Date: Wed, 27 Oct 2021 00:13:43 -0700 From: Lucas De Marchi To: Matt Roper Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Paulo Zanoni , Stuart Summers , Tvrtko Ursulin Subject: Re: [PATCH 07/11] drm/i915/xehp: Determine which tile raised an interrupt Message-ID: <20211027071343.s4rrp2v3kfnfj3sl@ldmartin-desk2> X-Patchwork-Hint: comment References: <20211008215635.2026385-1-matthew.d.roper@intel.com> <20211008215635.2026385-8-matthew.d.roper@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: <20211008215635.2026385-8-matthew.d.roper@intel.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Fri, Oct 08, 2021 at 02:56:31PM -0700, Matt Roper wrote: >From: Paulo Zanoni > >The first step of interrupt handling is to read a tile0 register that >tells us in which tile the interrupt happened; we can then we read the >usual interrupt registers from the appropriate tile. > >Note that this is just the first step of handling interrupts properly on >multi-tile platforms. Subsequent patches will convert other parts of >the interrupt handling flow. > >Cc: Stuart Summers >Signed-off-by: Paulo Zanoni >Signed-off-by: Tvrtko Ursulin >Signed-off-by: Matt Roper >--- > drivers/gpu/drm/i915/i915_irq.c | 31 ++++++++++++++++--------------- > 1 file changed, 16 insertions(+), 15 deletions(-) > >diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c >index 038a9ec563c1..9f99ad56cde6 100644 >--- a/drivers/gpu/drm/i915/i915_irq.c >+++ b/drivers/gpu/drm/i915/i915_irq.c >@@ -2772,37 +2772,38 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg) > { > struct drm_i915_private * const i915 = arg; > struct intel_gt *gt = &i915->gt; >- void __iomem * const regs = gt->uncore->regs; >+ void __iomem * const t0_regs = gt->uncore->regs; given that we later make gt point elsewhere since it's now only used inside the loop, I think this would be clearer with void __iomem * const t0_regs = i915->gt->uncore->regs; struct intel_gt *gt; but see below > u32 master_tile_ctl, master_ctl; >- u32 gu_misc_iir; >+ u32 gu_misc_iir = 0; >+ unsigned int i; > > if (!intel_irqs_enabled(i915)) > return IRQ_NONE; > >- master_tile_ctl = dg1_master_intr_disable(regs); >+ master_tile_ctl = dg1_master_intr_disable(t0_regs); > if (!master_tile_ctl) { >- dg1_master_intr_enable(regs); >+ dg1_master_intr_enable(t0_regs); > return IRQ_NONE; > } > >- /* FIXME: we only support tile 0 for now. */ >- if (master_tile_ctl & DG1_MSTR_TILE(0)) { >+ for_each_gt(i915, i, gt) { >+ void __iomem *const regs = gt->uncore->regs; >+ >+ if ((master_tile_ctl & DG1_MSTR_TILE(i)) == 0) >+ continue; >+ > master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ); > raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, master_ctl); >- } else { >- DRM_ERROR("Tile not supported: 0x%08x\n", master_tile_ctl); >- dg1_master_intr_enable(regs); >- return IRQ_NONE; >- } > >- gen11_gt_irq_handler(gt, master_ctl); >+ gen11_gt_irq_handler(gt, master_ctl); >+ >+ gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl); >+ } > > if (master_ctl & GEN11_DISPLAY_IRQ) > gen11_display_irq_handler(i915); > >- gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl); >- >- dg1_master_intr_enable(regs); >+ dg1_master_intr_enable(t0_regs); > > gen11_gu_misc_irq_handler(gt, gu_misc_iir); since we used gt in the for_each_gt() loop it looks like this is not the gt we wanted anymore. Alas gen11_gu_misc_irq_handler() only uses gt to backpoint to i915... so I'm not sure if it should actually be taking a gt as parameter if it is per device rather than per tile/gt. Lucas De Marchi > >-- >2.33.0 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45C35C433EF for ; Wed, 27 Oct 2021 07:13:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 107CB6109E for ; Wed, 27 Oct 2021 07:13:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 107CB6109E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 862606E4AB; Wed, 27 Oct 2021 07:13:53 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7EE366E4AB; Wed, 27 Oct 2021 07:13:52 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10149"; a="230365327" X-IronPort-AV: E=Sophos;i="5.87,186,1631602800"; d="scan'208";a="230365327" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2021 00:13:47 -0700 X-IronPort-AV: E=Sophos;i="5.87,186,1631602800"; d="scan'208";a="447426017" Received: from dzhang-mobl2.amr.corp.intel.com (HELO ldmartin-desk2) ([10.251.142.134]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2021 00:13:46 -0700 Date: Wed, 27 Oct 2021 00:13:43 -0700 From: Lucas De Marchi To: Matt Roper Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Paulo Zanoni , Stuart Summers , Tvrtko Ursulin Message-ID: <20211027071343.s4rrp2v3kfnfj3sl@ldmartin-desk2> X-Patchwork-Hint: comment References: <20211008215635.2026385-1-matthew.d.roper@intel.com> <20211008215635.2026385-8-matthew.d.roper@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: <20211008215635.2026385-8-matthew.d.roper@intel.com> Subject: Re: [Intel-gfx] [PATCH 07/11] drm/i915/xehp: Determine which tile raised an interrupt X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, Oct 08, 2021 at 02:56:31PM -0700, Matt Roper wrote: >From: Paulo Zanoni > >The first step of interrupt handling is to read a tile0 register that >tells us in which tile the interrupt happened; we can then we read the >usual interrupt registers from the appropriate tile. > >Note that this is just the first step of handling interrupts properly on >multi-tile platforms. Subsequent patches will convert other parts of >the interrupt handling flow. > >Cc: Stuart Summers >Signed-off-by: Paulo Zanoni >Signed-off-by: Tvrtko Ursulin >Signed-off-by: Matt Roper >--- > drivers/gpu/drm/i915/i915_irq.c | 31 ++++++++++++++++--------------- > 1 file changed, 16 insertions(+), 15 deletions(-) > >diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c >index 038a9ec563c1..9f99ad56cde6 100644 >--- a/drivers/gpu/drm/i915/i915_irq.c >+++ b/drivers/gpu/drm/i915/i915_irq.c >@@ -2772,37 +2772,38 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg) > { > struct drm_i915_private * const i915 = arg; > struct intel_gt *gt = &i915->gt; >- void __iomem * const regs = gt->uncore->regs; >+ void __iomem * const t0_regs = gt->uncore->regs; given that we later make gt point elsewhere since it's now only used inside the loop, I think this would be clearer with void __iomem * const t0_regs = i915->gt->uncore->regs; struct intel_gt *gt; but see below > u32 master_tile_ctl, master_ctl; >- u32 gu_misc_iir; >+ u32 gu_misc_iir = 0; >+ unsigned int i; > > if (!intel_irqs_enabled(i915)) > return IRQ_NONE; > >- master_tile_ctl = dg1_master_intr_disable(regs); >+ master_tile_ctl = dg1_master_intr_disable(t0_regs); > if (!master_tile_ctl) { >- dg1_master_intr_enable(regs); >+ dg1_master_intr_enable(t0_regs); > return IRQ_NONE; > } > >- /* FIXME: we only support tile 0 for now. */ >- if (master_tile_ctl & DG1_MSTR_TILE(0)) { >+ for_each_gt(i915, i, gt) { >+ void __iomem *const regs = gt->uncore->regs; >+ >+ if ((master_tile_ctl & DG1_MSTR_TILE(i)) == 0) >+ continue; >+ > master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ); > raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, master_ctl); >- } else { >- DRM_ERROR("Tile not supported: 0x%08x\n", master_tile_ctl); >- dg1_master_intr_enable(regs); >- return IRQ_NONE; >- } > >- gen11_gt_irq_handler(gt, master_ctl); >+ gen11_gt_irq_handler(gt, master_ctl); >+ >+ gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl); >+ } > > if (master_ctl & GEN11_DISPLAY_IRQ) > gen11_display_irq_handler(i915); > >- gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl); >- >- dg1_master_intr_enable(regs); >+ dg1_master_intr_enable(t0_regs); > > gen11_gu_misc_irq_handler(gt, gu_misc_iir); since we used gt in the for_each_gt() loop it looks like this is not the gt we wanted anymore. Alas gen11_gu_misc_irq_handler() only uses gt to backpoint to i915... so I'm not sure if it should actually be taking a gt as parameter if it is per device rather than per tile/gt. Lucas De Marchi > >-- >2.33.0 >