From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1C09C433EF for ; Wed, 27 Oct 2021 20:17:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C69BD6103C for ; Wed, 27 Oct 2021 20:17:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240910AbhJ0UTZ (ORCPT ); Wed, 27 Oct 2021 16:19:25 -0400 Received: from mail-ot1-f42.google.com ([209.85.210.42]:41546 "EHLO mail-ot1-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240753AbhJ0UTQ (ORCPT ); Wed, 27 Oct 2021 16:19:16 -0400 Received: by mail-ot1-f42.google.com with SMTP id v2-20020a05683018c200b0054e3acddd91so5317666ote.8; Wed, 27 Oct 2021 13:16:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HfrUN45cqHgCg9PtoxrLRh/H00SV7ZMBqcSirS6LsG8=; b=c6SoL+SlMrwJ5wzDr//V9lfaCQUhD6m+WeCmgkZz1mSTIovvHZD3b7UsebyLjQzOkh zGupLi+XIxu90kreH/E78fdIGqr8UeKp0Sh05NXTB1zYibyqRW7E0sC6mkuPPNF4U9CI BZvZDdM2XOr6MTJrdqkkB/DPRkO95j+NTilRUIg0Yb8w45JZ80Wsn81wyvxs37+mWX7D ekgIxXGMXl5MPfBbyFHPEHuyAB75PjlxmETnVtiyUycVQGh1qbiRdOAUs+x4dZbd9FqJ Qvzn+IxACbR7XBNz8DrSTgf+gvjh+lORUBcw/hOcr8ImTlZQLuO9aGsAyLHMKFCe3juP H52w== X-Gm-Message-State: AOAM533HztAqhe5EJyPklXu7E365XiQqfkkC9YWdf8I47Rzr+wFa2cBe hzdUv9vBfjZ7UUdppXTtIQ== X-Google-Smtp-Source: ABdhPJy9IQFcsudy3M0TVBpWfuRRPMkoDZolYuHhAEh/VwV+4a7Jh+jWci4BvaqumrdXRRuLuqzwAg== X-Received: by 2002:a05:6830:1f5c:: with SMTP id u28mr26099975oth.3.1635365810288; Wed, 27 Oct 2021 13:16:50 -0700 (PDT) Received: from xps15.herring.priv (66-90-148-213.dyn.grandenetworks.net. [66.90.148.213]) by smtp.googlemail.com with ESMTPSA id f10sm415332otc.26.2021.10.27.13.16.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Oct 2021 13:16:49 -0700 (PDT) From: Rob Herring To: Will Deacon , Mark Rutland , Peter Zijlstra Cc: Jonathan Corbet , Catalin Marinas , Ingo Molnar , Arnaldo Carvalho de Melo , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Thomas Gleixner , Borislav Petkov , x86@kernel.org, "H. Peter Anvin" , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Raphael Gault Subject: [PATCH v12 5/5] Documentation: arm64: Document PMU counters access from userspace Date: Wed, 27 Oct 2021 15:16:41 -0500 Message-Id: <20211027201641.2076427-6-robh@kernel.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211027201641.2076427-1-robh@kernel.org> References: <20211027201641.2076427-1-robh@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Raphael Gault Add documentation to describe the access to the pmu hardware counters from userspace. Signed-off-by: Raphael Gault Signed-off-by: Rob Herring --- v12: - Add note about accessing PMU registers and PMSELR_EL0 being zeroed v11: - Rework chained event section to reflect 64-bit counter request may fail and 32-bit counters may be 64-bit with upper bits UNKNOWN. v10: - Add details on perf_user_access sysctl v9: - No change v8: - Reword that config1:1 must always be set to request user access v7: - Merge into existing arm64 perf.rst v6: - Update the chained event section with attr.config1 details v2: - Update links to test examples Changes from Raphael's v4: - Convert to rSt - Update chained event status - Add section for heterogeneous systems --- Documentation/arm64/perf.rst | 78 +++++++++++++++++++++++++++++++++++- 1 file changed, 77 insertions(+), 1 deletion(-) diff --git a/Documentation/arm64/perf.rst b/Documentation/arm64/perf.rst index b567f177d385..1f87b57c2332 100644 --- a/Documentation/arm64/perf.rst +++ b/Documentation/arm64/perf.rst @@ -2,7 +2,10 @@ .. _perf_index: -===================== +==== +Perf +==== + Perf Event Attributes ===================== @@ -88,3 +91,76 @@ exclude_host. However when using !exclude_hv there is a small blackout window at the guest entry/exit where host events are not captured. On VHE systems there are no blackout windows. + +Perf Userspace PMU Hardware Counter Access +========================================== + +Overview +-------- +The perf userspace tool relies on the PMU to monitor events. It offers an +abstraction layer over the hardware counters since the underlying +implementation is cpu-dependent. +Arm64 allows userspace tools to have access to the registers storing the +hardware counters' values directly. + +This targets specifically self-monitoring tasks in order to reduce the overhead +by directly accessing the registers without having to go through the kernel. + +How-to +------ +The focus is set on the armv8 PMUv3 which makes sure that the access to the pmu +registers is enabled and that the userspace has access to the relevant +information in order to use them. + +In order to have access to the hardware counters, the global sysctl +kernel/perf_user_access must first be enabled: + +.. code-block:: sh + + echo 1 > /proc/sys/kernel/perf_user_access + +It is necessary to open the event using the perf tool interface with config1:1 +attr bit set: the sys_perf_event_open syscall returns a fd which can +subsequently be used with the mmap syscall in order to retrieve a page of memory +containing information about the event. The PMU driver uses this page to expose +to the user the hardware counter's index and other necessary data. Using this +index enables the user to access the PMU registers using the `mrs` instruction. +Access to the PMU registers is only valid while the sequence lock is unchanged. +In particular, the PMSELR_EL0 register is zeroed each time the sequence lock is +changed. + +The userspace access is supported in libperf using the perf_evsel__mmap() +and perf_evsel__read() functions. See `tools/lib/perf/tests/test-evsel.c`_ for +an example. + +About heterogeneous systems +--------------------------- +On heterogeneous systems such as big.LITTLE, userspace PMU counter access can +only be enabled when the tasks are pinned to a homogeneous subset of cores and +the corresponding PMU instance is opened by specifying the 'type' attribute. +The use of generic event types is not supported in this case. + +Have a look at `tools/perf/arch/arm64/tests/user-events.c`_ for an example. It +can be run using the perf tool to check that the access to the registers works +correctly from userspace: + +.. code-block:: sh + + perf test -v user + +About chained events and counter sizes +-------------------------------------- +The user can request either a 32-bit (config1:0 == 0) or 64-bit (config1:0 == 1) +counter along with userspace access. The sys_perf_event_open syscall will fail +if a 64-bit counter is requested and the hardware doesn't support 64-bit +counters. Chained events are not supported in conjunction with userspace counter +access. If a 32-bit counter is requested on hardware with 64-bit counters, then +userspace must treat the upper 32-bits read from the counter as UNKNOWN. The +'pmc_width' field in the user page will indicate the valid width of the counter +and should be used to mask the upper bits as needed. + +.. Links +.. _tools/perf/arch/arm64/tests/user-events.c: + https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/perf/arch/arm64/tests/user-events.c +.. _tools/lib/perf/tests/test-evsel.c: + https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/lib/perf/tests/test-evsel.c -- 2.32.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47182C433F5 for ; Wed, 27 Oct 2021 20:25:37 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 05A256103C for ; Wed, 27 Oct 2021 20:25:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 05A256103C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=PuadXTM8GwSnPeGSWhs44n8j/5OnLc/cfGLT8eWRNDs=; b=3m63cuwaMWnipt 2m3GN0hAryBAWqe4gEbWGqoHk5zg2qskjj29gQMhrHiZJbsVVVq0VbqjMFsvAlW9FOKxxLKFkfmCs Mh3XEuCrNg8O7Q54odpXexDzOn53nyVhT+1qhKIi0vGwDakWTlVHOxbZZIqga7/vrADu/TmzMdKn9 OgRrAsWqItx+AfAxdKrvCOQSfGN0UW8IsgzzZkvLyUHKJlIa9f2Q28Y7f4ZGxPyuC+VtLp/crZQJm 3tHc0Z7JzJbk+S+y96+j4XpVRSA6b0FYDwvqXKB3AGwKVFi1TnYp4wKMJpgzHzyXvVEYrw+TcN1YO ke9SzXPABu0eQXnAFiPg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mfpT8-0063DI-1q; Wed, 27 Oct 2021 20:24:18 +0000 Received: from mail-oo1-f48.google.com ([209.85.161.48]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mfpT4-0063Ci-5Y for linux-arm-kernel@lists.infradead.org; Wed, 27 Oct 2021 20:24:15 +0000 Received: by mail-oo1-f48.google.com with SMTP id e200-20020a4a55d1000000b002b8bedf08cdso1360528oob.1 for ; Wed, 27 Oct 2021 13:24:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HfrUN45cqHgCg9PtoxrLRh/H00SV7ZMBqcSirS6LsG8=; b=f8Obfwchh5UkNmvUdAAghzOB/I5xqzm2vqUffs2wu8Q+t3ZJTckyJu54lISLChHvzR cWwgfumLC6GrSRu0jtQjrZfVwZ+kPdgsSYae0Lv2g7XWpSMFxTk61PfyoHgl4SAIuDYh 8SbqFVBr72Qjinhxzv+nF7AdTe5Lk1qZcIg4j+boKOkcgn36TIcLnJoZSbFAWezwBlYn CsIAHehNbVmWV/krNRfu7DK5mxUPUZ6rFjGs+9Gc+OQO2nBrH4XfuIPSkvbvnZkjJd6o m9xp0nC2ufVUepIGWarLhXXJXT0cSrloMwbVV6qNetSh9k1uTYRkAWtUsUrql+0WE/gv ZEFg== X-Gm-Message-State: AOAM530Hozzs07E9pUXmIPc5xEultkkljUQLAzsIgLpGq2QA7gm/w4QO Yp4Yh1g0fxSWDxkIPdjIYt9cvUeS1g== X-Google-Smtp-Source: ABdhPJy9IQFcsudy3M0TVBpWfuRRPMkoDZolYuHhAEh/VwV+4a7Jh+jWci4BvaqumrdXRRuLuqzwAg== X-Received: by 2002:a05:6830:1f5c:: with SMTP id u28mr26099975oth.3.1635365810288; Wed, 27 Oct 2021 13:16:50 -0700 (PDT) Received: from xps15.herring.priv (66-90-148-213.dyn.grandenetworks.net. [66.90.148.213]) by smtp.googlemail.com with ESMTPSA id f10sm415332otc.26.2021.10.27.13.16.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Oct 2021 13:16:49 -0700 (PDT) From: Rob Herring To: Will Deacon , Mark Rutland , Peter Zijlstra Cc: Jonathan Corbet , Catalin Marinas , Ingo Molnar , Arnaldo Carvalho de Melo , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Thomas Gleixner , Borislav Petkov , x86@kernel.org, "H. Peter Anvin" , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Raphael Gault Subject: [PATCH v12 5/5] Documentation: arm64: Document PMU counters access from userspace Date: Wed, 27 Oct 2021 15:16:41 -0500 Message-Id: <20211027201641.2076427-6-robh@kernel.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211027201641.2076427-1-robh@kernel.org> References: <20211027201641.2076427-1-robh@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211027_132414_227084_B3CD354E X-CRM114-Status: GOOD ( 26.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Raphael Gault Add documentation to describe the access to the pmu hardware counters from userspace. Signed-off-by: Raphael Gault Signed-off-by: Rob Herring --- v12: - Add note about accessing PMU registers and PMSELR_EL0 being zeroed v11: - Rework chained event section to reflect 64-bit counter request may fail and 32-bit counters may be 64-bit with upper bits UNKNOWN. v10: - Add details on perf_user_access sysctl v9: - No change v8: - Reword that config1:1 must always be set to request user access v7: - Merge into existing arm64 perf.rst v6: - Update the chained event section with attr.config1 details v2: - Update links to test examples Changes from Raphael's v4: - Convert to rSt - Update chained event status - Add section for heterogeneous systems --- Documentation/arm64/perf.rst | 78 +++++++++++++++++++++++++++++++++++- 1 file changed, 77 insertions(+), 1 deletion(-) diff --git a/Documentation/arm64/perf.rst b/Documentation/arm64/perf.rst index b567f177d385..1f87b57c2332 100644 --- a/Documentation/arm64/perf.rst +++ b/Documentation/arm64/perf.rst @@ -2,7 +2,10 @@ .. _perf_index: -===================== +==== +Perf +==== + Perf Event Attributes ===================== @@ -88,3 +91,76 @@ exclude_host. However when using !exclude_hv there is a small blackout window at the guest entry/exit where host events are not captured. On VHE systems there are no blackout windows. + +Perf Userspace PMU Hardware Counter Access +========================================== + +Overview +-------- +The perf userspace tool relies on the PMU to monitor events. It offers an +abstraction layer over the hardware counters since the underlying +implementation is cpu-dependent. +Arm64 allows userspace tools to have access to the registers storing the +hardware counters' values directly. + +This targets specifically self-monitoring tasks in order to reduce the overhead +by directly accessing the registers without having to go through the kernel. + +How-to +------ +The focus is set on the armv8 PMUv3 which makes sure that the access to the pmu +registers is enabled and that the userspace has access to the relevant +information in order to use them. + +In order to have access to the hardware counters, the global sysctl +kernel/perf_user_access must first be enabled: + +.. code-block:: sh + + echo 1 > /proc/sys/kernel/perf_user_access + +It is necessary to open the event using the perf tool interface with config1:1 +attr bit set: the sys_perf_event_open syscall returns a fd which can +subsequently be used with the mmap syscall in order to retrieve a page of memory +containing information about the event. The PMU driver uses this page to expose +to the user the hardware counter's index and other necessary data. Using this +index enables the user to access the PMU registers using the `mrs` instruction. +Access to the PMU registers is only valid while the sequence lock is unchanged. +In particular, the PMSELR_EL0 register is zeroed each time the sequence lock is +changed. + +The userspace access is supported in libperf using the perf_evsel__mmap() +and perf_evsel__read() functions. See `tools/lib/perf/tests/test-evsel.c`_ for +an example. + +About heterogeneous systems +--------------------------- +On heterogeneous systems such as big.LITTLE, userspace PMU counter access can +only be enabled when the tasks are pinned to a homogeneous subset of cores and +the corresponding PMU instance is opened by specifying the 'type' attribute. +The use of generic event types is not supported in this case. + +Have a look at `tools/perf/arch/arm64/tests/user-events.c`_ for an example. It +can be run using the perf tool to check that the access to the registers works +correctly from userspace: + +.. code-block:: sh + + perf test -v user + +About chained events and counter sizes +-------------------------------------- +The user can request either a 32-bit (config1:0 == 0) or 64-bit (config1:0 == 1) +counter along with userspace access. The sys_perf_event_open syscall will fail +if a 64-bit counter is requested and the hardware doesn't support 64-bit +counters. Chained events are not supported in conjunction with userspace counter +access. If a 32-bit counter is requested on hardware with 64-bit counters, then +userspace must treat the upper 32-bits read from the counter as UNKNOWN. The +'pmc_width' field in the user page will indicate the valid width of the counter +and should be used to mask the upper bits as needed. + +.. Links +.. _tools/perf/arch/arm64/tests/user-events.c: + https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/perf/arch/arm64/tests/user-events.c +.. _tools/lib/perf/tests/test-evsel.c: + https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/lib/perf/tests/test-evsel.c -- 2.32.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel