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From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com,
	Anatoly Parshintsev <kupokupokupopo@gmail.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 13/18] target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension
Date: Thu, 28 Oct 2021 14:43:37 +1000	[thread overview]
Message-ID: <20211028044342.3070385-14-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20211028044342.3070385-1-alistair.francis@opensource.wdc.com>

From: Anatoly Parshintsev <kupokupokupopo@gmail.com>

Signed-off-by: Anatoly Parshintsev <kupokupokupopo@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211025173609.2724490-8-space.monkey.delivers@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        |  2 ++
 target/riscv/cpu_helper.c | 18 ++++++++++++++++++
 target/riscv/translate.c  | 39 +++++++++++++++++++++++++++++++++++++--
 3 files changed, 57 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index b2422e3f99..325908287d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -410,6 +410,8 @@ FIELD(TB_FLAGS, HLSX, 10, 1)
 FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2)
 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
 FIELD(TB_FLAGS, XL, 13, 2)
+/* If PointerMasking should be applied */
+FIELD(TB_FLAGS, PM_ENABLED, 15, 1)
 
 #ifdef TARGET_RISCV32
 #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 0d1132f39d..662228c238 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -107,6 +107,24 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
         flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
                            get_field(env->mstatus_hs, MSTATUS_FS));
     }
+    if (riscv_has_ext(env, RVJ)) {
+        int priv = flags & TB_FLAGS_PRIV_MMU_MASK;
+        bool pm_enabled = false;
+        switch (priv) {
+        case PRV_U:
+            pm_enabled = env->mmte & U_PM_ENABLE;
+            break;
+        case PRV_S:
+            pm_enabled = env->mmte & S_PM_ENABLE;
+            break;
+        case PRV_M:
+            pm_enabled = env->mmte & M_PM_ENABLE;
+            break;
+        default:
+            g_assert_not_reached();
+        }
+        flags = FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled);
+    }
 #endif
 
     flags = FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env));
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index a5e6fa145d..1d57bc97b5 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -36,6 +36,9 @@ static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
 static TCGv load_res;
 static TCGv load_val;
+/* globals for PM CSRs */
+static TCGv pm_mask[4];
+static TCGv pm_base[4];
 
 #include "exec/gen-icount.h"
 
@@ -83,6 +86,10 @@ typedef struct DisasContext {
     TCGv zero;
     /* Space for 3 operands plus 1 extra for address computation. */
     TCGv temp[4];
+    /* PointerMasking extension */
+    bool pm_enabled;
+    TCGv pm_mask;
+    TCGv pm_base;
 } DisasContext;
 
 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -272,11 +279,20 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
 }
 
 /*
- * Temp stub: generates address adjustment for PointerMasking
+ * Generates address adjustment for PointerMasking
  */
 static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src)
 {
-    return src;
+    TCGv temp;
+    if (!s->pm_enabled) {
+        /* Load unmodified address */
+        return src;
+    } else {
+        temp = temp_new(s);
+        tcg_gen_andc_tl(temp, src, s->pm_mask);
+        tcg_gen_or_tl(temp, temp, s->pm_base);
+        return temp;
+    }
 }
 
 #ifndef CONFIG_USER_ONLY
@@ -622,6 +638,10 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->cs = cs;
     ctx->ntemp = 0;
     memset(ctx->temp, 0, sizeof(ctx->temp));
+    ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
+    int priv = tb_flags & TB_FLAGS_PRIV_MMU_MASK;
+    ctx->pm_mask = pm_mask[priv];
+    ctx->pm_base = pm_base[priv];
 
     ctx->zero = tcg_constant_tl(0);
 }
@@ -735,4 +755,19 @@ void riscv_translate_init(void)
                              "load_res");
     load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
                              "load_val");
+#ifndef CONFIG_USER_ONLY
+    /* Assign PM CSRs to tcg globals */
+    pm_mask[PRV_U] =
+      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask");
+    pm_base[PRV_U] =
+      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase");
+    pm_mask[PRV_S] =
+      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask");
+    pm_base[PRV_S] =
+      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase");
+    pm_mask[PRV_M] =
+      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask");
+    pm_base[PRV_M] =
+      tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase");
+#endif
 }
-- 
2.31.1



  parent reply	other threads:[~2021-10-28  5:03 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-28  4:43 [PULL 00/18] riscv-to-apply queue Alistair Francis
2021-10-28  4:43 ` [PULL 01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration Alistair Francis
2021-10-28  4:43 ` [PULL 02/18] hw/riscv: boot: Add a PLIC config string function Alistair Francis
2021-10-28  4:43 ` [PULL 03/18] hw/riscv: sifive_u: Use the PLIC config helper function Alistair Francis
2021-10-28  4:43 ` [PULL 04/18] hw/riscv: microchip_pfsoc: " Alistair Francis
2021-10-28  4:43 ` [PULL 05/18] hw/riscv: virt: " Alistair Francis
2021-10-28  4:43 ` [PULL 06/18] hw/riscv: opentitan: Fixup the PLIC context addresses Alistair Francis
2021-10-28  4:43 ` [PULL 07/18] target/riscv: Add J-extension into RISC-V Alistair Francis
2021-10-28  4:43 ` [PULL 08/18] target/riscv: Add CSR defines for RISC-V PM extension Alistair Francis
2021-10-28  4:43 ` [PULL 09/18] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode Alistair Francis
2021-10-28  4:43 ` [PULL 10/18] target/riscv: Add J extension state description Alistair Francis
2021-10-28  4:43 ` [PULL 11/18] target/riscv: Print new PM CSRs in QEMU logs Alistair Francis
2021-10-28  4:43 ` [PULL 12/18] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions Alistair Francis
2021-10-28  4:43 ` Alistair Francis [this message]
2021-10-28  4:43 ` [PULL 14/18] target/riscv: Allow experimental J-ext to be turned on Alistair Francis
2021-10-28  4:43 ` [PULL 15/18] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin Alistair Francis
2021-10-28  4:43 ` [PULL 16/18] target/riscv: change the api for RVF/RVD fmin/fmax Alistair Francis
2021-10-28  8:22   ` Frank Chang
2021-10-28 11:30     ` Alistair Francis
2021-10-28 14:22       ` Richard Henderson
2021-10-28 21:40         ` Alistair Francis
2021-10-28  4:43 ` [PULL 17/18] target/riscv: fix VS interrupts forwarding to HS Alistair Francis
2021-10-28  4:43 ` [PULL 18/18] target/riscv: remove force HS exception Alistair Francis
2021-10-28 16:54 ` [PULL 00/18] riscv-to-apply queue Richard Henderson

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