From: Aaron Liu <aaron.liu@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Alexander.Deucher@amd.com, Ray.Huang@amd.com,
Aaron Liu <aaron.liu@amd.com>
Subject: [PATCH] drm/amdgpu: update RLC_PG_DELAY_3 Value to 200us for yellow carp
Date: Tue, 2 Nov 2021 16:51:18 +0800 [thread overview]
Message-ID: <20211102085118.1465543-1-aaron.liu@amd.com> (raw)
For yellow carp, the desired CGPG hysteresis value is 0x4E20.
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 90a834dc4008..b53b36f5ae92 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -8316,11 +8316,8 @@ static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(10, 3, 1):
- data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
- WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
- break;
case IP_VERSION(10, 3, 3):
- data = 0x1388 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
+ data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
break;
default:
--
2.25.1
next reply other threads:[~2021-11-02 8:52 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-02 8:51 Aaron Liu [this message]
2021-11-02 9:18 ` [PATCH] drm/amdgpu: update RLC_PG_DELAY_3 Value to 200us for yellow carp Huang Rui
2021-11-03 2:32 ` Liu, Aaron
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