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[80.71.140.73]) by smtp.gmail.com with ESMTPSA id c7sm8451374ejd.91.2021.11.02.09.11.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 09:11:53 -0700 (PDT) From: Emil Renner Berthing To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org Cc: Geert Uytterhoeven , Palmer Dabbelt , Paul Walmsley , Rob Herring , Michael Turquette , Stephen Boyd , Thomas Gleixner , Marc Zyngier , Philipp Zabel , Linus Walleij , Greg Kroah-Hartman , Daniel Lezcano , Andy Shevchenko , Jiri Slaby , Maximilian Luz , Sagar Kadam , Drew Fustini , Michael Zhu , Fu Wei , Anup Patel , Atish Patra , Matteo Croce , linux-kernel@vger.kernel.org, Emil Renner Berthing , Rob Herring Subject: [PATCH v3 05/16] dt-bindings: clock: starfive: Add JH7100 bindings Date: Tue, 2 Nov 2021 17:11:14 +0100 Message-Id: <20211102161125.1144023-6-kernel@esmil.dk> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211102161125.1144023-1-kernel@esmil.dk> References: <20211102161125.1144023-1-kernel@esmil.dk> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211102_091155_257535_7F3C47DC X-CRM114-Status: GOOD ( 14.59 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Geert Uytterhoeven Add bindings for the clock generator on the JH7100 RISC-V SoC by StarFive Ltd. This is a test chip for their upcoming JH7110 SoC. Signed-off-by: Geert Uytterhoeven Signed-off-by: Emil Renner Berthing Reviewed-by: Rob Herring --- .../clock/starfive,jh7100-clkgen.yaml | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml new file mode 100644 index 000000000000..12f17b60ecbe --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7100-clkgen.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7100 Clock Generator + +maintainers: + - Geert Uytterhoeven + - Emil Renner Berthing + +properties: + compatible: + const: starfive,jh7100-clkgen + + reg: + maxItems: 1 + + clocks: + items: + - description: Main clock source (25 MHz) + - description: Application-specific clock source (12-27 MHz) + - description: RMII reference clock (50 MHz) + - description: RGMII RX clock (125 MHz) + + clock-names: + items: + - const: osc_sys + - const: osc_aud + - const: gmac_rmii_ref + - const: gmac_gr_mii_rxclk + + '#clock-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@11800000 { + compatible = "starfive,jh7100-clkgen"; + reg = <0x11800000 0x10000>; + clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>; + clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk"; + #clock-cells = <1>; + }; -- 2.33.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77739C4167E for ; Tue, 2 Nov 2021 16:44:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6375F610FC for ; Tue, 2 Nov 2021 16:44:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234844AbhKBQqv (ORCPT ); Tue, 2 Nov 2021 12:46:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234682AbhKBQqs (ORCPT ); Tue, 2 Nov 2021 12:46:48 -0400 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D78ABC061228; Tue, 2 Nov 2021 09:11:56 -0700 (PDT) Received: by mail-ed1-x52d.google.com with SMTP id g14so15544936edz.2; Tue, 02 Nov 2021 09:11:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2spzz5iUsCei46qM+L/MJDySI5miFtOjpI0Cf6AGYao=; b=WxRd8qrhezsDBV76zdNgFbGvonceSYVUFuWl/XoAD+YOv8AJ7Tr0+LFhQ6L28FwMz1 Un/mTpcZuZWChF/15IneWQPInwxFH+4mr+N1untVmSNCJm+lDkpigJfAN093NmzLoHly Y9R1bmxkLP9nbiiGNAtDSMlZjluHwWTG1nvZ2OSSbZHNqZiaWaxnE68X2G344WSlrWmt aqysBH6c8bmms8fOFEEReWYBPkrQIQiemyAWuKYnNIKQtSNV9ampaCetaHJ0Bhc4OvDd 73TA1izwxLNgH42ZBkEbG1iQWtYZ0a34b+ZDDxc0hIuIhZkxEYzBx6xeJPr25oFLIPwL Wgog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=2spzz5iUsCei46qM+L/MJDySI5miFtOjpI0Cf6AGYao=; b=3ema/VhqVeuIQSPs+1Zzmv2xYSfphdE5X62SBniGvdPrU8FQShVY0iwWl9xFL8M3Eb 2OLwsNtXjBi5An4AVRbkC8Ld02ch8RkZYCLHrmC3LszBJwr/ibYLMyBuhHT3+F+5h7Na ITTthyVtmKS5ahMUn/oCNnssejr1gpx7A6yS9kgkFAvUyzpWbL9LrqudQ7SRs5/kIIq9 HRSQjwwYq26tvy0FRY1e/9wjShK60/61eCE8IkXSKeV9rpRgFH0NYwV6GtLPH2anvTpi 2QS8UWHLeQw/3r/gB9R+jR4XxUW1Cp4nlsOE1KgdggjTbRYFEGnkxQcUSfADlb2LFGi6 fNSA== X-Gm-Message-State: AOAM533WEzIFJlFZ+kfqU8p+idulraEH4CVLDshw4fE4eds0vuRHYNjJ RaMOjYqu7+E8dc1LvzoapuI= X-Google-Smtp-Source: ABdhPJwLELEyFD1tbUxnAZfTVpplJpLOULjki97voHP5VnV3zAwR8+cfEFFIw97ZcQcuieeEtdOI1g== X-Received: by 2002:a05:6402:430a:: with SMTP id m10mr20774685edc.273.1635869513942; Tue, 02 Nov 2021 09:11:53 -0700 (PDT) Received: from stitch.. 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[80.71.140.73]) by smtp.gmail.com with ESMTPSA id c7sm8451374ejd.91.2021.11.02.09.11.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 09:11:53 -0700 (PDT) Sender: Emil Renner Berthing From: Emil Renner Berthing To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org Cc: Geert Uytterhoeven , Palmer Dabbelt , Paul Walmsley , Rob Herring , Michael Turquette , Stephen Boyd , Thomas Gleixner , Marc Zyngier , Philipp Zabel , Linus Walleij , Greg Kroah-Hartman , Daniel Lezcano , Andy Shevchenko , Jiri Slaby , Maximilian Luz , Sagar Kadam , Drew Fustini , Michael Zhu , Fu Wei , Anup Patel , Atish Patra , Matteo Croce , linux-kernel@vger.kernel.org, Emil Renner Berthing , Rob Herring Subject: [PATCH v3 05/16] dt-bindings: clock: starfive: Add JH7100 bindings Date: Tue, 2 Nov 2021 17:11:14 +0100 Message-Id: <20211102161125.1144023-6-kernel@esmil.dk> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211102161125.1144023-1-kernel@esmil.dk> References: <20211102161125.1144023-1-kernel@esmil.dk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Geert Uytterhoeven Add bindings for the clock generator on the JH7100 RISC-V SoC by StarFive Ltd. This is a test chip for their upcoming JH7110 SoC. Signed-off-by: Geert Uytterhoeven Signed-off-by: Emil Renner Berthing Reviewed-by: Rob Herring --- .../clock/starfive,jh7100-clkgen.yaml | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml new file mode 100644 index 000000000000..12f17b60ecbe --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7100-clkgen.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7100 Clock Generator + +maintainers: + - Geert Uytterhoeven + - Emil Renner Berthing + +properties: + compatible: + const: starfive,jh7100-clkgen + + reg: + maxItems: 1 + + clocks: + items: + - description: Main clock source (25 MHz) + - description: Application-specific clock source (12-27 MHz) + - description: RMII reference clock (50 MHz) + - description: RGMII RX clock (125 MHz) + + clock-names: + items: + - const: osc_sys + - const: osc_aud + - const: gmac_rmii_ref + - const: gmac_gr_mii_rxclk + + '#clock-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@11800000 { + compatible = "starfive,jh7100-clkgen"; + reg = <0x11800000 0x10000>; + clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>; + clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk"; + #clock-cells = <1>; + }; -- 2.33.1