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From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915: Fix Memory BW formulae for ADL-P
Date: Fri,  5 Nov 2021 17:37:14 -0700	[thread overview]
Message-ID: <20211106003714.17894-1-radhakrishna.sripada@intel.com> (raw)

The earlier update to BW formulae broke ADL-P. Include
GEN13 to use TGL path for BW parameters.

Fixes: c64a9a7c05be drm/i915: Update memory bandwidth formulae
Cc: Matt Roper <matthew.d.roper@intel.com>
Reported-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 15c006194c85..abec394f6869 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -147,7 +147,7 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
 	qi->num_points = dram_info->num_qgv_points;
 	qi->num_psf_points = dram_info->num_psf_gv_points;
 
-	if (DISPLAY_VER(dev_priv) == 12)
+	if (DISPLAY_VER(dev_priv) >= 12)
 		switch (dram_info->type) {
 		case INTEL_DRAM_DDR4:
 			qi->t_bl = is_y_tile ? 8 : 4;
-- 
2.20.1


             reply	other threads:[~2021-11-06  0:37 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-06  0:37 Radhakrishna Sripada [this message]
2021-11-06  1:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix Memory BW formulae for ADL-P Patchwork
2021-11-08 22:46   ` Sripada, Radhakrishna
2021-11-08 23:03     ` Souza, Jose
2021-11-06  3:14 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-11-08 20:18 ` [Intel-gfx] [PATCH] " Yokoyama, Caz
2021-11-08 22:35 ` Souza, Jose

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