From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2AA12C9A for ; Sun, 7 Nov 2021 07:42:06 +0000 (UTC) Received: by mail-wr1-f48.google.com with SMTP id s13so21083662wrb.3 for ; Sun, 07 Nov 2021 00:42:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=x10IZirB5LB8RZRsT12IdJrVjqBTqx2EabDrhJCUln8=; b=W1swplioznskhYAQ1ZqCNQvi2fsHPXAhokpSmvufHZVx07Gvy69LzQTUeT3BrrJwQ+ cEGUdNof1JflZwCpj3rWZ1sFMz6qePAAlqrfcF5Rl6zvIYbOzBXyYu5zCEN0pFssXzpe KTftB8wQZ5OE9QZ4rwH1RLbwiDfVfYio/ItfcKwh4mClDtUKsX0u+NyGt+S2tWtweiab 6D2B4/tTRAbXpbw3Kh1j+UlsGOsuD2v+zso+X4Uj+CFF7dQt5ZhRQHI4Epadni1QIthG k7UlVntS0WFFLenHhKk6jYNDtNnQADal616xPCUxpPJf1tdDM8dp4kkDZVNImIVBMDXy cTNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=x10IZirB5LB8RZRsT12IdJrVjqBTqx2EabDrhJCUln8=; b=Vgdwfs3HMtJICZeuBLvDLLDDrBw1crA8V00U7x9R6BTImgimf3RmBQNSajxZHZFSlt BtfY8mive4jqG//+VsT5vwXWXFVbuLYlHcyug1RGVW2qh/vfz92auTEAuv9dodRgU0Zw P46GluecEDSmYAwU5qe5xWMNGobGgQ1LQUJBymTP0a8qADMf8kAZiGspfFbRHQFOYxYo ICK9W/Fk8ttzMghKLFj7Jnt40Ey8pPo+E6Ry/O1WbNk1euaxh+jakyJWWuzY5wk/vn77 ZV+c7qn9eGHiMhgMn00Gce3Xw1bv+JZOlDwbKGtnhXvBtXaPxieCu4iIr8aaC3PuOP+o 8KKw== X-Gm-Message-State: AOAM5322iHKydAOV6LFfv/h/mRLBLxVpH2FaJfUXIEutR34u+rmj5sku U8AG2ezEw6c+b/iQg5LEKX0= X-Google-Smtp-Source: ABdhPJy75LeVj3e7rKYpSXW0JCBUnqe1MheUEqygdahEB/IjRYt1Pg4wLTfIvcAOBhhdkv7quCsSWA== X-Received: by 2002:a5d:4348:: with SMTP id u8mr27088940wrr.35.1636270925443; Sun, 07 Nov 2021 00:42:05 -0700 (PDT) Received: from localhost.localdomain (252.red-83-54-181.dynamicip.rima-tde.net. [83.54.181.252]) by smtp.gmail.com with ESMTPSA id e12sm15353352wrq.20.2021.11.07.00.42.04 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 07 Nov 2021 00:42:05 -0700 (PDT) From: Sergio Paracuellos To: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org, sboyd@kernel.org, john@phrozen.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name Subject: [PATCH v5 3/4] clk: ralink: make system controller node a reset provider Date: Sun, 7 Nov 2021 08:41:59 +0100 Message-Id: <20211107074200.18911-4-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211107074200.18911-1-sergio.paracuellos@gmail.com> References: <20211107074200.18911-1-sergio.paracuellos@gmail.com> Precedence: bulk X-Mailing-List: linux-staging@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit MT7621 system controller node is already providing the clocks for the whole system but must also serve as a reset provider. Hence, add reset controller related code to the clock driver itself. To get resets properly ready for the rest of the world we need to move platform driver initialization process to 'arch_initcall'. Signed-off-by: Sergio Paracuellos --- drivers/clk/ralink/clk-mt7621.c | 86 ++++++++++++++++++++++++++++++++- 1 file changed, 85 insertions(+), 1 deletion(-) diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c index a2c045390f00..c725bf6e6e07 100644 --- a/drivers/clk/ralink/clk-mt7621.c +++ b/drivers/clk/ralink/clk-mt7621.c @@ -11,14 +11,17 @@ #include #include #include +#include #include #include +#include /* Configuration registers */ #define SYSC_REG_SYSTEM_CONFIG0 0x10 #define SYSC_REG_SYSTEM_CONFIG1 0x14 #define SYSC_REG_CLKCFG0 0x2c #define SYSC_REG_CLKCFG1 0x30 +#define SYSC_REG_RESET_CTRL 0x34 #define SYSC_REG_CUR_CLK_STS 0x44 #define MEMC_REG_CPU_PLL 0x648 @@ -398,6 +401,76 @@ static void __init mt7621_clk_init(struct device_node *node) } CLK_OF_DECLARE_DRIVER(mt7621_clk, "mediatek,mt7621-sysc", mt7621_clk_init); +struct mt7621_rst { + struct reset_controller_dev rcdev; + struct regmap *sysc; +}; + +static struct mt7621_rst *to_mt7621_rst(struct reset_controller_dev *dev) +{ + return container_of(dev, struct mt7621_rst, rcdev); +} + +static int mt7621_assert_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct mt7621_rst *data = to_mt7621_rst(rcdev); + struct regmap *sysc = data->sysc; + + if (id == MT7621_RST_SYS) + return -EINVAL; + + return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id)); +} + +static int mt7621_deassert_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct mt7621_rst *data = to_mt7621_rst(rcdev); + struct regmap *sysc = data->sysc; + + if (id == MT7621_RST_SYS) + return -EINVAL; + + return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0); +} + +static int mt7621_reset_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + int ret; + + ret = mt7621_assert_device(rcdev, id); + if (ret < 0) + return ret; + + return mt7621_deassert_device(rcdev, id); +} + +static const struct reset_control_ops reset_ops = { + .reset = mt7621_reset_device, + .assert = mt7621_assert_device, + .deassert = mt7621_deassert_device +}; + +static int mt7621_reset_init(struct device *dev, struct regmap *sysc) +{ + struct mt7621_rst *rst_data; + + rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL); + if (!rst_data) + return -ENOMEM; + + rst_data->sysc = sysc; + rst_data->rcdev.ops = &reset_ops; + rst_data->rcdev.owner = THIS_MODULE; + rst_data->rcdev.nr_resets = 32; + rst_data->rcdev.of_reset_n_cells = 1; + rst_data->rcdev.of_node = dev_of_node(dev); + + return devm_reset_controller_register(dev, &rst_data->rcdev); +} + static int mt7621_clk_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -424,6 +497,12 @@ static int mt7621_clk_probe(struct platform_device *pdev) return ret; } + ret = mt7621_reset_init(dev, priv->sysc); + if (ret) { + dev_err(dev, "Could not init reset controller\n"); + return ret; + } + count = ARRAY_SIZE(mt7621_clks_base) + ARRAY_SIZE(mt7621_fixed_clks) + ARRAY_SIZE(mt7621_gates); clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count), @@ -485,4 +564,9 @@ static struct platform_driver mt7621_clk_driver = { .of_match_table = mt7621_clk_of_match, }, }; -builtin_platform_driver(mt7621_clk_driver); + +static int __init mt7621_clk_reset_init(void) +{ + return platform_driver_register(&mt7621_clk_driver); +} +arch_initcall(mt7621_clk_reset_init); -- 2.33.0