From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F906C43219 for ; Sun, 7 Nov 2021 20:30:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2AA9761075 for ; Sun, 7 Nov 2021 20:30:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236480AbhKGUdK (ORCPT ); Sun, 7 Nov 2021 15:33:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55594 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236574AbhKGUct (ORCPT ); Sun, 7 Nov 2021 15:32:49 -0500 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C7041C06122B for ; Sun, 7 Nov 2021 12:30:00 -0800 (PST) Received: by mail-lf1-x135.google.com with SMTP id j10so6103786lfu.4 for ; Sun, 07 Nov 2021 12:30:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9RBK6L5sPHBfA9E4ROAzR6qwhEdcT7uzmZdJODyoaHE=; b=p9s4I/1cufJuq7N0Ql9FShfZUL6xclTHtK9U+Dx+lKbOhZsM13PA/ZCCRlvRFmc8Kb MtrU1eNsAnbMh/kyjkPwTkTm2YQ6wXE0WASHANre6YZErjSObsip/S7WCKV++b83b+ef sylMJ3IKBsyKqk5zJSY/F5BE5zZgC6xPAWTNVFbAYCS0CoRiJk8IGX1f4SetNJTC5oCJ 5aGghZFhMT4AWXY2bi9M7+d7yKn1N7oFDwPUYqbSsACtd8kPWogkA9KbuiGn5kwQKo4j VU1IrSMGA/ZEeCrnFsPU3LdfDbWjbhYNMNZik+ACnXRkaZuJ4SNFKPbohE/b+Na4QZ1W S3GA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9RBK6L5sPHBfA9E4ROAzR6qwhEdcT7uzmZdJODyoaHE=; b=OpywMzMXog5Cb3QiD2ib89FuVpxemp7yj7uQFiZ6Qv7/1eT1C086SkD7cbBEaE/fWj HbjKohVZ+cOwk2+SbTD5fuldBX3YGkp/ihvF48UFF+wzWXQ7SZc7zOqF9wQikAo1P1Hm bR7dyD/Ry/ryTGaBJPNZejusYzZaMHIIyBKK8NFXz9DQPy2JCtjMc3lIoZNBFoVDscmb oq9UYMIgdlzGk4N9DGh6F4+Jn2OrtYyZSu2SzbS0soTWxBZOMbMU11juaF7c5GzsrAuQ 6Kf6T9WKBMaetqObi09QOZESO1sWrAczKICwMDGI6tula83G0zpkBQQKXj4kBVfmIFsj xMug== X-Gm-Message-State: AOAM533p7DA0D3jiUW2QrlDsPc1Msvgb9rWbnffY9LpVLgiZQew5FPgM DtLiDz7RY4f3nNL6VG04IX6AzQ== X-Google-Smtp-Source: ABdhPJwMH3gpWIlfVe0lnvJlooRW94dMT8JoEqnaNL5EGkVfAh50QJ4xv4o3IlpkhzEjl/I2Et1Ugw== X-Received: by 2002:a05:6512:3192:: with SMTP id i18mr1355151lfe.569.1636316999205; Sun, 07 Nov 2021 12:29:59 -0800 (PST) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id w15sm22444lfe.245.2021.11.07.12.29.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Nov 2021 12:29:58 -0800 (PST) From: Sam Protsenko To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH v3 08/12] watchdog: s3c2410: Add support for WDT counter enable register Date: Sun, 7 Nov 2021 22:29:39 +0200 Message-Id: <20211107202943.8859-9-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211107202943.8859-1-semen.protsenko@linaro.org> References: <20211107202943.8859-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On new Exynos chips (e.g. Exynos850) new CLUSTERx_NONCPU_OUT register is introduced, where CNT_EN_WDT bit must be enabled to make watchdog counter running. Add corresponding quirk and proper infrastructure to handle that register if the quirk is set. This commit doesn't bring any functional change to existing devices, but merely provides an infrastructure for upcoming chips support. Signed-off-by: Sam Protsenko Reviewed-by: Krzysztof Kozlowski --- Changes in v3: - Added R-b tag by Krzysztof Kozlowski Changes in v2: - Used quirks instead of callbacks for all added PMU registers - Used BIT() macro - Extracted cleanup code to separate patch to minimize changes and ease the review and porting drivers/watchdog/s3c2410_wdt.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index 2a61b6ea5602..ec341c876225 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -60,11 +60,13 @@ #define QUIRK_HAS_RST_STAT (1 << 1) #define QUIRK_HAS_WTCLRINT_REG (1 << 2) #define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3) +#define QUIRK_HAS_PMU_CNT_EN (1 << 4) /* These quirks require that we have a PMU register map */ #define QUIRKS_HAVE_PMUREG (QUIRK_HAS_PMU_CONFIG | \ QUIRK_HAS_RST_STAT | \ - QUIRK_HAS_PMU_AUTO_DISABLE) + QUIRK_HAS_PMU_AUTO_DISABLE | \ + QUIRK_HAS_PMU_CNT_EN) static bool nowayout = WATCHDOG_NOWAYOUT; static int tmr_margin; @@ -98,6 +100,8 @@ MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, 0 to * @rst_stat_reg: Offset in pmureg for the register that has the reset status. * @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog * reset. + * @cnt_en_reg: Offset in pmureg for the register that enables WDT counter. + * @cnt_en_bit: Bit number for "watchdog counter enable" in cnt_en register. * @quirks: A bitfield of quirks. */ @@ -108,6 +112,8 @@ struct s3c2410_wdt_variant { int mask_bit; int rst_stat_reg; int rst_stat_bit; + int cnt_en_reg; + int cnt_en_bit; u32 quirks; }; @@ -233,6 +239,20 @@ static int s3c2410wdt_mask_wdt_reset(struct s3c2410_wdt *wdt, bool mask) return ret; } +static int s3c2410wdt_enable_counter(struct s3c2410_wdt *wdt, bool en) +{ + const u32 mask_val = BIT(wdt->drv_data->cnt_en_bit); + const u32 val = en ? mask_val : 0; + int ret; + + ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->cnt_en_reg, + mask_val, val); + if (ret < 0) + dev_err(wdt->dev, "failed to update reg(%d)\n", ret); + + return ret; +} + static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask) { int ret; @@ -249,6 +269,12 @@ static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask) return ret; } + if (wdt->drv_data->quirks & QUIRK_HAS_PMU_CNT_EN) { + ret = s3c2410wdt_enable_counter(wdt, !mask); + if (ret < 0) + return ret; + } + return 0; } -- 2.30.2 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8ED39C433EF for ; Sun, 7 Nov 2021 20:35:05 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5995E61159 for ; Sun, 7 Nov 2021 20:35:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 5995E61159 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=TZGcO9T72q67DsCic/vstOceMpD2P3RZIIfMulppkR8=; b=U97bVtQD7EBeV2 lcsAngtbwmpPZSyJPXJPS3GOZHPvHZKB2S9RYhGsOuQiZisvO2MHd7PShMo3mjFPw1vIvZhqyeLrI oxZc1TqH36j6aEY1Pdq54EwczfXhpJmk8ksrnp2v+5UiQHBEPgjbr7FC5UUpvHZYsofVNzimbo62A 7fsAwjND9L40lDqoArCWhCKf0ziuIC7vne5Hq1gjEYvi8M06Y2rfTMxSr8K7PAWp3Mimb9sSUXyV6 oiK3XpU3UWCV4GaDXHQehrKnxMYk4pCGP37LsZliIBoj3wtDiLhcP0HuFjECIDy/Nq18ekphJjrMh 2L4zRP7yoHRbGxkGqHAQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mjoqt-00EqAM-Nu; Sun, 07 Nov 2021 20:33:20 +0000 Received: from mail-lf1-x129.google.com ([2a00:1450:4864:20::129]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mjong-00EoiX-Qz for linux-arm-kernel@lists.infradead.org; Sun, 07 Nov 2021 20:30:02 +0000 Received: by mail-lf1-x129.google.com with SMTP id d12so28060465lfv.6 for ; Sun, 07 Nov 2021 12:30:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9RBK6L5sPHBfA9E4ROAzR6qwhEdcT7uzmZdJODyoaHE=; b=p9s4I/1cufJuq7N0Ql9FShfZUL6xclTHtK9U+Dx+lKbOhZsM13PA/ZCCRlvRFmc8Kb MtrU1eNsAnbMh/kyjkPwTkTm2YQ6wXE0WASHANre6YZErjSObsip/S7WCKV++b83b+ef sylMJ3IKBsyKqk5zJSY/F5BE5zZgC6xPAWTNVFbAYCS0CoRiJk8IGX1f4SetNJTC5oCJ 5aGghZFhMT4AWXY2bi9M7+d7yKn1N7oFDwPUYqbSsACtd8kPWogkA9KbuiGn5kwQKo4j VU1IrSMGA/ZEeCrnFsPU3LdfDbWjbhYNMNZik+ACnXRkaZuJ4SNFKPbohE/b+Na4QZ1W S3GA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9RBK6L5sPHBfA9E4ROAzR6qwhEdcT7uzmZdJODyoaHE=; b=WuL+RyMyYFVQ0R70eDDWOnKRjYJUi9rwSfHkTefpoMvn3puzcwq/8hgfm9snKrClVg ldq1QuGGlCb1Ki56+8gHAzDOYRyIuOct1upkfgZHjmAxSu5GyZ9Iy5GiRnxKin7YGbSd iAwcWLr+Kx3PHZzzYadOGjoCL6T+IC+gTMqYyimgw8VUbF30WJYhg3TEE9MRkQ98ZgKh LGuTNJ+wuItNZytAOTxamjDgMpufKrIET4FRUQEDAfuxeXlvyuFo4/6GR7Zll4iVwe+Z fp7GiQHfx2d8Mqbljahmle5GfEN3rZeAlRqsh6J7Cp/f0pZs34NwPxiB1VYqalf/Yyzh c1Og== X-Gm-Message-State: AOAM531tUFzlh97tRNHcq3ObkQi/Yi7fZcn3NXGSmOr7j8Oxd964SWKw C0mYofJZz6JMQb6Bc/JiN9bxMQ== X-Google-Smtp-Source: ABdhPJwMH3gpWIlfVe0lnvJlooRW94dMT8JoEqnaNL5EGkVfAh50QJ4xv4o3IlpkhzEjl/I2Et1Ugw== X-Received: by 2002:a05:6512:3192:: with SMTP id i18mr1355151lfe.569.1636316999205; Sun, 07 Nov 2021 12:29:59 -0800 (PST) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id w15sm22444lfe.245.2021.11.07.12.29.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Nov 2021 12:29:58 -0800 (PST) From: Sam Protsenko To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH v3 08/12] watchdog: s3c2410: Add support for WDT counter enable register Date: Sun, 7 Nov 2021 22:29:39 +0200 Message-Id: <20211107202943.8859-9-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211107202943.8859-1-semen.protsenko@linaro.org> References: <20211107202943.8859-1-semen.protsenko@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211107_123000_942190_3B293212 X-CRM114-Status: GOOD ( 19.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On new Exynos chips (e.g. Exynos850) new CLUSTERx_NONCPU_OUT register is introduced, where CNT_EN_WDT bit must be enabled to make watchdog counter running. Add corresponding quirk and proper infrastructure to handle that register if the quirk is set. This commit doesn't bring any functional change to existing devices, but merely provides an infrastructure for upcoming chips support. Signed-off-by: Sam Protsenko Reviewed-by: Krzysztof Kozlowski --- Changes in v3: - Added R-b tag by Krzysztof Kozlowski Changes in v2: - Used quirks instead of callbacks for all added PMU registers - Used BIT() macro - Extracted cleanup code to separate patch to minimize changes and ease the review and porting drivers/watchdog/s3c2410_wdt.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index 2a61b6ea5602..ec341c876225 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -60,11 +60,13 @@ #define QUIRK_HAS_RST_STAT (1 << 1) #define QUIRK_HAS_WTCLRINT_REG (1 << 2) #define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3) +#define QUIRK_HAS_PMU_CNT_EN (1 << 4) /* These quirks require that we have a PMU register map */ #define QUIRKS_HAVE_PMUREG (QUIRK_HAS_PMU_CONFIG | \ QUIRK_HAS_RST_STAT | \ - QUIRK_HAS_PMU_AUTO_DISABLE) + QUIRK_HAS_PMU_AUTO_DISABLE | \ + QUIRK_HAS_PMU_CNT_EN) static bool nowayout = WATCHDOG_NOWAYOUT; static int tmr_margin; @@ -98,6 +100,8 @@ MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, 0 to * @rst_stat_reg: Offset in pmureg for the register that has the reset status. * @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog * reset. + * @cnt_en_reg: Offset in pmureg for the register that enables WDT counter. + * @cnt_en_bit: Bit number for "watchdog counter enable" in cnt_en register. * @quirks: A bitfield of quirks. */ @@ -108,6 +112,8 @@ struct s3c2410_wdt_variant { int mask_bit; int rst_stat_reg; int rst_stat_bit; + int cnt_en_reg; + int cnt_en_bit; u32 quirks; }; @@ -233,6 +239,20 @@ static int s3c2410wdt_mask_wdt_reset(struct s3c2410_wdt *wdt, bool mask) return ret; } +static int s3c2410wdt_enable_counter(struct s3c2410_wdt *wdt, bool en) +{ + const u32 mask_val = BIT(wdt->drv_data->cnt_en_bit); + const u32 val = en ? mask_val : 0; + int ret; + + ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->cnt_en_reg, + mask_val, val); + if (ret < 0) + dev_err(wdt->dev, "failed to update reg(%d)\n", ret); + + return ret; +} + static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask) { int ret; @@ -249,6 +269,12 @@ static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask) return ret; } + if (wdt->drv_data->quirks & QUIRK_HAS_PMU_CNT_EN) { + ret = s3c2410wdt_enable_counter(wdt, !mask); + if (ret < 0) + return ret; + } + return 0; } -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel