[PATCH v2 0/3] Add WDT driver for RZ/G2L

[PATCH v2 0/3] Add WDT driver for RZ/G2L

[Biju Das]

This patch series aims to add WDT driver support for RZ/G2L SoC's.

WDT has 3 channels 
1) CH0 to check the operation of Cortex-A55-CPU Core0
2) CH1 to check the operation of Cortex-A55-CPU Core1
3) CH2 to check the operation of Cortex-M33 CPU

WDT IP supports 
1) Normal Watchdog Timer Function
2) Reset Request Function due to CPU Parity Error

Once the software activates the watchdog timer, the watchdog timer does
not stop until it is reset.

The WDT Overflow System Reset Register (CPG_WDTOVF_RST) and 
WDT Reset Selector Register (CPG_WDTRST_SEL) are in CPG IP
block.

Current driver supports Normal Watchdog Timer basic functionality.

Tested WDT driver with selftests tool and reboot command

All 3 channels tested with below command.

cat /dev/watchdog  & for i in {1..60}; do sleep 1; echo $i; devmem2 0x12800808; done
cat /dev/watchdog1  & for i in {1..60}; do sleep 1; echo $i; devmem2 0x12800c08; done
cat /dev/watchdog2 & for i in {1..60}; do sleep 1; echo $i; devmem2 0x12800408; done

V1->V2:
 * started using clk_get/put instead of devm_clk_get/put
 * Moved devm_add_action_or_reset after set_drvdata() and 
 * removed redundant action on devm_add_action_or_reset() failure.
RFC->V1
 * Removed patch#3, the clk patch is queued for 5.17
 * Added clock-names and interrupt-names as required properties for RZ/G2L
 * Re-order clocknames with internal module clock first
 * Removed pclk_rate from priv.
 * rzg2l_wdt_write() returns void and Removed tiemout related to register update 
 * rzg2l_wdt_init_timeout() returns void and removed delays.
 * removed set_bit(WDOG_HW_RUNNING,..) as we can stop watchdog
 * renamed reset_assert_clock_disable->reset_assert_pm_disable_put
 * started using devm_reset_control_get_exclusive()
 * removed platform_set_drvdata(pdev, priv) as there is no user
 * removed watchdog_set_restart_priority(&priv->wdev, 0) as 0 is the default.
 * removed remove callback as it is empty.

Biju Das (3):
  clk: renesas: rzg2l: Add support for watchdog reset selection
  dt-bindings: watchdog: renesas,wdt: Add support for RZ/G2L
  watchdog: Add Watchdog Timer driver for RZ/G2L

 .../bindings/watchdog/renesas,wdt.yaml        |  75 ++++--
 drivers/clk/renesas/r9a07g044-cpg.c           |  22 ++
 drivers/clk/renesas/rzg2l-cpg.c               |   6 +
 drivers/clk/renesas/rzg2l-cpg.h               |  14 +
 drivers/watchdog/Kconfig                      |   8 +
 drivers/watchdog/Makefile                     |   1 +
 drivers/watchdog/rzg2l_wdt.c                  | 255 ++++++++++++++++++
 7 files changed, 363 insertions(+), 18 deletions(-)
 create mode 100644 drivers/watchdog/rzg2l_wdt.c

-- 
2.17.1

[PATCH v2 1/3] clk: renesas: rzg2l: Add support for watchdog reset selection

[Biju Das]

This patch adds support for watchdog reset selection.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
V1->V2:
 * No Change
RFC->V1:
 * No change
---
 drivers/clk/renesas/r9a07g044-cpg.c | 22 ++++++++++++++++++++++
 drivers/clk/renesas/rzg2l-cpg.c     |  6 ++++++
 drivers/clk/renesas/rzg2l-cpg.h     | 14 ++++++++++++++
 3 files changed, 42 insertions(+)

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 91643b4e1c9c..0bbdc8bd6235 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -8,6 +8,7 @@
 #include <linux/clk-provider.h>
 #include <linux/device.h>
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/kernel.h>
 
 #include <dt-bindings/clock/r9a07g044-cpg.h>
@@ -295,7 +296,28 @@ static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
 	MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
 };
 
+#define CPG_WDTRST_SEL			0xb14
+#define CPG_WDTRST_SEL_WDTRSTSEL(n)	BIT(n)
+
+#define CPG_WDTRST_SEL_WDTRST	(CPG_WDTRST_SEL_WDTRSTSEL(0) | \
+				 CPG_WDTRST_SEL_WDTRSTSEL(1) | \
+				 CPG_WDTRST_SEL_WDTRSTSEL(2))
+
+int r9a07g044_wdt_rst_setect(void __iomem *base)
+{
+	writel((CPG_WDTRST_SEL_WDTRST << 16) | CPG_WDTRST_SEL_WDTRST,
+	       base + CPG_WDTRST_SEL);
+
+	return 0;
+}
+
+static const struct rzg2l_cpg_soc_operations r9a07g044_cpg_ops = {
+	.wdt_rst_setect = r9a07g044_wdt_rst_setect,
+};
+
 const struct rzg2l_cpg_info r9a07g044_cpg_info = {
+	.ops = &r9a07g044_cpg_ops,
+
 	/* Core Clocks */
 	.core_clks = r9a07g044_core_clks,
 	.num_core_clks = ARRAY_SIZE(r9a07g044_core_clks),
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index a77cb47b75e7..f9dfee14a33e 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -932,6 +932,12 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev)
 	if (error)
 		return error;
 
+	if (info->ops && info->ops->wdt_rst_setect) {
+		error = info->ops->wdt_rst_setect(priv->base);
+		if (error)
+			return error;
+	}
+
 	return 0;
 }
 
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index 484c7cee2629..e1b1497002ed 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -156,9 +156,20 @@ struct rzg2l_reset {
 		.bit = (_bit) \
 	}
 
+/**
+ * struct rzg2l_cpg_soc_operations - SoC-specific CPG Operations
+ *
+ * @wdt_rst_setect: WDT reset selection
+ */
+struct rzg2l_cpg_soc_operations {
+	int (*wdt_rst_setect)(void __iomem *base); /* Platform specific WDT reset selection */
+};
+
 /**
  * struct rzg2l_cpg_info - SoC-specific CPG Description
  *
+ * @ops: SoC-specific CPG Operations
+ *
  * @core_clks: Array of Core Clock definitions
  * @num_core_clks: Number of entries in core_clks[]
  * @last_dt_core_clk: ID of the last Core Clock exported to DT
@@ -176,6 +187,9 @@ struct rzg2l_reset {
  * @num_crit_mod_clks: Number of entries in crit_mod_clks[]
  */
 struct rzg2l_cpg_info {
+	/* CPG Operations */
+	const struct rzg2l_cpg_soc_operations *ops;
+
 	/* Core Clocks */
 	const struct cpg_core_clk *core_clks;
 	unsigned int num_core_clks;
-- 
2.17.1

[PATCH v2 2/3] dt-bindings: watchdog: renesas,wdt: Add support for RZ/G2L

[Biju Das]

Describe the WDT hardware in the RZ/G2L series.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
V1->V2:
 * No Change
RFC->V1:
 * Added clock-names and interrupt-names as required properties for RZ/G2L
 * Re-order clocknames with internal module clock first
---
 .../bindings/watchdog/renesas,wdt.yaml        | 75 ++++++++++++++-----
 1 file changed, 57 insertions(+), 18 deletions(-)

diff --git a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml
index ab66d3f0c476..91a98ccd4226 100644
--- a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml
@@ -10,9 +10,6 @@ maintainers:
   - Wolfram Sang <wsa+renesas@sang-engineering.com>
   - Geert Uytterhoeven <geert+renesas@glider.be>
 
-allOf:
-  - $ref: "watchdog.yaml#"
-
 properties:
   compatible:
     oneOf:
@@ -22,6 +19,11 @@ properties:
               - renesas,r7s9210-wdt      # RZ/A2
           - const: renesas,rza-wdt       # RZ/A
 
+      - items:
+          - enum:
+              - renesas,r9a07g044-wdt    # RZ/G2{L,LC}
+          - const: renesas,rzg2l-wdt     # RZ/G2L
+
       - items:
           - enum:
               - renesas,r8a7742-wdt      # RZ/G1H
@@ -56,11 +58,13 @@ properties:
   reg:
     maxItems: 1
 
-  interrupts:
-    maxItems: 1
+  interrupts: true
 
-  clocks:
-    maxItems: 1
+  interrupt-names: true
+
+  clocks: true
+
+  clock-names: true
 
   power-domains:
     maxItems: 1
@@ -75,17 +79,52 @@ required:
   - reg
   - clocks
 
-if:
-  not:
-    properties:
-      compatible:
-        contains:
-          enum:
-            - renesas,rza-wdt
-then:
-  required:
-    - power-domains
-    - resets
+allOf:
+  - $ref: "watchdog.yaml#"
+
+  - if:
+      not:
+        properties:
+          compatible:
+            contains:
+              enum:
+                - renesas,rza-wdt
+    then:
+      required:
+        - power-domains
+        - resets
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - renesas,rzg2l-wdt
+    then:
+      properties:
+        interrupts:
+          maxItems: 2
+        interrupt-names:
+          items:
+            - const: wdt
+            - const: perrout
+        clocks:
+          items:
+            - description: Register access clock
+            - description: Main clock
+        clock-names:
+          items:
+            - const: pclk
+            - const: oscclk
+      required:
+        - clock-names
+        - interrupt-names
+    else:
+      properties:
+        interrupts:
+          maxItems: 1
+        clocks:
+          maxItems: 1
 
 additionalProperties: false
 
-- 
2.17.1

[PATCH v2 3/3] watchdog: Add Watchdog Timer driver for RZ/G2L

[Biju Das]

Add Watchdog Timer driver for RZ/G2L SoC.

WDT IP block supports normal watchdog timer function and reset
request function due to CPU parity error.

This driver currently supports normal watchdog timer function
and later will add support for reset request function due to
CPU parity error.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
V1->V2:
 * started using clk_get/put instead of devm_clk_get/put
 * Moved devm_add_action_or_reset after set_drvdata() and 
 * removed redundant action on devm_add_action_or_reset() failure.
RFC->V1
 * Removed pclk_rate from priv.
 * rzg2l_wdt_write() returns void and Removed tiemout related to register update 
 * rzg2l_wdt_init_timeout() returns void and removed delays.
 * removed set_bit(WDOG_HW_RUNNING,..) as we can stop watchdog
 * renamed reset_assert_clock_disable->reset_assert_pm_disable_put
 * started using devm_reset_control_get_exclusive()
 * removed platform_set_drvdata(pdev, priv) as there is no user
 * removed watchdog_set_restart_priority(&priv->wdev, 0) as 0 is the default.
 * removed remove callback as it is empty.
---
 drivers/watchdog/Kconfig     |   8 ++
 drivers/watchdog/Makefile    |   1 +
 drivers/watchdog/rzg2l_wdt.c | 255 +++++++++++++++++++++++++++++++++++
 3 files changed, 264 insertions(+)
 create mode 100644 drivers/watchdog/rzg2l_wdt.c

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index bf59faeb3de1..34da309a7afd 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -895,6 +895,14 @@ config RENESAS_RZAWDT
 	  This driver adds watchdog support for the integrated watchdogs in the
 	  Renesas RZ/A SoCs. These watchdogs can be used to reset a system.
 
+config RENESAS_RZG2LWDT
+	tristate "Renesas RZ/G2L WDT Watchdog"
+	depends on ARCH_RENESAS || COMPILE_TEST
+	select WATCHDOG_CORE
+	help
+	  This driver adds watchdog support for the integrated watchdogs in the
+	  Renesas RZ/G2L SoCs. These watchdogs can be used to reset a system.
+
 config ASPEED_WATCHDOG
 	tristate "Aspeed BMC watchdog support"
 	depends on ARCH_ASPEED || COMPILE_TEST
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 1bd2d6f37c53..e7e8ce546814 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -85,6 +85,7 @@ obj-$(CONFIG_LPC18XX_WATCHDOG) += lpc18xx_wdt.o
 obj-$(CONFIG_BCM7038_WDT) += bcm7038_wdt.o
 obj-$(CONFIG_RENESAS_WDT) += renesas_wdt.o
 obj-$(CONFIG_RENESAS_RZAWDT) += rza_wdt.o
+obj-$(CONFIG_RENESAS_RZG2LWDT) += rzg2l_wdt.o
 obj-$(CONFIG_ASPEED_WATCHDOG) += aspeed_wdt.o
 obj-$(CONFIG_STM32_WATCHDOG) += stm32_iwdg.o
 obj-$(CONFIG_UNIPHIER_WATCHDOG) += uniphier_wdt.o
diff --git a/drivers/watchdog/rzg2l_wdt.c b/drivers/watchdog/rzg2l_wdt.c
new file mode 100644
index 000000000000..77f1cfc5ecf6
--- /dev/null
+++ b/drivers/watchdog/rzg2l_wdt.c
@@ -0,0 +1,255 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/G2L WDT Watchdog Driver
+ *
+ * Copyright (C) 2021 Renesas Electronics Corporation
+ */
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <linux/watchdog.h>
+
+#define WDTCNT		0x00
+#define WDTSET		0x04
+#define WDTTIM		0x08
+#define WDTINT		0x0C
+#define WDTCNT_WDTEN	BIT(0)
+#define WDTINT_INTDISP	BIT(0)
+
+#define WDT_DEFAULT_TIMEOUT		60U
+
+/* Setting period time register only 12 bit set in WDTSET[31:20] */
+#define WDTSET_COUNTER_MASK		(0xFFF00000)
+#define WDTSET_COUNTER_VAL(f)		((f) << 20)
+
+#define F2CYCLE_NSEC(f)			(1000000000 / (f))
+#define WDT_CYCLE_MSEC(f, wdttime)	((1024 * 1024 * (((u64)wdttime) + 1)) / \
+					 ((f) / 1000000))
+
+static bool nowayout = WATCHDOG_NOWAYOUT;
+module_param(nowayout, bool, 0);
+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
+				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
+
+struct rzg2l_wdt_priv {
+	void __iomem *base;
+	struct watchdog_device wdev;
+	struct reset_control *rstc;
+	unsigned long osc_clk_rate;
+	unsigned long delay;
+};
+
+static void rzg2l_wdt_wait_delay(struct rzg2l_wdt_priv *priv)
+{
+	/* delay timer when change the setting register */
+	ndelay(priv->delay);
+}
+
+static void rzg2l_wdt_write(struct rzg2l_wdt_priv *priv, u32 val, unsigned int reg)
+{
+	if (reg == WDTSET)
+		val &= WDTSET_COUNTER_MASK;
+
+	writel_relaxed(val, priv->base + reg);
+	/* Registers other than the WDTINT is always synchronized with WDT_CLK */
+	if (reg != WDTINT)
+		rzg2l_wdt_wait_delay(priv);
+}
+
+static void rzg2l_wdt_init_timeout(struct watchdog_device *wdev)
+{
+	struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
+	u32 time_out;
+
+	/* Clear Lapsed Time Register and clear Interrupt */
+	rzg2l_wdt_write(priv, WDTINT_INTDISP, WDTINT);
+	/* 2 consecutive overflow cycle needed to trigger reset */
+	time_out = (wdev->timeout / 2 * 1000000) / WDT_CYCLE_MSEC(priv->osc_clk_rate, 0);
+	rzg2l_wdt_write(priv, WDTSET_COUNTER_VAL(time_out), WDTSET);
+}
+
+static int rzg2l_wdt_start(struct watchdog_device *wdev)
+{
+	struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
+
+	reset_control_deassert(priv->rstc);
+	pm_runtime_get_sync(wdev->parent);
+
+	/* Initialize time out */
+	rzg2l_wdt_init_timeout(wdev);
+
+	/* Initialize watchdog counter register */
+	rzg2l_wdt_write(priv, 0, WDTTIM);
+
+	/* Enable watchdog timer*/
+	rzg2l_wdt_write(priv, WDTCNT_WDTEN, WDTCNT);
+
+	return 0;
+}
+
+static int rzg2l_wdt_stop(struct watchdog_device *wdev)
+{
+	struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
+
+	pm_runtime_put(wdev->parent);
+	reset_control_assert(priv->rstc);
+
+	return 0;
+}
+
+static int rzg2l_wdt_restart(struct watchdog_device *wdev,
+			     unsigned long action, void *data)
+{
+	struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
+
+	/* Reset the module before we modify any register */
+	reset_control_reset(priv->rstc);
+	pm_runtime_get_sync(wdev->parent);
+
+	/* smallest counter value to reboot soon */
+	rzg2l_wdt_write(priv, WDTSET_COUNTER_VAL(1), WDTSET);
+
+	/* Enable watchdog timer*/
+	rzg2l_wdt_write(priv, WDTCNT_WDTEN, WDTCNT);
+
+	return 0;
+}
+
+static const struct watchdog_info rzg2l_wdt_ident = {
+	.options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
+	.identity = "Renesas RZ/G2L WDT Watchdog",
+};
+
+static int rzg2l_wdt_ping(struct watchdog_device *wdev)
+{
+	struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
+
+	rzg2l_wdt_write(priv, WDTINT_INTDISP, WDTINT);
+
+	return 0;
+}
+
+static const struct watchdog_ops rzg2l_wdt_ops = {
+	.owner = THIS_MODULE,
+	.start = rzg2l_wdt_start,
+	.stop = rzg2l_wdt_stop,
+	.ping = rzg2l_wdt_ping,
+	.restart = rzg2l_wdt_restart,
+};
+
+static void rzg2l_wdt_reset_assert_pm_disable_put(void *data)
+{
+	struct watchdog_device *wdev = data;
+	struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
+
+	pm_runtime_put(wdev->parent);
+	pm_runtime_disable(wdev->parent);
+	reset_control_assert(priv->rstc);
+}
+
+static int rzg2l_wdt_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct rzg2l_wdt_priv *priv;
+	unsigned long pclk_rate;
+	struct clk *wdt_clk;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(priv->base))
+		return PTR_ERR(priv->base);
+
+	/* Get watchdog main clock */
+	wdt_clk = clk_get(&pdev->dev, "oscclk");
+	if (IS_ERR(wdt_clk))
+		return dev_err_probe(&pdev->dev, PTR_ERR(wdt_clk), "no oscclk");
+
+	priv->osc_clk_rate = clk_get_rate(wdt_clk);
+	clk_put(wdt_clk);
+	if (!priv->osc_clk_rate)
+		return dev_err_probe(&pdev->dev, -EINVAL, "oscclk rate is 0");
+
+	/* Get Peripheral clock */
+	wdt_clk = clk_get(&pdev->dev, "pclk");
+	if (IS_ERR(wdt_clk))
+		return dev_err_probe(&pdev->dev, PTR_ERR(wdt_clk), "no pclk");
+
+	pclk_rate = clk_get_rate(wdt_clk);
+	clk_put(wdt_clk);
+	if (!pclk_rate)
+		return dev_err_probe(&pdev->dev, -EINVAL, "pclk rate is 0");
+
+	priv->delay = F2CYCLE_NSEC(priv->osc_clk_rate) * 6 + F2CYCLE_NSEC(pclk_rate) * 9;
+
+	priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
+	if (IS_ERR(priv->rstc))
+		return dev_err_probe(&pdev->dev, PTR_ERR(priv->rstc),
+				     "failed to get cpg reset");
+
+	reset_control_deassert(priv->rstc);
+	pm_runtime_enable(&pdev->dev);
+	ret = pm_runtime_resume_and_get(&pdev->dev);
+	if (ret < 0) {
+		dev_err(dev, "pm_runtime_resume_and_get failed ret=%pe", ERR_PTR(ret));
+		goto out_pm_get;
+	}
+
+	priv->wdev.info = &rzg2l_wdt_ident;
+	priv->wdev.ops = &rzg2l_wdt_ops;
+	priv->wdev.parent = dev;
+	priv->wdev.min_timeout = 1;
+	priv->wdev.max_timeout = WDT_CYCLE_MSEC(priv->osc_clk_rate, 0xfff);
+	priv->wdev.timeout = WDT_DEFAULT_TIMEOUT;
+
+	watchdog_set_drvdata(&priv->wdev, priv);
+	ret = devm_add_action_or_reset(&pdev->dev,
+				       rzg2l_wdt_reset_assert_pm_disable_put,
+				       &priv->wdev);
+	if (ret < 0)
+		return ret;
+
+	watchdog_set_nowayout(&priv->wdev, nowayout);
+	watchdog_stop_on_unregister(&priv->wdev);
+
+	ret = watchdog_init_timeout(&priv->wdev, 0, dev);
+	if (ret)
+		dev_warn(dev, "Specified timeout invalid, using default");
+
+	return devm_watchdog_register_device(&pdev->dev, &priv->wdev);
+
+out_pm_get:
+	pm_runtime_disable(dev);
+	reset_control_assert(priv->rstc);
+
+	return ret;
+}
+
+static const struct of_device_id rzg2l_wdt_ids[] = {
+	{ .compatible = "renesas,rzg2l-wdt", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rzg2l_wdt_ids);
+
+static struct platform_driver rzg2l_wdt_driver = {
+	.driver = {
+		.name = "rzg2l_wdt",
+		.of_match_table = rzg2l_wdt_ids,
+	},
+	.probe = rzg2l_wdt_probe,
+};
+module_platform_driver(rzg2l_wdt_driver);
+
+MODULE_DESCRIPTION("Renesas RZ/G2L WDT Watchdog Driver");
+MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
+MODULE_LICENSE("GPL v2");
-- 
2.17.1

RE: [PATCH v2 1/3] clk: renesas: rzg2l: Add support for watchdog reset selection

[Prabhakar Mahadev Lad]

Hi Biju,

Thank you for the patch.

> -----Original Message-----
> From: Biju Das <biju.das.jz@bp.renesas.com>
> Sent: 11 November 2021 11:54
> To: Michael Turquette <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>
> Cc: Biju Das <biju.das.jz@bp.renesas.com>; Geert Uytterhoeven <geert+renesas@glider.be>; linux-
> renesas-soc@vger.kernel.org; linux-watchdog@vger.kernel.org; linux-clk@vger.kernel.org; Chris Paterson
> <Chris.Paterson2@renesas.com>; Biju Das <biju.das@bp.renesas.com>; Prabhakar Mahadev Lad
> <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Subject: [PATCH v2 1/3] clk: renesas: rzg2l: Add support for watchdog reset selection
> 
> This patch adds support for watchdog reset selection.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> V1->V2:
>  * No Change
> RFC->V1:
>  * No change
> ---
>  drivers/clk/renesas/r9a07g044-cpg.c | 22 ++++++++++++++++++++++
>  drivers/clk/renesas/rzg2l-cpg.c     |  6 ++++++
>  drivers/clk/renesas/rzg2l-cpg.h     | 14 ++++++++++++++
>  3 files changed, 42 insertions(+)
> 
> diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
> index 91643b4e1c9c..0bbdc8bd6235 100644
> --- a/drivers/clk/renesas/r9a07g044-cpg.c
> +++ b/drivers/clk/renesas/r9a07g044-cpg.c
> @@ -8,6 +8,7 @@
>  #include <linux/clk-provider.h>
>  #include <linux/device.h>
>  #include <linux/init.h>
> +#include <linux/io.h>
>  #include <linux/kernel.h>
> 
>  #include <dt-bindings/clock/r9a07g044-cpg.h>
> @@ -295,7 +296,28 @@ static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
>  	MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
>  };
> 
> +#define CPG_WDTRST_SEL			0xb14
> +#define CPG_WDTRST_SEL_WDTRSTSEL(n)	BIT(n)
> +
> +#define CPG_WDTRST_SEL_WDTRST	(CPG_WDTRST_SEL_WDTRSTSEL(0) | \
> +				 CPG_WDTRST_SEL_WDTRSTSEL(1) | \
> +				 CPG_WDTRST_SEL_WDTRSTSEL(2))
> +
> +int r9a07g044_wdt_rst_setect(void __iomem *base)
> +{
Can be static.

Cheers,
Prabhakar

> +	writel((CPG_WDTRST_SEL_WDTRST << 16) | CPG_WDTRST_SEL_WDTRST,
> +	       base + CPG_WDTRST_SEL);
> +
> +	return 0;
> +}
> +
> +static const struct rzg2l_cpg_soc_operations r9a07g044_cpg_ops = {
> +	.wdt_rst_setect = r9a07g044_wdt_rst_setect,
> +};
> +
>  const struct rzg2l_cpg_info r9a07g044_cpg_info = {
> +	.ops = &r9a07g044_cpg_ops,
> +
>  	/* Core Clocks */
>  	.core_clks = r9a07g044_core_clks,
>  	.num_core_clks = ARRAY_SIZE(r9a07g044_core_clks),
> diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
> index a77cb47b75e7..f9dfee14a33e 100644
> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> @@ -932,6 +932,12 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev)
>  	if (error)
>  		return error;
> 
> +	if (info->ops && info->ops->wdt_rst_setect) {
> +		error = info->ops->wdt_rst_setect(priv->base);
> +		if (error)
> +			return error;
> +	}
> +
>  	return 0;
>  }
> 
> diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
> index 484c7cee2629..e1b1497002ed 100644
> --- a/drivers/clk/renesas/rzg2l-cpg.h
> +++ b/drivers/clk/renesas/rzg2l-cpg.h
> @@ -156,9 +156,20 @@ struct rzg2l_reset {
>  		.bit = (_bit) \
>  	}
> 
> +/**
> + * struct rzg2l_cpg_soc_operations - SoC-specific CPG Operations
> + *
> + * @wdt_rst_setect: WDT reset selection
> + */
> +struct rzg2l_cpg_soc_operations {
> +	int (*wdt_rst_setect)(void __iomem *base); /* Platform specific WDT reset selection */
> +};
> +
>  /**
>   * struct rzg2l_cpg_info - SoC-specific CPG Description
>   *
> + * @ops: SoC-specific CPG Operations
> + *
>   * @core_clks: Array of Core Clock definitions
>   * @num_core_clks: Number of entries in core_clks[]
>   * @last_dt_core_clk: ID of the last Core Clock exported to DT
> @@ -176,6 +187,9 @@ struct rzg2l_reset {
>   * @num_crit_mod_clks: Number of entries in crit_mod_clks[]
>   */
>  struct rzg2l_cpg_info {
> +	/* CPG Operations */
> +	const struct rzg2l_cpg_soc_operations *ops;
> +
>  	/* Core Clocks */
>  	const struct cpg_core_clk *core_clks;
>  	unsigned int num_core_clks;
> --
> 2.17.1

Re: [PATCH v2 3/3] watchdog: Add Watchdog Timer driver for RZ/G2L

[Guenter Roeck]

On Thu, Nov 11, 2021 at 11:54:27AM +0000, Biju Das wrote:
> Add Watchdog Timer driver for RZ/G2L SoC.
> 
> WDT IP block supports normal watchdog timer function and reset
> request function due to CPU parity error.
> 
> This driver currently supports normal watchdog timer function
> and later will add support for reset request function due to
> CPU parity error.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Guenter Roeck <linux@roeck-us.net>

> ---
> V1->V2:
>  * started using clk_get/put instead of devm_clk_get/put
>  * Moved devm_add_action_or_reset after set_drvdata() and 
>  * removed redundant action on devm_add_action_or_reset() failure.
> RFC->V1
>  * Removed pclk_rate from priv.
>  * rzg2l_wdt_write() returns void and Removed tiemout related to register update 
>  * rzg2l_wdt_init_timeout() returns void and removed delays.
>  * removed set_bit(WDOG_HW_RUNNING,..) as we can stop watchdog
>  * renamed reset_assert_clock_disable->reset_assert_pm_disable_put
>  * started using devm_reset_control_get_exclusive()
>  * removed platform_set_drvdata(pdev, priv) as there is no user
>  * removed watchdog_set_restart_priority(&priv->wdev, 0) as 0 is the default.
>  * removed remove callback as it is empty.
> ---
>  drivers/watchdog/Kconfig     |   8 ++
>  drivers/watchdog/Makefile    |   1 +
>  drivers/watchdog/rzg2l_wdt.c | 255 +++++++++++++++++++++++++++++++++++
>  3 files changed, 264 insertions(+)
>  create mode 100644 drivers/watchdog/rzg2l_wdt.c
> 
> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> index bf59faeb3de1..34da309a7afd 100644
> --- a/drivers/watchdog/Kconfig
> +++ b/drivers/watchdog/Kconfig
> @@ -895,6 +895,14 @@ config RENESAS_RZAWDT
>  	  This driver adds watchdog support for the integrated watchdogs in the
>  	  Renesas RZ/A SoCs. These watchdogs can be used to reset a system.
>  
> +config RENESAS_RZG2LWDT
> +	tristate "Renesas RZ/G2L WDT Watchdog"
> +	depends on ARCH_RENESAS || COMPILE_TEST
> +	select WATCHDOG_CORE
> +	help
> +	  This driver adds watchdog support for the integrated watchdogs in the
> +	  Renesas RZ/G2L SoCs. These watchdogs can be used to reset a system.
> +
>  config ASPEED_WATCHDOG
>  	tristate "Aspeed BMC watchdog support"
>  	depends on ARCH_ASPEED || COMPILE_TEST
> diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
> index 1bd2d6f37c53..e7e8ce546814 100644
> --- a/drivers/watchdog/Makefile
> +++ b/drivers/watchdog/Makefile
> @@ -85,6 +85,7 @@ obj-$(CONFIG_LPC18XX_WATCHDOG) += lpc18xx_wdt.o
>  obj-$(CONFIG_BCM7038_WDT) += bcm7038_wdt.o
>  obj-$(CONFIG_RENESAS_WDT) += renesas_wdt.o
>  obj-$(CONFIG_RENESAS_RZAWDT) += rza_wdt.o
> +obj-$(CONFIG_RENESAS_RZG2LWDT) += rzg2l_wdt.o
>  obj-$(CONFIG_ASPEED_WATCHDOG) += aspeed_wdt.o
>  obj-$(CONFIG_STM32_WATCHDOG) += stm32_iwdg.o
>  obj-$(CONFIG_UNIPHIER_WATCHDOG) += uniphier_wdt.o
> diff --git a/drivers/watchdog/rzg2l_wdt.c b/drivers/watchdog/rzg2l_wdt.c
> new file mode 100644
> index 000000000000..77f1cfc5ecf6
> --- /dev/null
> +++ b/drivers/watchdog/rzg2l_wdt.c
> @@ -0,0 +1,255 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Renesas RZ/G2L WDT Watchdog Driver
> + *
> + * Copyright (C) 2021 Renesas Electronics Corporation
> + */
> +#include <linux/bitops.h>
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/reset.h>
> +#include <linux/watchdog.h>
> +
> +#define WDTCNT		0x00
> +#define WDTSET		0x04
> +#define WDTTIM		0x08
> +#define WDTINT		0x0C
> +#define WDTCNT_WDTEN	BIT(0)
> +#define WDTINT_INTDISP	BIT(0)
> +
> +#define WDT_DEFAULT_TIMEOUT		60U
> +
> +/* Setting period time register only 12 bit set in WDTSET[31:20] */
> +#define WDTSET_COUNTER_MASK		(0xFFF00000)
> +#define WDTSET_COUNTER_VAL(f)		((f) << 20)
> +
> +#define F2CYCLE_NSEC(f)			(1000000000 / (f))
> +#define WDT_CYCLE_MSEC(f, wdttime)	((1024 * 1024 * (((u64)wdttime) + 1)) / \
> +					 ((f) / 1000000))
> +
> +static bool nowayout = WATCHDOG_NOWAYOUT;
> +module_param(nowayout, bool, 0);
> +MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
> +				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
> +
> +struct rzg2l_wdt_priv {
> +	void __iomem *base;
> +	struct watchdog_device wdev;
> +	struct reset_control *rstc;
> +	unsigned long osc_clk_rate;
> +	unsigned long delay;
> +};
> +
> +static void rzg2l_wdt_wait_delay(struct rzg2l_wdt_priv *priv)
> +{
> +	/* delay timer when change the setting register */
> +	ndelay(priv->delay);
> +}
> +
> +static void rzg2l_wdt_write(struct rzg2l_wdt_priv *priv, u32 val, unsigned int reg)
> +{
> +	if (reg == WDTSET)
> +		val &= WDTSET_COUNTER_MASK;
> +
> +	writel_relaxed(val, priv->base + reg);
> +	/* Registers other than the WDTINT is always synchronized with WDT_CLK */
> +	if (reg != WDTINT)
> +		rzg2l_wdt_wait_delay(priv);
> +}
> +
> +static void rzg2l_wdt_init_timeout(struct watchdog_device *wdev)
> +{
> +	struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
> +	u32 time_out;
> +
> +	/* Clear Lapsed Time Register and clear Interrupt */
> +	rzg2l_wdt_write(priv, WDTINT_INTDISP, WDTINT);
> +	/* 2 consecutive overflow cycle needed to trigger reset */
> +	time_out = (wdev->timeout / 2 * 1000000) / WDT_CYCLE_MSEC(priv->osc_clk_rate, 0);
> +	rzg2l_wdt_write(priv, WDTSET_COUNTER_VAL(time_out), WDTSET);
> +}
> +
> +static int rzg2l_wdt_start(struct watchdog_device *wdev)
> +{
> +	struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
> +
> +	reset_control_deassert(priv->rstc);
> +	pm_runtime_get_sync(wdev->parent);
> +
> +	/* Initialize time out */
> +	rzg2l_wdt_init_timeout(wdev);
> +
> +	/* Initialize watchdog counter register */
> +	rzg2l_wdt_write(priv, 0, WDTTIM);
> +
> +	/* Enable watchdog timer*/
> +	rzg2l_wdt_write(priv, WDTCNT_WDTEN, WDTCNT);
> +
> +	return 0;
> +}
> +
> +static int rzg2l_wdt_stop(struct watchdog_device *wdev)
> +{
> +	struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
> +
> +	pm_runtime_put(wdev->parent);
> +	reset_control_assert(priv->rstc);
> +
> +	return 0;
> +}
> +
> +static int rzg2l_wdt_restart(struct watchdog_device *wdev,
> +			     unsigned long action, void *data)
> +{
> +	struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
> +
> +	/* Reset the module before we modify any register */
> +	reset_control_reset(priv->rstc);
> +	pm_runtime_get_sync(wdev->parent);
> +
> +	/* smallest counter value to reboot soon */
> +	rzg2l_wdt_write(priv, WDTSET_COUNTER_VAL(1), WDTSET);
> +
> +	/* Enable watchdog timer*/
> +	rzg2l_wdt_write(priv, WDTCNT_WDTEN, WDTCNT);
> +
> +	return 0;
> +}
> +
> +static const struct watchdog_info rzg2l_wdt_ident = {
> +	.options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
> +	.identity = "Renesas RZ/G2L WDT Watchdog",
> +};
> +
> +static int rzg2l_wdt_ping(struct watchdog_device *wdev)
> +{
> +	struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
> +
> +	rzg2l_wdt_write(priv, WDTINT_INTDISP, WDTINT);
> +
> +	return 0;
> +}
> +
> +static const struct watchdog_ops rzg2l_wdt_ops = {
> +	.owner = THIS_MODULE,
> +	.start = rzg2l_wdt_start,
> +	.stop = rzg2l_wdt_stop,
> +	.ping = rzg2l_wdt_ping,
> +	.restart = rzg2l_wdt_restart,
> +};
> +
> +static void rzg2l_wdt_reset_assert_pm_disable_put(void *data)
> +{
> +	struct watchdog_device *wdev = data;
> +	struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
> +
> +	pm_runtime_put(wdev->parent);
> +	pm_runtime_disable(wdev->parent);
> +	reset_control_assert(priv->rstc);
> +}
> +
> +static int rzg2l_wdt_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct rzg2l_wdt_priv *priv;
> +	unsigned long pclk_rate;
> +	struct clk *wdt_clk;
> +	int ret;
> +
> +	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +	if (!priv)
> +		return -ENOMEM;
> +
> +	priv->base = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(priv->base))
> +		return PTR_ERR(priv->base);
> +
> +	/* Get watchdog main clock */
> +	wdt_clk = clk_get(&pdev->dev, "oscclk");
> +	if (IS_ERR(wdt_clk))
> +		return dev_err_probe(&pdev->dev, PTR_ERR(wdt_clk), "no oscclk");
> +
> +	priv->osc_clk_rate = clk_get_rate(wdt_clk);
> +	clk_put(wdt_clk);
> +	if (!priv->osc_clk_rate)
> +		return dev_err_probe(&pdev->dev, -EINVAL, "oscclk rate is 0");
> +
> +	/* Get Peripheral clock */
> +	wdt_clk = clk_get(&pdev->dev, "pclk");
> +	if (IS_ERR(wdt_clk))
> +		return dev_err_probe(&pdev->dev, PTR_ERR(wdt_clk), "no pclk");
> +
> +	pclk_rate = clk_get_rate(wdt_clk);
> +	clk_put(wdt_clk);
> +	if (!pclk_rate)
> +		return dev_err_probe(&pdev->dev, -EINVAL, "pclk rate is 0");
> +
> +	priv->delay = F2CYCLE_NSEC(priv->osc_clk_rate) * 6 + F2CYCLE_NSEC(pclk_rate) * 9;
> +
> +	priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
> +	if (IS_ERR(priv->rstc))
> +		return dev_err_probe(&pdev->dev, PTR_ERR(priv->rstc),
> +				     "failed to get cpg reset");
> +
> +	reset_control_deassert(priv->rstc);
> +	pm_runtime_enable(&pdev->dev);
> +	ret = pm_runtime_resume_and_get(&pdev->dev);
> +	if (ret < 0) {
> +		dev_err(dev, "pm_runtime_resume_and_get failed ret=%pe", ERR_PTR(ret));
> +		goto out_pm_get;
> +	}
> +
> +	priv->wdev.info = &rzg2l_wdt_ident;
> +	priv->wdev.ops = &rzg2l_wdt_ops;
> +	priv->wdev.parent = dev;
> +	priv->wdev.min_timeout = 1;
> +	priv->wdev.max_timeout = WDT_CYCLE_MSEC(priv->osc_clk_rate, 0xfff);
> +	priv->wdev.timeout = WDT_DEFAULT_TIMEOUT;
> +
> +	watchdog_set_drvdata(&priv->wdev, priv);
> +	ret = devm_add_action_or_reset(&pdev->dev,
> +				       rzg2l_wdt_reset_assert_pm_disable_put,
> +				       &priv->wdev);
> +	if (ret < 0)
> +		return ret;
> +
> +	watchdog_set_nowayout(&priv->wdev, nowayout);
> +	watchdog_stop_on_unregister(&priv->wdev);
> +
> +	ret = watchdog_init_timeout(&priv->wdev, 0, dev);
> +	if (ret)
> +		dev_warn(dev, "Specified timeout invalid, using default");
> +
> +	return devm_watchdog_register_device(&pdev->dev, &priv->wdev);
> +
> +out_pm_get:
> +	pm_runtime_disable(dev);
> +	reset_control_assert(priv->rstc);
> +
> +	return ret;
> +}
> +
> +static const struct of_device_id rzg2l_wdt_ids[] = {
> +	{ .compatible = "renesas,rzg2l-wdt", },
> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, rzg2l_wdt_ids);
> +
> +static struct platform_driver rzg2l_wdt_driver = {
> +	.driver = {
> +		.name = "rzg2l_wdt",
> +		.of_match_table = rzg2l_wdt_ids,
> +	},
> +	.probe = rzg2l_wdt_probe,
> +};
> +module_platform_driver(rzg2l_wdt_driver);
> +
> +MODULE_DESCRIPTION("Renesas RZ/G2L WDT Watchdog Driver");
> +MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
> +MODULE_LICENSE("GPL v2");
> -- 
> 2.17.1
> 

RE: [PATCH v2 1/3] clk: renesas: rzg2l: Add support for watchdog reset selection

[Biju Das]

Hi Prabhakar,

Thanks for the feedback

> Subject: RE: [PATCH v2 1/3] clk: renesas: rzg2l: Add support for watchdog
> reset selection
> 
> Hi Biju,
> 
> Thank you for the patch.
> 
> > -----Original Message-----
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> > Sent: 11 November 2021 11:54
> > To: Michael Turquette <mturquette@baylibre.com>; Stephen Boyd
> > <sboyd@kernel.org>
> > Cc: Biju Das <biju.das.jz@bp.renesas.com>; Geert Uytterhoeven
> > <geert+renesas@glider.be>; linux- renesas-soc@vger.kernel.org;
> > linux-watchdog@vger.kernel.org; linux-clk@vger.kernel.org; Chris
> > Paterson <Chris.Paterson2@renesas.com>; Biju Das
> > <biju.das@bp.renesas.com>; Prabhakar Mahadev Lad
> > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Subject: [PATCH v2 1/3] clk: renesas: rzg2l: Add support for watchdog
> > reset selection
> >
> > This patch adds support for watchdog reset selection.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > V1->V2:
> >  * No Change
> > RFC->V1:
> >  * No change
> > ---
> >  drivers/clk/renesas/r9a07g044-cpg.c | 22 ++++++++++++++++++++++
> >  drivers/clk/renesas/rzg2l-cpg.c     |  6 ++++++
> >  drivers/clk/renesas/rzg2l-cpg.h     | 14 ++++++++++++++
> >  3 files changed, 42 insertions(+)
> >
> > diff --git a/drivers/clk/renesas/r9a07g044-cpg.c
> > b/drivers/clk/renesas/r9a07g044-cpg.c
> > index 91643b4e1c9c..0bbdc8bd6235 100644
> > --- a/drivers/clk/renesas/r9a07g044-cpg.c
> > +++ b/drivers/clk/renesas/r9a07g044-cpg.c
> > @@ -8,6 +8,7 @@
> >  #include <linux/clk-provider.h>
> >  #include <linux/device.h>
> >  #include <linux/init.h>
> > +#include <linux/io.h>
> >  #include <linux/kernel.h>
> >
> >  #include <dt-bindings/clock/r9a07g044-cpg.h>
> > @@ -295,7 +296,28 @@ static const unsigned int r9a07g044_crit_mod_clks[]
> __initconst = {
> >  	MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
> >  };
> >
> > +#define CPG_WDTRST_SEL			0xb14
> > +#define CPG_WDTRST_SEL_WDTRSTSEL(n)	BIT(n)
> > +
> > +#define CPG_WDTRST_SEL_WDTRST	(CPG_WDTRST_SEL_WDTRSTSEL(0) | \
> > +				 CPG_WDTRST_SEL_WDTRSTSEL(1) | \
> > +				 CPG_WDTRST_SEL_WDTRSTSEL(2))
> > +
> > +int r9a07g044_wdt_rst_setect(void __iomem *base) {
> Can be static.

OK. Will change to static on the next version.

Geert,
On the, next version I am planning to introduce the below code for
Reset selection based on device availability, instead of selecting
all the channels. Is it the right way to do ? please let me know.

node = of_find_node_by_name (NULL, NULL, "watchdog@12800800");
if (node && of_device_is_available(node) {
 	// set reset selection for that channel
 	of_node_put(node);
}

node = of_find_node_by_name (NULL, NULL, "watchdog@12800c00");
if (node && of_device_is_available(node) {
 	// set reset selection for that channel
 	of_node_put(node);
}

node = of_find_node_by_name (NULL, NULL, "watchdog@12800400");
if (node && of_device_is_available(node) {
 	// set reset selection for that channel
 	of_node_put(node);
}

Regards,
Biju

> 
> Cheers,
> Prabhakar
> 
> > +	writel((CPG_WDTRST_SEL_WDTRST << 16) | CPG_WDTRST_SEL_WDTRST,
> > +	       base + CPG_WDTRST_SEL);
> > +
> > +	return 0;
> > +}
> > +
> > +static const struct rzg2l_cpg_soc_operations r9a07g044_cpg_ops = {
> > +	.wdt_rst_setect = r9a07g044_wdt_rst_setect, };
> > +
> >  const struct rzg2l_cpg_info r9a07g044_cpg_info = {
> > +	.ops = &r9a07g044_cpg_ops,
> > +
> >  	/* Core Clocks */
> >  	.core_clks = r9a07g044_core_clks,
> >  	.num_core_clks = ARRAY_SIZE(r9a07g044_core_clks), diff --git
> > a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
> > index a77cb47b75e7..f9dfee14a33e 100644
> > --- a/drivers/clk/renesas/rzg2l-cpg.c
> > +++ b/drivers/clk/renesas/rzg2l-cpg.c
> > @@ -932,6 +932,12 @@ static int __init rzg2l_cpg_probe(struct
> platform_device *pdev)
> >  	if (error)
> >  		return error;
> >
> > +	if (info->ops && info->ops->wdt_rst_setect) {
> > +		error = info->ops->wdt_rst_setect(priv->base);
> > +		if (error)
> > +			return error;
> > +	}
> > +
> >  	return 0;
> >  }
> >
> > diff --git a/drivers/clk/renesas/rzg2l-cpg.h
> > b/drivers/clk/renesas/rzg2l-cpg.h index 484c7cee2629..e1b1497002ed
> > 100644
> > --- a/drivers/clk/renesas/rzg2l-cpg.h
> > +++ b/drivers/clk/renesas/rzg2l-cpg.h
> > @@ -156,9 +156,20 @@ struct rzg2l_reset {
> >  		.bit = (_bit) \
> >  	}
> >
> > +/**
> > + * struct rzg2l_cpg_soc_operations - SoC-specific CPG Operations
> > + *
> > + * @wdt_rst_setect: WDT reset selection  */ struct
> > +rzg2l_cpg_soc_operations {
> > +	int (*wdt_rst_setect)(void __iomem *base); /* Platform specific WDT
> > +reset selection */ };
> > +
> >  /**
> >   * struct rzg2l_cpg_info - SoC-specific CPG Description
> >   *
> > + * @ops: SoC-specific CPG Operations
> > + *
> >   * @core_clks: Array of Core Clock definitions
> >   * @num_core_clks: Number of entries in core_clks[]
> >   * @last_dt_core_clk: ID of the last Core Clock exported to DT @@
> > -176,6 +187,9 @@ struct rzg2l_reset {
> >   * @num_crit_mod_clks: Number of entries in crit_mod_clks[]
> >   */
> >  struct rzg2l_cpg_info {
> > +	/* CPG Operations */
> > +	const struct rzg2l_cpg_soc_operations *ops;
> > +
> >  	/* Core Clocks */
> >  	const struct cpg_core_clk *core_clks;
> >  	unsigned int num_core_clks;
> > --
> > 2.17.1

Re: [PATCH v2 1/3] clk: renesas: rzg2l: Add support for watchdog reset selection

[Geert Uytterhoeven]

Hi Biju,

Thanks for your patch!

On Thu, Nov 11, 2021 at 12:54 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> This patch adds support for watchdog reset selection.

Please explain what this patch really does, and why it is needed,
instead of repeating the one-line summary.

> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

> --- a/drivers/clk/renesas/r9a07g044-cpg.c
> +++ b/drivers/clk/renesas/r9a07g044-cpg.c

> @@ -295,7 +296,28 @@ static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
>         MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
>  };
>
> +#define CPG_WDTRST_SEL                 0xb14
> +#define CPG_WDTRST_SEL_WDTRSTSEL(n)    BIT(n)
> +
> +#define CPG_WDTRST_SEL_WDTRST  (CPG_WDTRST_SEL_WDTRSTSEL(0) | \
> +                                CPG_WDTRST_SEL_WDTRSTSEL(1) | \
> +                                CPG_WDTRST_SEL_WDTRSTSEL(2))

You might as well use BIT() directly. Or GENMASK().

> +
> +int r9a07g044_wdt_rst_setect(void __iomem *base)
> +{
> +       writel((CPG_WDTRST_SEL_WDTRST << 16) | CPG_WDTRST_SEL_WDTRST,
> +              base + CPG_WDTRST_SEL);
> +
> +       return 0;
> +}
> +
> +static const struct rzg2l_cpg_soc_operations r9a07g044_cpg_ops = {
> +       .wdt_rst_setect = r9a07g044_wdt_rst_setect,

As you use a function pointer, I assume different SoCs need different
handling, and you can't just store e.g. a bitmask of bits to set in info?


> +};
> +
>  const struct rzg2l_cpg_info r9a07g044_cpg_info = {
> +       .ops = &r9a07g044_cpg_ops,
> +
>         /* Core Clocks */
>         .core_clks = r9a07g044_core_clks,
>         .num_core_clks = ARRAY_SIZE(r9a07g044_core_clks),
> diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
> index a77cb47b75e7..f9dfee14a33e 100644
> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> @@ -932,6 +932,12 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev)
>         if (error)
>                 return error;
>
> +       if (info->ops && info->ops->wdt_rst_setect) {
> +               error = info->ops->wdt_rst_setect(priv->base);
> +               if (error)
> +                       return error;
> +       }
> +
>         return 0;
>  }
>
> diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
> index 484c7cee2629..e1b1497002ed 100644
> --- a/drivers/clk/renesas/rzg2l-cpg.h
> +++ b/drivers/clk/renesas/rzg2l-cpg.h
> @@ -156,9 +156,20 @@ struct rzg2l_reset {
>                 .bit = (_bit) \
>         }
>
> +/**
> + * struct rzg2l_cpg_soc_operations - SoC-specific CPG Operations
> + *
> + * @wdt_rst_setect: WDT reset selection
> + */
> +struct rzg2l_cpg_soc_operations {
> +       int (*wdt_rst_setect)(void __iomem *base); /* Platform specific WDT reset selection */

Do you plan to add more operations?

> +};
> +
>  /**
>   * struct rzg2l_cpg_info - SoC-specific CPG Description
>   *
> + * @ops: SoC-specific CPG Operations
> + *
>   * @core_clks: Array of Core Clock definitions
>   * @num_core_clks: Number of entries in core_clks[]
>   * @last_dt_core_clk: ID of the last Core Clock exported to DT
> @@ -176,6 +187,9 @@ struct rzg2l_reset {
>   * @num_crit_mod_clks: Number of entries in crit_mod_clks[]
>   */
>  struct rzg2l_cpg_info {
> +       /* CPG Operations */
> +       const struct rzg2l_cpg_soc_operations *ops;
> +
>         /* Core Clocks */
>         const struct cpg_core_clk *core_clks;
>         unsigned int num_core_clks;

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 1/3] clk: renesas: rzg2l: Add support for watchdog reset selection

[Geert Uytterhoeven]

Hi Biju,

On Wed, Nov 17, 2021 at 9:21 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> On the, next version I am planning to introduce the below code for
> Reset selection based on device availability, instead of selecting
> all the channels. Is it the right way to do ? please let me know.
>
> node = of_find_node_by_name (NULL, NULL, "watchdog@12800800");
> if (node && of_device_is_available(node) {
>         // set reset selection for that channel
>         of_node_put(node);
> }
>
> node = of_find_node_by_name (NULL, NULL, "watchdog@12800c00");
> if (node && of_device_is_available(node) {
>         // set reset selection for that channel
>         of_node_put(node);
> }
>
> node = of_find_node_by_name (NULL, NULL, "watchdog@12800400");
> if (node && of_device_is_available(node) {
>         // set reset selection for that channel
>         of_node_put(node);
> }

Matching on node names is very fragile.  And what if the watchdog
node is enabled in DT, but the watchdog driver is not available?
Moreover, this looks like it should not be controlled from the clock
driver, but from the watchdog driver instead.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v2 1/3] clk: renesas: rzg2l: Add support for watchdog reset selection

[Biju Das]

Hi Geert,

Thanks for the feedback.

> Subject: Re: [PATCH v2 1/3] clk: renesas: rzg2l: Add support for watchdog
> reset selection
> 
> Hi Biju,
> 
> Thanks for your patch!
> 
> On Thu, Nov 11, 2021 at 12:54 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > This patch adds support for watchdog reset selection.
> 
> Please explain what this patch really does, and why it is needed, instead
> of repeating the one-line summary.

OK will do. CPG IP block contains 2 WDT registers. 1) WDT reset selector and 
2) WDT Overflow system Register. 

Former one is used to mask reset requests from WDT and the later
One used to check the WDTOVF status and clearing.

CPG IP and WDT IP are in different address space. The operation involving
WDT reset selector, is a configuration operation, which we can do
in Clock driver without any direct call from WDT driver to CPG.

Where as Operation involving WDT Overflow system Register, needs to
be exported to WDT driver, as it needs WDTOVF status, so that It can support
WDIOF_CARDRESET option.

> 
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> 
> > --- a/drivers/clk/renesas/r9a07g044-cpg.c
> > +++ b/drivers/clk/renesas/r9a07g044-cpg.c
> 
> > @@ -295,7 +296,28 @@ static const unsigned int r9a07g044_crit_mod_clks[]
> __initconst = {
> >         MOD_CLK_BASE + R9A07G044_DMAC_ACLK,  };
> >
> > +#define CPG_WDTRST_SEL                 0xb14
> > +#define CPG_WDTRST_SEL_WDTRSTSEL(n)    BIT(n)
> > +
> > +#define CPG_WDTRST_SEL_WDTRST  (CPG_WDTRST_SEL_WDTRSTSEL(0) | \
> > +                                CPG_WDTRST_SEL_WDTRSTSEL(1) | \
> > +                                CPG_WDTRST_SEL_WDTRSTSEL(2))
> 
> You might as well use BIT() directly. Or GENMASK().

OK.

> 
> > +
> > +int r9a07g044_wdt_rst_setect(void __iomem *base) {
> > +       writel((CPG_WDTRST_SEL_WDTRST << 16) | CPG_WDTRST_SEL_WDTRST,
> > +              base + CPG_WDTRST_SEL);
> > +
> > +       return 0;
> > +}
> > +
> > +static const struct rzg2l_cpg_soc_operations r9a07g044_cpg_ops = {
> > +       .wdt_rst_setect = r9a07g044_wdt_rst_setect,
> 
> As you use a function pointer, I assume different SoCs need different
> handling, and you can't just store e.g. a bitmask of bits to set in info?

Currently I am not sure about RZ/G2UL, since it has single Core.
That is the reason function pointer Introduced. For RZ/G2{L,LC} it is same.
I will drop function pointer and store it in bitmask of bits.

> 
> 
> > +};
> > +
> >  const struct rzg2l_cpg_info r9a07g044_cpg_info = {
> > +       .ops = &r9a07g044_cpg_ops,
> > +
> >         /* Core Clocks */
> >         .core_clks = r9a07g044_core_clks,
> >         .num_core_clks = ARRAY_SIZE(r9a07g044_core_clks), diff --git
> > a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
> > index a77cb47b75e7..f9dfee14a33e 100644
> > --- a/drivers/clk/renesas/rzg2l-cpg.c
> > +++ b/drivers/clk/renesas/rzg2l-cpg.c
> > @@ -932,6 +932,12 @@ static int __init rzg2l_cpg_probe(struct
> platform_device *pdev)
> >         if (error)
> >                 return error;
> >
> > +       if (info->ops && info->ops->wdt_rst_setect) {
> > +               error = info->ops->wdt_rst_setect(priv->base);
> > +               if (error)
> > +                       return error;
> > +       }
> > +
> >         return 0;
> >  }
> >
> > diff --git a/drivers/clk/renesas/rzg2l-cpg.h
> > b/drivers/clk/renesas/rzg2l-cpg.h index 484c7cee2629..e1b1497002ed
> > 100644
> > --- a/drivers/clk/renesas/rzg2l-cpg.h
> > +++ b/drivers/clk/renesas/rzg2l-cpg.h
> > @@ -156,9 +156,20 @@ struct rzg2l_reset {
> >                 .bit = (_bit) \
> >         }
> >
> > +/**
> > + * struct rzg2l_cpg_soc_operations - SoC-specific CPG Operations
> > + *
> > + * @wdt_rst_setect: WDT reset selection  */ struct
> > +rzg2l_cpg_soc_operations {
> > +       int (*wdt_rst_setect)(void __iomem *base); /* Platform
> > +specific WDT reset selection */
> 
> Do you plan to add more operations?

As mentioned above, I am dropping function pointer and going with bitmask.

Another Operation to be added in future is to export WDTOVF status to WDT driver. 
So that the  Watchdog driver will get last boot status from CPG IP.

But currently, I guess we can do this only with exported API??
Do you have any other suggestion apart from this? Please let me know.

Regards,
Biju

RE: [PATCH v2 1/3] clk: renesas: rzg2l: Add support for watchdog reset selection

[Biju Das]

Hi Geert,

Thanks for the feedback.

> Subject: Re: [PATCH v2 1/3] clk: renesas: rzg2l: Add support for watchdog
> reset selection
> 
> Hi Biju,
> 
> On Wed, Nov 17, 2021 at 9:21 AM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > On the, next version I am planning to introduce the below code for
> > Reset selection based on device availability, instead of selecting all
> > the channels. Is it the right way to do ? please let me know.
> >
> > node = of_find_node_by_name (NULL, NULL, "watchdog@12800800"); if
> > (node && of_device_is_available(node) {
> >         // set reset selection for that channel
> >         of_node_put(node);
> > }
> >
> > node = of_find_node_by_name (NULL, NULL, "watchdog@12800c00"); if
> > (node && of_device_is_available(node) {
> >         // set reset selection for that channel
> >         of_node_put(node);
> > }
> >
> > node = of_find_node_by_name (NULL, NULL, "watchdog@12800400"); if
> > (node && of_device_is_available(node) {
> >         // set reset selection for that channel
> >         of_node_put(node);
> > }
> 
> Matching on node names is very fragile.

Agreed. 

  And what if the watchdog node is
> enabled in DT, but the watchdog driver is not available?
We will just configure, but since there is no watch driver available.
I guess nothing will happen.

> Moreover, this looks like it should not be controlled from the clock
> driver, but from the watchdog driver instead.

I have referred configure option from reset driver for R-Car, where WDT is configured
in reset block as similar register is located in reset block rather the watchdog driver.

May be I should not use Matching on node names, rather use bitmask of bits as you suggested.

Please share your views.

Regards,
Biju

Re: [PATCH v2 1/3] clk: renesas: rzg2l: Add support for watchdog reset selection

[Geert Uytterhoeven]

Hi Biju,

On Thu, Nov 18, 2021 at 5:01 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > Subject: Re: [PATCH v2 1/3] clk: renesas: rzg2l: Add support for watchdog
> > reset selection
> > On Wed, Nov 17, 2021 at 9:21 AM Biju Das <biju.das.jz@bp.renesas.com>
> > wrote:
> > > On the, next version I am planning to introduce the below code for
> > > Reset selection based on device availability, instead of selecting all
> > > the channels. Is it the right way to do ? please let me know.
> > >
> > > node = of_find_node_by_name (NULL, NULL, "watchdog@12800800"); if
> > > (node && of_device_is_available(node) {
> > >         // set reset selection for that channel
> > >         of_node_put(node);
> > > }
> > >
> > > node = of_find_node_by_name (NULL, NULL, "watchdog@12800c00"); if
> > > (node && of_device_is_available(node) {
> > >         // set reset selection for that channel
> > >         of_node_put(node);
> > > }
> > >
> > > node = of_find_node_by_name (NULL, NULL, "watchdog@12800400"); if
> > > (node && of_device_is_available(node) {
> > >         // set reset selection for that channel
> > >         of_node_put(node);
> > > }
> >
> > Matching on node names is very fragile.
>
> Agreed.
>
>   And what if the watchdog node is
> > enabled in DT, but the watchdog driver is not available?
> We will just configure, but since there is no watch driver available.
> I guess nothing will happen.
>
> > Moreover, this looks like it should not be controlled from the clock
> > driver, but from the watchdog driver instead.
>
> I have referred configure option from reset driver for R-Car, where WDT is configured
> in reset block as similar register is located in reset block rather the watchdog driver.
>
> May be I should not use Matching on node names, rather use bitmask of bits as you suggested.
>
> Please share your views.

On R-Car Gen2 and RZ/G1 SoCs, this is indeed configured by the
rcar-rst driver, because the support was added later. Initial R-Car
Gen2 revisions had hardware quirks preventing proper operation.
On R-Car Gen3 and other RZ/G2 SoCs, this is configured by the boot
loader, and it would be great if new SoCs (R-Car V3U, R-Car S4-8,
and RZ/G2L) would handle this the same way.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v2 1/3] clk: renesas: rzg2l: Add support for watchdog reset selection

[Biju Das]

Hi Geert,

> Subject: Re: [PATCH v2 1/3] clk: renesas: rzg2l: Add support for watchdog
> reset selection
> 
> Hi Biju,
> 
> On Thu, Nov 18, 2021 at 5:01 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > > Subject: Re: [PATCH v2 1/3] clk: renesas: rzg2l: Add support for
> > > watchdog reset selection On Wed, Nov 17, 2021 at 9:21 AM Biju Das
> > > <biju.das.jz@bp.renesas.com>
> > > wrote:
> > > > On the, next version I am planning to introduce the below code for
> > > > Reset selection based on device availability, instead of selecting
> > > > all the channels. Is it the right way to do ? please let me know.
> > > >
> > > > node = of_find_node_by_name (NULL, NULL, "watchdog@12800800"); if
> > > > (node && of_device_is_available(node) {
> > > >         // set reset selection for that channel
> > > >         of_node_put(node);
> > > > }
> > > >
> > > > node = of_find_node_by_name (NULL, NULL, "watchdog@12800c00"); if
> > > > (node && of_device_is_available(node) {
> > > >         // set reset selection for that channel
> > > >         of_node_put(node);
> > > > }
> > > >
> > > > node = of_find_node_by_name (NULL, NULL, "watchdog@12800400"); if
> > > > (node && of_device_is_available(node) {
> > > >         // set reset selection for that channel
> > > >         of_node_put(node);
> > > > }
> > >
> > > Matching on node names is very fragile.
> >
> > Agreed.
> >
> >   And what if the watchdog node is
> > > enabled in DT, but the watchdog driver is not available?
> > We will just configure, but since there is no watch driver available.
> > I guess nothing will happen.
> >
> > > Moreover, this looks like it should not be controlled from the clock
> > > driver, but from the watchdog driver instead.
> >
> > I have referred configure option from reset driver for R-Car, where
> > WDT is configured in reset block as similar register is located in reset
> block rather the watchdog driver.
> >
> > May be I should not use Matching on node names, rather use bitmask of
> bits as you suggested.
> >
> > Please share your views.
> 
> On R-Car Gen2 and RZ/G1 SoCs, this is indeed configured by the rcar-rst
> driver, because the support was added later. Initial R-Car
> Gen2 revisions had hardware quirks preventing proper operation.
> On R-Car Gen3 and other RZ/G2 SoCs, this is configured by the boot loader,
> and it would be great if new SoCs (R-Car V3U, R-Car S4-8, and RZ/G2L)
> would handle this the same way.

Agreed, will move to bootloader. On R-Car it is done in TF-A(bl2_plat_setup).
Will do the same for RZ/G2L as well.

Regards,
Biju