From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECCFCC4332F for ; Fri, 12 Nov 2021 08:10:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D01BC60FBF for ; Fri, 12 Nov 2021 08:10:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233999AbhKLINL (ORCPT ); Fri, 12 Nov 2021 03:13:11 -0500 Received: from relmlor2.renesas.com ([210.160.252.172]:23962 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S234078AbhKLINJ (ORCPT ); Fri, 12 Nov 2021 03:13:09 -0500 X-IronPort-AV: E=Sophos;i="5.87,228,1631545200"; d="scan'208";a="100363462" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 12 Nov 2021 17:10:18 +0900 Received: from localhost.localdomain (unknown [10.226.93.91]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 6EF5842247ED; Fri, 12 Nov 2021 17:10:16 +0900 (JST) From: Biju Das To: Rob Herring Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [PATCH v2 4/4] arm64: dts: renesas: r9a07g044: Add OPP table Date: Fri, 12 Nov 2021 08:10:03 +0000 Message-Id: <20211112081003.15453-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211112081003.15453-1-biju.das.jz@bp.renesas.com> References: <20211112081003.15453-1-biju.das.jz@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add OPP table for RZ/G2L SoC. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar --- V1->v2: * Fixed typo cluster1_opp->cluster0_opp --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 43a5d359519a..ccb788de6654 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -42,6 +42,32 @@ clock-frequency = <0>; }; + cluster0_opp: opp_table { + compatible = "operating-points-v2"; + opp-shared; + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -63,6 +89,8 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A07G044_CLK_I>; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@100 { @@ -71,6 +99,8 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A07G044_CLK_I>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 { -- 2.17.1