From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27D0BC433F5 for ; Wed, 17 Nov 2021 12:41:52 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 965C861B9F for ; Wed, 17 Nov 2021 12:41:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 965C861B9F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=windriver.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 42C6B83305; Wed, 17 Nov 2021 13:41:48 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=windriver.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id D34E083531; Wed, 17 Nov 2021 13:41:32 +0100 (CET) Received: from mail5.wrs.com (mail5.windriver.com [192.103.53.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 5FD0C82F7E for ; Wed, 17 Nov 2021 13:41:21 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=windriver.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=Ovidiu.Panait@windriver.com Received: from ala-exchng01.corp.ad.wrs.com (ala-exchng01.corp.ad.wrs.com [147.11.82.252]) by mail5.wrs.com (8.15.2/8.15.2) with ESMTPS id 1AHCfJ6Y030882 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 17 Nov 2021 04:41:19 -0800 Received: from otp-linux03.wrs.com (128.224.125.155) by ala-exchng01.corp.ad.wrs.com (147.11.82.252) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Wed, 17 Nov 2021 04:41:17 -0800 From: Ovidiu Panait To: CC: , Ovidiu Panait Subject: [PATCH 10/10] microblaze: branch to base vector address on reset Date: Wed, 17 Nov 2021 14:40:26 +0200 Message-ID: <20211117124026.1410172-10-ovidiu.panait@windriver.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211117124026.1410172-1-ovidiu.panait@windriver.com> References: <20211117124026.1410172-1-ovidiu.panait@windriver.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [128.224.125.155] X-ClientProxiedBy: ala-exchng01.corp.ad.wrs.com (147.11.82.252) To ala-exchng01.corp.ad.wrs.com (147.11.82.252) X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.35 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Current code assumes that the vector base address is always at 0x0. However, this value is configurable for MicroBlaze using the CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR Kconfig option. Update the reset routines to branch to this location instead. Signed-off-by: Ovidiu Panait --- arch/microblaze/cpu/spl.c | 6 ++++-- drivers/sysreset/sysreset_microblaze.c | 6 ++++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c index 06d4af99b2..cea6d56f16 100644 --- a/arch/microblaze/cpu/spl.c +++ b/arch/microblaze/cpu/spl.c @@ -12,6 +12,7 @@ #include #include #include +#include bool boot_linux; @@ -54,8 +55,9 @@ int spl_start_uboot(void) int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - __asm__ __volatile__ ("mts rmsr, r0;" \ - "bra r0"); + __asm__ __volatile__ ( + "mts rmsr, r0;" \ + "brai " __stringify(CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR)); return 0; } diff --git a/drivers/sysreset/sysreset_microblaze.c b/drivers/sysreset/sysreset_microblaze.c index 514c95817f..83a7f77ac4 100644 --- a/drivers/sysreset/sysreset_microblaze.c +++ b/drivers/sysreset/sysreset_microblaze.c @@ -8,13 +8,15 @@ #include #include #include +#include static int microblaze_sysreset_request(struct udevice *dev, enum sysreset_t type) { puts("Microblaze soft reset sysreset\n"); - __asm__ __volatile__ (" mts rmsr, r0;" \ - "bra r0"); + __asm__ __volatile__ ( + "mts rmsr, r0;" \ + "brai " __stringify(CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR)); return -EINPROGRESS; } -- 2.25.1