Re: [RFC PATCH v4 net-next 17/23] pinctrl: microchip-sgpio: expose microchip_sgpio_core_probe interface

[kernel test robot <lkp@intel.com>]

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Hi Colin,

[FYI, it's a private test report for your RFC patch.]
[auto build test WARNING on net-next/master]

url:    https://github.com/0day-ci/linux/commits/Colin-Foster/add-support-for-VSC75XX-control-over-SPI/20211116-143245
base:   https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git 3ad4b7c81a992463c29ae130332c217607fe4452
config: openrisc-randconfig-r033-20211116 (attached as .config)
compiler: or1k-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/687241afbab24f5d57bb22b23b4a7c3ad941702e
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Colin-Foster/add-support-for-VSC75XX-control-over-SPI/20211116-143245
        git checkout 687241afbab24f5d57bb22b23b4a7c3ad941702e
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=openrisc 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/pinctrl/pinctrl-microchip-sgpio.c:838:5: warning: no previous prototype for 'microchip_sgpio_core_probe' [-Wmissing-prototypes]
     838 | int microchip_sgpio_core_probe(struct device *dev, struct device_node *node,
         |     ^~~~~~~~~~~~~~~~~~~~~~~~~~


vim +/microchip_sgpio_core_probe +838 drivers/pinctrl/pinctrl-microchip-sgpio.c

   837	
 > 838	int microchip_sgpio_core_probe(struct device *dev, struct device_node *node,
   839				       struct regmap *regmap, u32 offset)
   840	{
   841		int div_clock = 0, ret, port, i, nbanks;
   842		struct fwnode_handle *child, *fwnode;
   843		struct reset_control *reset;
   844		struct sgpio_priv *priv;
   845		struct clk *clk;
   846		u32 val;
   847	
   848		priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
   849		if (!priv)
   850			return -ENOMEM;
   851	
   852		priv->dev = dev;
   853		priv->dev_node = node;
   854	
   855		fwnode = of_fwnode_handle(node);
   856	
   857		reset = devm_reset_control_get_optional_shared(dev, "switch");
   858		if (IS_ERR(reset))
   859			return dev_err_probe(dev, PTR_ERR(reset), "Failed to get reset\n");
   860		reset_control_reset(reset);
   861	
   862		clk = devm_get_clk_from_child(dev, node, NULL);
   863		if (IS_ERR(clk))
   864			return dev_err_probe(dev, PTR_ERR(clk), "Failed to get clock\n");
   865	
   866		div_clock = clk_get_rate(clk);
   867		if (fwnode_property_read_u32(fwnode, "bus-frequency", &priv->clock))
   868			priv->clock = 12500000;
   869		if (priv->clock == 0 || priv->clock > (div_clock / 2)) {
   870			dev_err(dev, "Invalid frequency %d\n", priv->clock);
   871			return -EINVAL;
   872		}
   873	
   874		priv->regs = regmap;
   875		priv->regs_offset = 0;
   876		priv->properties = microchip_sgpio_match_from_node(node);
   877		priv->in.is_input = true;
   878	
   879		if (!priv->properties)
   880			return dev_err_probe(dev, -EINVAL, "No property match found\n");
   881	
   882		/* Get rest of device properties */
   883		ret = microchip_sgpio_get_ports(priv);
   884		if (ret)
   885			return ret;
   886	
   887		nbanks = fwnode_get_child_node_count(fwnode);
   888		if (nbanks != 2) {
   889			dev_err(dev, "Must have 2 banks (have %d)\n", nbanks);
   890			return -EINVAL;
   891		}
   892	
   893		i = 0;
   894		fwnode_for_each_child_node(fwnode, child) {
   895			ret = microchip_sgpio_register_bank(dev, priv, child, i++);
   896			if (ret) {
   897				fwnode_handle_put(child);
   898				return ret;
   899			}
   900		}
   901	
   902		if (priv->in.gpio.ngpio != priv->out.gpio.ngpio) {
   903			dev_err(dev, "Banks must have same GPIO count\n");
   904			return -ERANGE;
   905		}
   906	
   907		sgpio_configure_bitstream(priv);
   908	
   909		val = max(2U, div_clock / priv->clock);
   910		sgpio_configure_clock(priv, val);
   911	
   912		for (port = 0; port < SGPIO_BITS_PER_WORD; port++)
   913			sgpio_writel(priv, 0, REG_PORT_CONFIG, port);
   914		sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0);
   915	
   916		return 0;
   917	}
   918	EXPORT_SYMBOL(microchip_sgpio_core_probe);
   919	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

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