From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78367C433F5 for ; Thu, 18 Nov 2021 10:13:35 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B05F661B9F for ; Thu, 18 Nov 2021 10:13:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org B05F661B9F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C60D682F6F; Thu, 18 Nov 2021 11:13:24 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="eUjUxUoO"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id BB92A82F7E; Thu, 18 Nov 2021 11:13:19 +0100 (CET) Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 2D19082F4B for ; Thu, 18 Nov 2021 11:13:14 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jaimeliao.tw@gmail.com Received: by mail-pj1-x1035.google.com with SMTP id gt5so4731613pjb.1 for ; Thu, 18 Nov 2021 02:13:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hVpBpjYBkPvLewMeP2U0cJY+dGaJvUI12HKuC2CKZR0=; b=eUjUxUoO943iS7o9/9Ku/vQHY0meNxzx1nkKf1dihI7rV76R8Gnas207t2CUOUsfOK YrGE0kfY4zyUJbh7v2JT9O4+TrJrQeLDdz3JYAouvlhmqtogrX+2MLvC3JQ0mPH1jrjb rzO3B2oPIRZX7o8ev2pKOcQlkuzMkl2h4UJr8hYAWb/HULYu6789Gg1QtDiDj8MdzSzd U6OXSThQ8dfLyVVf/wwD8uBIymh5dl/8VP3FSJzFFwHRvQKGF2sQe43Cz+xm42mr1xFK 8t19GOBIOejQmMqMfw6oC76sHFYQ2fvWtDGnPxYMEtAoPfmYpEZXuJ5lECw0Vtuhd9uJ yE9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hVpBpjYBkPvLewMeP2U0cJY+dGaJvUI12HKuC2CKZR0=; b=sXjN0MzdDUj1sT6zs8NZWNk6wIzeoLTtpfEg+PJViqQYpe7/ArNQTv+DXrSIISmmby KQE7jNrRyPDt8FEztLy9TTKYqYLTJbUZIrec/puxitB+kBRrLldM8SiCXYkGykZcbN46 Ord+v3dPB7mJxCwLFHCjLke2FbxRCdzYu2RGujY+H5CegOlfOTV4V0XnP2fAMPk+WNzG 2hP4IzQXBKtZcYS3z1L0YzjZWauD1IEQCXUjHFOxweBYfqPmsneBA8NqwZ+QvPGRO5K7 3dYxY3AUe7nh7T6wwPCeUT4DWkIBHjPhLsV9/RRLoyzGhNcQ9iRzPftVGffJ5pNcUFGp o4sg== X-Gm-Message-State: AOAM530skOkK5ibPX1KHeByeCQXQnMgBTwn6lq9s6zuQA38NcUwOUKRp 3Gk0gS+Y5JtySvYpjDRdebQb0QbMaRE= X-Google-Smtp-Source: ABdhPJy7O3pdXiaq80lV0PloiqFuj7K95RO3ysD8P0WhsI7zDvfYfDddQXdu6/b2Ka2LVL8+LNkHGA== X-Received: by 2002:a17:902:aa82:b0:140:4655:b211 with SMTP id d2-20020a170902aa8200b001404655b211mr63788913plr.38.1637230392141; Thu, 18 Nov 2021 02:13:12 -0800 (PST) Received: from localhost.localdomain ([123.51.145.88]) by smtp.gmail.com with ESMTPSA id y18sm3137000pfa.142.2021.11.18.02.13.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Nov 2021 02:13:11 -0800 (PST) From: JaimeLiao To: u-boot@lists.denx.de, jagan@amarulasolutions.com, vigneshr@ti.com, p.yadav@ti.com Cc: zhengxunli@mxic.com.tw, jaimeliao@mxic.com.tw, JaimeLiao Subject: [PATCH v5 1/3] mtd: spi-nor: macronix: add support for Macronix Octal Date: Thu, 18 Nov 2021 18:13:01 +0800 Message-Id: <20211118101303.26061-2-jaimeliao.tw@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211118101303.26061-1-jaimeliao.tw@gmail.com> References: <20211118101303.26061-1-jaimeliao.tw@gmail.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.35 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Follow patch "f6adec1af4b2f5d3012480c6cdce7743b74a6156" for adding Macronix flash in Octal DTR mode. Enable Octal DTR mode with 20 dummy cycles to allow running at the maximum supported frequency. -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf Signed-off-by: JaimeLiao --- drivers/mtd/spi/spi-nor-core.c | 83 ++++++++++++++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 12 ++++- 2 files changed, 93 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index d5d905fa5a..0a6550984b 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3489,6 +3489,85 @@ static struct spi_nor_fixups mt35xu512aba_fixups = { }; #endif /* CONFIG_SPI_FLASH_MT35XU */ +#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX) +/** + * spi_nor_macronix_octal_dtr_enable() - set DTR OPI Enable bit in Configuration Register 2. + * @nor: pointer to a 'struct spi_nor' + * + * Set the DTR OPI Enable (DOPI) bit in Configuration Register 2. + * Bit 2 of Configuration Register 2 is the DOPI bit for Macronix like OPI memories. + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_macronix_octal_dtr_enable(struct spi_nor *nor) +{ + struct spi_mem_op op; + int ret; + u8 buf; + + ret = write_enable(nor); + if (ret) + return ret; + + buf = SPINOR_REG_MXIC_DC_20; + op = (struct spi_mem_op) + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1), + SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_DC, 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(1, &buf, 1)); + + ret = spi_mem_exec_op(nor->spi, &op); + if (ret) + return ret; + + ret = spi_nor_wait_till_ready(nor); + if (ret) + return ret; + + nor->read_dummy = MXIC_MAX_DC; + ret = write_enable(nor); + if (ret) + return ret; + + buf = SPINOR_REG_MXIC_OPI_DTR_EN; + op = (struct spi_mem_op) + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1), + SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_MODE, 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(1, &buf, 1)); + + ret = spi_mem_exec_op(nor->spi, &op); + if (ret) { + dev_err(nor->dev, "Failed to enable octal DTR mode\n"); + return ret; + } + nor->reg_proto = SNOR_PROTO_8_8_8_DTR; + + return 0; +} + +static void macronix_octal_default_init(struct spi_nor *nor) +{ + nor->octal_dtr_enable = spi_nor_macronix_octal_dtr_enable; +} + +static void macronix_octal_post_sfdp_fixup(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) +{ + /* + * Adding SNOR_HWCAPS_PP_8_8_8_DTR in hwcaps.mask when + * SPI_NOR_OCTAL_DTR_READ flag exists. + */ + if (params->hwcaps.mask & SNOR_HWCAPS_READ_8_8_8_DTR) + params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR; +} + +static struct spi_nor_fixups macronix_octal_fixups = { + .default_init = macronix_octal_default_init, + .post_sfdp = macronix_octal_post_sfdp_fixup, +}; +#endif /* CONFIG_SPI_FLASH_MACRONIX */ + /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed * @nor: pointer to a 'struct spi_nor' * @@ -3655,6 +3734,10 @@ void spi_nor_set_fixups(struct spi_nor *nor) if (!strcmp(nor->info->name, "mt35xu512aba")) nor->fixups = &mt35xu512aba_fixups; #endif + +#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX) + nor->fixups = ¯onix_octal_fixups; +#endif /* SPI_FLASH_MACRONIX */ } int spi_nor_scan(struct spi_nor *nor) diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 7ddc4ba2bf..8682368f2f 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -116,8 +116,16 @@ #define XSR_RDY BIT(7) /* Ready */ /* Used for Macronix and Winbond flashes. */ -#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ -#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */ +#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ +#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */ +#define SPINOR_OP_RD_CR2 0x71 /* Read configuration register 2 */ +#define SPINOR_OP_WR_CR2 0x72 /* Write configuration register 2 */ +#define SPINOR_OP_MXIC_DTR_RD 0xee /* Fast Read opcode in DTR mode */ +#define SPINOR_REG_MXIC_CR2_MODE 0x00000000 /* For setting octal DTR mode */ +#define SPINOR_REG_MXIC_OPI_DTR_EN 0x2 /* Enable Octal DTR */ +#define SPINOR_REG_MXIC_CR2_DC 0x00000300 /* For setting dummy cycles */ +#define SPINOR_REG_MXIC_DC_20 0x0 /* Setting dummy cycles to 20 */ +#define MXIC_MAX_DC 20 /* Maximum value of dummy cycles */ /* Used for Spansion flashes only. */ #define SPINOR_OP_BRWR 0x17 /* Bank register write */ -- 2.17.1