Re: [PATCH v2 0/4] Introduce pmu-events support for HiFive Unmatched

["João Mário Domingos" <joao.mario@tecnico.ulisboa.pt>]

On Thu, Nov 18, 2021 at 12:00:09AM -0800, Atish Patra wrote:
> On Wed, Nov 17, 2021 at 4:25 AM Nikita Shubin <nikita.shubin@maquefel.me> wrote:
> >
> > On Tue, 16 Nov 2021 15:48:08 +0000
> > João Mário Domingos <joao.mario@tecnico.ulisboa.pt> wrote:
> >
> > Hello Mario!
> >
> > Thank you for your patch series.
> >
> > I have reproduced your test with some u-boot dts tinkering, and got
> > similar results.
> >
> > However,
> >
> > >
> > > [1] https://github.com/atishp04/opensbi/tree/pmu_sscofpmf_v2
> >
> > OpenSBI sscofpmf has been merged.
> >
> > > [2] https://github.com/atishp04/u-boot/tree/hifive_unmatched_dt_pmu
> > > [5]
> > > https://github.com/atishp04/u-boot/blob/hifive_unmatched_dt_pmu/arch/riscv/dts/fu740-c000.dtsi
> >
> > Is missing the adaptation for OpenSBI bitmap patch for
> > "raw-event-to-mhpmcounters".
> 
> My patch was just an example and predates before the bitmap patch
> posted by Vincent.
> I will update the U-boot patch along with the next kernel version.
> 
> >
> > > [3] https://github.com/atishp04/linux/tree/riscv_pmu_v4
> >
> > The link is broken.
> >
> 
> Sorry. This should be
> https://github.com/atishp04/linux/tree/sbi_pmu_v4
> 
> > > [4]
> > > http://lists.infradead.org/pipermail/linux-riscv/2021-October/009408.html
> >
> > > [6]
> > > https://patchwork.ozlabs.org/project/opensbi/patch/20211105013301.27656-1-vincent.chen@sifive.com/
> > >
> >
> > There is a version 2 submitted, and it won't apply as require rebasing
> > and some renaming.
> >
> > Please share your u-boot dts changes - they should be small and provide
> > a common base for this series.
> >
> 
> Yes. That would be really helpful to have a DT path with all the
> entries for easier testing.
> 
> 

As the changes to the U-Boot are short I'm including them here, please tell me if I
should include them in other way. I merged my changes with Atish's own
patch to simplify the process.

diff -u b/arch/riscv/dts/fu740-c000.dtsi b/arch/riscv/dts/fu740-c000.dtsi
--- b/arch/riscv/dts/fu740-c000.dtsi
+++ b/arch/riscv/dts/fu740-c000.dtsi
@@ -141,6 +141,49 @@
                #size-cells = <2>;
                compatible = "sifive,fu740-c000", "sifive,fu740", "simple-bus";
                ranges;
+               pmu {
+                       compatible = "riscv,pmu";
+                       pmu,raw-event-to-mhpmcounters = <0x00000000 0x00000100 0x18
+                                                       0x00000000 0x00000200 0x18
+                                                       0x00000000 0x00000400 0x18
+                                                       0x00000000 0x00000800 0x18
+                                                       0x00000000 0x00001000 0x18
+                                                       0x00000000 0x00002000 0x18
+                                                       0x00000000 0x00004000 0x18
+                                                       0x00000000 0x00008000 0x18
+                                                       0x00000000 0x00010000 0x18
+                                                       0x00000000 0x00020000 0x18
+                                                       0x00000000 0x00040000 0x18
+                                                       0x00000000 0x00080000 0x18
+                                                       0x00000000 0x00100000 0x18
+                                                       0x00000000 0x00200000 0x18
+                                                       0x00000000 0x00400000 0x18
+                                                       0x00000000 0x00800000 0x18
+                                                       0x00000000 0x01000000 0x18
+                                                       0x00000000 0x02000000 0x18
+                                                       0x00000000 0x00000101 0x18
+                                                       0x00000000 0x00000201 0x18
+                                                       0x00000000 0x00000401 0x18
+                                                       0x00000000 0x00000801 0x18
+                                                       0x00000000 0x00001001 0x18
+                                                       0x00000000 0x00002001 0x18
+                                                       0x00000000 0x00004001 0x18
+                                                       0x00000000 0x00008001 0x18
+                                                       0x00000000 0x00010001 0x18
+                                                       0x00000000 0x00020001 0x18
+                                                       0x00000000 0x00040001 0x18
+                                                       0x00000000 0x00000102 0x18
+                                                       0x00000000 0x00000202 0x18
+                                                       0x00000000 0x00000402 0x18
+                                                       0x00000000 0x00000802 0x18
+                                                       0x00000000 0x00001002 0x18
+                                                       0x00000000 0x00002002 0x18>;
+                       pmu,event-to-mhpmcounters = <0x05 0x06 0x18
+                                                    0x10009 0x10009 0x18>;
+                       pmu,event-to-mhpmevent = <0x05 0x00000000 0x4000
+                                                 0x06 0x00000000 0x4001
+                                                 0x10008 0x00000000 0x102>;
+               };
                plic0: interrupt-controller@c000000 {
                        #interrupt-cells = <1>;
                        compatible = "sifive,plic-1.0.0";


> > Tested-by: Nikita Shubin <n.shubin@yadro.com>
> >
> > > Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
> > >
> > > This work was developed at INESC-ID, Instituto Superior Técnico,
> > > Universidade de Lisboa.
> > >
> > > ---
> > > Changes in v2:
> > >   - Fix compilation errors and warnings
> > >   - Remove space idents
> > >   - Correct formatting
> 
> 
> 
> > >
> > > João Mário Domingos (4):
> > >   RISC-V: Create unique identification for SoC PMU
> > >   RISC-V: Support CPUID for risc-v in perf
> > >   RISC-V: Added generic pmu-events mapfile
> > >   RISC-V: Added HiFive Unmatched PMU events
> > >
> > >  arch/riscv/kernel/sbi.c                       |  3 +
> > >  drivers/perf/riscv_pmu.c                      | 18 ++++
> > >  drivers/perf/riscv_pmu_sbi.c                  | 47 ++++++++++
> > >  tools/perf/arch/riscv/util/Build              |  1 +
> > >  tools/perf/arch/riscv/util/header.c           | 66 +++++++++++++
> > >  tools/perf/pmu-events/arch/riscv/mapfile.csv  | 15 +++
> > >  .../pmu-events/arch/riscv/riscv-generic.json  | 20 ++++
> > >  .../arch/riscv/sifive/u74/instructions.json   | 92
> > > +++++++++++++++++++ .../arch/riscv/sifive/u74/memory.json         |
> > > 32 +++++++ .../arch/riscv/sifive/u74/microarch.json      | 57
> > > ++++++++++++ 10 files changed, 351 insertions(+)
> > >  create mode 100644 tools/perf/arch/riscv/util/header.c
> > >  create mode 100644 tools/perf/pmu-events/arch/riscv/mapfile.csv
> > >  create mode 100644
> > > tools/perf/pmu-events/arch/riscv/riscv-generic.json create mode
> > > 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
> > > create mode 100644
> > > tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json create mode
> > > 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
> > >
> >
> >
> > _______________________________________________
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> 
> 
> 
> -- 
> Regards,
> Atish

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