* [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
@ 2021-11-22 21:14 Stanislav Lisovskiy
2021-11-22 21:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: Tile 4 plane format support (rev5) Patchwork
` (4 more replies)
0 siblings, 5 replies; 28+ messages in thread
From: Stanislav Lisovskiy @ 2021-11-22 21:14 UTC (permalink / raw)
To: intel-gfx
TileF(Tile4 in bspec) format is 4K tile organized into
64B subtiles with same basic shape as for legacy TileY
which will be supported by Display13.
v2: - Fixed wrong case condition(Jani Nikula)
- Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
v3: - s/I915_TILING_F/TILING_4/g
- s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
- Removed unneeded fencing code
v4: - Rebased, fixed merge conflict with new table-oriented
format modifier checking(Stan)
- Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
v5: - Still had to remove some Tile F mentionings
- Moved has_4tile from adlp to DG2(Ramalingam C)
- Check specifically for DG2, but not the Display13(Imre)
v6: - Moved Tile4 assocating struct for modifier/display to
the beginning(Imre Deak)
- Removed unneeded case I915_FORMAT_MOD_4_TILED modifier
checks(Imre Deak)
- Fixed I915_FORMAT_MOD_4_TILED to be 9 instead of 12
(Imre Deak)
v7: - Fixed display_ver to { 13, 13 }(Imre Deak)
- Removed redundant newline(Imre Deak)
Reviewed-by: Imre Deak <imre.deak@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_fb.c | 9 +++++++++
drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
.../drm/i915/display/intel_plane_initial.c | 1 +
.../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 1 +
include/uapi/drm/drm_fourcc.h | 8 ++++++++
11 files changed, 37 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f3c9208a30b1..7429965d3682 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7766,6 +7766,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state, struct int
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
+ case I915_FORMAT_MOD_4_TILED:
break;
default:
drm_dbg_kms(&i915->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index c4a743d0913f..b7f1ef62072c 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -139,6 +139,9 @@ struct intel_modifier_desc {
static const struct intel_modifier_desc intel_modifiers[] = {
{
+ .modifier = I915_FORMAT_MOD_4_TILED,
+ .display_ver = { 13, 13 },
+ }, {
.modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
.display_ver = { 12, 13 },
.plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_MC,
@@ -544,6 +547,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
return 128;
else
return 512;
+ case I915_FORMAT_MOD_4_TILED:
+ /*
+ * Each 4K tile consists of 64B(8*8) subtiles, with
+ * same shape as Y Tile(i.e 4*16B OWords)
+ */
+ return 128;
case I915_FORMAT_MOD_Y_TILED_CCS:
if (intel_fb_is_ccs_aux_plane(fb, color_plane))
return 128;
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index d0c34bc3af6c..0ceabe40d8c9 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -898,6 +898,7 @@ static bool tiling_is_valid(struct drm_i915_private *i915,
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
return DISPLAY_VER(i915) >= 9;
+ case I915_FORMAT_MOD_4_TILED:
case I915_FORMAT_MOD_X_TILED:
return true;
default:
diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index dcd698a02da2..d80855ee9b96 100644
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
+ case I915_FORMAT_MOD_4_TILED:
break;
default:
drm_dbg(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 28890876bdeb..e5cda5bcbde4 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
return PLANE_CTL_TILED_X;
case I915_FORMAT_MOD_Y_TILED:
return PLANE_CTL_TILED_Y;
+ case I915_FORMAT_MOD_4_TILED:
+ return PLANE_CTL_TILED_4;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
@@ -1971,9 +1973,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_Y216:
case DRM_FORMAT_XVYU12_16161616:
case DRM_FORMAT_XVYU16161616:
- if (modifier == DRM_FORMAT_MOD_LINEAR ||
- modifier == I915_FORMAT_MOD_X_TILED ||
- modifier == I915_FORMAT_MOD_Y_TILED)
+ if (!intel_fb_is_ccs_modifier(modifier))
return true;
fallthrough;
default:
@@ -2299,11 +2299,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
else
fb->modifier = I915_FORMAT_MOD_Y_TILED;
break;
- case PLANE_CTL_TILED_YF:
- if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
- fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
- else
- fb->modifier = I915_FORMAT_MOD_Yf_TILED;
+ case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
+ if (HAS_4TILE(dev_priv)) {
+ fb->modifier = I915_FORMAT_MOD_4_TILED;
+ } else {
+ if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
+ fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
+ else
+ fb->modifier = I915_FORMAT_MOD_Yf_TILED;
+ }
break;
default:
MISSING_CASE(tiling);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1bfadd9127fc..3d90bd732e91 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
#define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
+#define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
#define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
#define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
#define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f01cba4ec283..403d3a581ce7 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1044,6 +1044,7 @@ static const struct intel_device_info dg2_info = {
DGFX_FEATURES,
.graphics.rel = 55,
.media.rel = 55,
+ .has_4tile = 1,
PLATFORM(INTEL_DG2),
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3450818802c2..22d18a292430 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7284,6 +7284,7 @@ enum {
#define PLANE_CTL_TILED_X (1 << 10)
#define PLANE_CTL_TILED_Y (4 << 10)
#define PLANE_CTL_TILED_YF (5 << 10)
+#define PLANE_CTL_TILED_4 (5 << 10)
#define PLANE_CTL_ASYNC_FLIP (1 << 9)
#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 669f0d26c3c3..67177e18704a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -125,6 +125,7 @@ enum intel_ppgtt_type {
func(has_64bit_reloc); \
func(gpu_reset_clobbers_display); \
func(has_reset_engine); \
+ func(has_4tile); \
func(has_global_mocs); \
func(has_gt_uc); \
func(has_l3_dpf); \
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 01fa3fac1b57..167704f0acf0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5386,6 +5386,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
}
wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
+ modifier == I915_FORMAT_MOD_4_TILED ||
modifier == I915_FORMAT_MOD_Yf_TILED ||
modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 7f652c96845b..41184a94935d 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -564,6 +564,14 @@ extern "C" {
* pitch is required to be a multiple of 4 tile widths.
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
+/*
+ * Intel F-tiling(aka Tile4) layout
+ *
+ * This is a tiled layout using 4Kb tiles in row-major layout.
+ * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
+ * (16 bytes) chunks column-major..
+ */
+#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
--
2.24.1.485.gad05a3d8e5
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: Tile 4 plane format support (rev5)
2021-11-22 21:14 [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support Stanislav Lisovskiy
@ 2021-11-22 21:37 ` Patchwork
2021-11-22 21:40 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
4 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2021-11-22 21:37 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dg2: Tile 4 plane format support (rev5)
URL : https://patchwork.freedesktop.org/series/95715/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5aed8d5e5781 drm/i915/dg2: Tile 4 plane format support
-:28: WARNING:TYPO_SPELLING: 'assocating' may be misspelled - perhaps 'associating'?
#28:
v6: - Moved Tile4 assocating struct for modifier/display to
^^^^^^^^^^
total: 0 errors, 1 warnings, 0 checks, 129 lines checked
^ permalink raw reply [flat|nested] 28+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/dg2: Tile 4 plane format support (rev5)
2021-11-22 21:14 [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support Stanislav Lisovskiy
2021-11-22 21:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: Tile 4 plane format support (rev5) Patchwork
@ 2021-11-22 21:40 ` Patchwork
2021-11-22 22:08 ` [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support Nanley Chery
` (2 subsequent siblings)
4 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2021-11-22 21:40 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dg2: Tile 4 plane format support (rev5)
URL : https://patchwork.freedesktop.org/series/95715/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
2021-11-22 21:14 [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support Stanislav Lisovskiy
2021-11-22 21:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: Tile 4 plane format support (rev5) Patchwork
2021-11-22 21:40 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-11-22 22:08 ` Nanley Chery
2021-11-23 8:13 ` Lisovskiy, Stanislav
2021-11-23 16:20 ` Imre Deak
2021-11-22 22:14 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dg2: Tile 4 plane format support (rev5) Patchwork
2021-11-23 3:36 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
4 siblings, 2 replies; 28+ messages in thread
From: Nanley Chery @ 2021-11-22 22:08 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx, Nanley Chery
Hi Stanislav,
Are there IGT tests for this modifier?
On Mon, Nov 22, 2021 at 4:14 PM Stanislav Lisovskiy
<stanislav.lisovskiy@intel.com> wrote:
>
> TileF(Tile4 in bspec) format is 4K tile organized into
> 64B subtiles with same basic shape as for legacy TileY
> which will be supported by Display13.
>
> v2: - Fixed wrong case condition(Jani Nikula)
> - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
>
> v3: - s/I915_TILING_F/TILING_4/g
> - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
> - Removed unneeded fencing code
>
> v4: - Rebased, fixed merge conflict with new table-oriented
> format modifier checking(Stan)
> - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
>
> v5: - Still had to remove some Tile F mentionings
> - Moved has_4tile from adlp to DG2(Ramalingam C)
> - Check specifically for DG2, but not the Display13(Imre)
>
> v6: - Moved Tile4 assocating struct for modifier/display to
> the beginning(Imre Deak)
> - Removed unneeded case I915_FORMAT_MOD_4_TILED modifier
> checks(Imre Deak)
> - Fixed I915_FORMAT_MOD_4_TILED to be 9 instead of 12
> (Imre Deak)
>
> v7: - Fixed display_ver to { 13, 13 }(Imre Deak)
> - Removed redundant newline(Imre Deak)
>
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 1 +
> drivers/gpu/drm/i915/display/intel_fb.c | 9 +++++++++
> drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> .../drm/i915/display/intel_plane_initial.c | 1 +
> .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 1 +
> include/uapi/drm/drm_fourcc.h | 8 ++++++++
> 11 files changed, 37 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f3c9208a30b1..7429965d3682 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7766,6 +7766,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state, struct int
> case I915_FORMAT_MOD_X_TILED:
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Yf_TILED:
> + case I915_FORMAT_MOD_4_TILED:
> break;
> default:
> drm_dbg_kms(&i915->drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> index c4a743d0913f..b7f1ef62072c 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -139,6 +139,9 @@ struct intel_modifier_desc {
>
> static const struct intel_modifier_desc intel_modifiers[] = {
> {
> + .modifier = I915_FORMAT_MOD_4_TILED,
> + .display_ver = { 13, 13 },
I see that every other modifier has the plane_cap field set. Why is it
okay for it to be zero here?
> + }, {
> .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> .display_ver = { 12, 13 },
> .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_MC,
> @@ -544,6 +547,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> return 128;
> else
> return 512;
> + case I915_FORMAT_MOD_4_TILED:
> + /*
> + * Each 4K tile consists of 64B(8*8) subtiles, with
> + * same shape as Y Tile(i.e 4*16B OWords)
> + */
> + return 128;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> return 128;
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index d0c34bc3af6c..0ceabe40d8c9 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -898,6 +898,7 @@ static bool tiling_is_valid(struct drm_i915_private *i915,
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Yf_TILED:
> return DISPLAY_VER(i915) >= 9;
> + case I915_FORMAT_MOD_4_TILED:
The tile Y cases above check the display version. Should we do the same here?
> case I915_FORMAT_MOD_X_TILED:
> return true;
> default:
> diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> index dcd698a02da2..d80855ee9b96 100644
> --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
> case DRM_FORMAT_MOD_LINEAR:
> case I915_FORMAT_MOD_X_TILED:
> case I915_FORMAT_MOD_Y_TILED:
> + case I915_FORMAT_MOD_4_TILED:
> break;
> default:
> drm_dbg(&dev_priv->drm,
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 28890876bdeb..e5cda5bcbde4 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> return PLANE_CTL_TILED_X;
> case I915_FORMAT_MOD_Y_TILED:
> return PLANE_CTL_TILED_Y;
> + case I915_FORMAT_MOD_4_TILED:
> + return PLANE_CTL_TILED_4;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> @@ -1971,9 +1973,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> case DRM_FORMAT_Y216:
> case DRM_FORMAT_XVYU12_16161616:
> case DRM_FORMAT_XVYU16161616:
> - if (modifier == DRM_FORMAT_MOD_LINEAR ||
> - modifier == I915_FORMAT_MOD_X_TILED ||
> - modifier == I915_FORMAT_MOD_Y_TILED)
> + if (!intel_fb_is_ccs_modifier(modifier))
> return true;
> fallthrough;
> default:
> @@ -2299,11 +2299,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> else
> fb->modifier = I915_FORMAT_MOD_Y_TILED;
> break;
> - case PLANE_CTL_TILED_YF:
> - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> - else
> - fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
To be safe, maybe add a static_assert(PLANE_CTL_TILED_YF ==
PLANE_CTL_TILED_4); ?
> + if (HAS_4TILE(dev_priv)) {
> + fb->modifier = I915_FORMAT_MOD_4_TILED;
> + } else {
> + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> + else
> + fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> + }
> break;
> default:
> MISSING_CASE(tiling);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1bfadd9127fc..3d90bd732e91 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
>
> #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
> +#define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
> #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
> #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
> #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index f01cba4ec283..403d3a581ce7 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -1044,6 +1044,7 @@ static const struct intel_device_info dg2_info = {
> DGFX_FEATURES,
> .graphics.rel = 55,
> .media.rel = 55,
> + .has_4tile = 1,
> PLATFORM(INTEL_DG2),
> .platform_engine_mask =
> BIT(RCS0) | BIT(BCS0) |
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3450818802c2..22d18a292430 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7284,6 +7284,7 @@ enum {
> #define PLANE_CTL_TILED_X (1 << 10)
> #define PLANE_CTL_TILED_Y (4 << 10)
> #define PLANE_CTL_TILED_YF (5 << 10)
> +#define PLANE_CTL_TILED_4 (5 << 10)
> #define PLANE_CTL_ASYNC_FLIP (1 << 9)
> #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 669f0d26c3c3..67177e18704a 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -125,6 +125,7 @@ enum intel_ppgtt_type {
> func(has_64bit_reloc); \
> func(gpu_reset_clobbers_display); \
> func(has_reset_engine); \
> + func(has_4tile); \
> func(has_global_mocs); \
> func(has_gt_uc); \
> func(has_l3_dpf); \
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 01fa3fac1b57..167704f0acf0 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5386,6 +5386,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> }
>
> wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
> + modifier == I915_FORMAT_MOD_4_TILED ||
> modifier == I915_FORMAT_MOD_Yf_TILED ||
> modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 7f652c96845b..41184a94935d 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -564,6 +564,14 @@ extern "C" {
> * pitch is required to be a multiple of 4 tile widths.
> */
> #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> +/*
> + * Intel F-tiling(aka Tile4) layout
> + *
v4 and v5 attempted to get rid of the F-tile references, but this was
left behind.
> + * This is a tiled layout using 4Kb tiles in row-major layout.
> + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
> + * (16 bytes) chunks column-major..
I can't picture how tile 4 is organized from this description. Could
we update it?
Here's a draft I came up with when wondering how I might do this myself:
* This is a tiled layout using 4KB tiles in a row-major layout. It has the same
* shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
* only differs from Tile Y at the 256B granularity in between. At this
* granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
* of 64B x 8 rows.
-Nanley
> + */
> +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)
>
> /*
> * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> --
> 2.24.1.485.gad05a3d8e5
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dg2: Tile 4 plane format support (rev5)
2021-11-22 21:14 [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support Stanislav Lisovskiy
` (2 preceding siblings ...)
2021-11-22 22:08 ` [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support Nanley Chery
@ 2021-11-22 22:14 ` Patchwork
2021-11-23 3:36 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2021-11-22 22:14 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5209 bytes --]
== Series Details ==
Series: drm/i915/dg2: Tile 4 plane format support (rev5)
URL : https://patchwork.freedesktop.org/series/95715/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10916 -> Patchwork_21659
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/index.html
Participating hosts (42 -> 35)
------------------------------
Additional (1): fi-icl-u2
Missing (8): bat-dg1-6 fi-tgl-u2 bat-dg1-5 fi-bsw-cyan bat-adlp-6 bat-adlp-4 bat-jsl-2 bat-jsl-1
Known issues
------------
Here are the changes found in Patchwork_21659 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@semaphore:
- fi-bsw-nick: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/fi-bsw-nick/igt@amdgpu/amd_basic@semaphore.html
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> [SKIP][2] ([fdo#109315]) +17 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/fi-icl-u2/igt@amdgpu/amd_cs_nop@fork-gfx0.html
* igt@gem_huc_copy@huc-copy:
- fi-icl-u2: NOTRUN -> [SKIP][3] ([i915#2190])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/fi-icl-u2/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][4] ([i915#4555]) +3 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/fi-icl-u2/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: [PASS][5] -> [INCOMPLETE][6] ([i915#2940])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: NOTRUN -> [SKIP][7] ([fdo#111827]) +8 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: NOTRUN -> [SKIP][8] ([fdo#109278]) +2 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2: NOTRUN -> [SKIP][9] ([fdo#109285])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@prime_vgem@basic-userptr:
- fi-icl-u2: NOTRUN -> [SKIP][10] ([i915#3301])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/fi-icl-u2/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-bsw-kefka: NOTRUN -> [FAIL][11] ([fdo#109271] / [i915#1436] / [i915#3428] / [i915#4312])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/fi-bsw-kefka/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_selftest@live@execlists:
- fi-bsw-nick: [INCOMPLETE][12] ([i915#2940]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/fi-bsw-nick/igt@i915_selftest@live@execlists.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/fi-bsw-nick/igt@i915_selftest@live@execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4555]: https://gitlab.freedesktop.org/drm/intel/issues/4555
Build changes
-------------
* Linux: CI_DRM_10916 -> Patchwork_21659
CI-20190529: 20190529
CI_DRM_10916: 876217519d26774d843128cc66640ae501a5c38d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6286: cdcbf81f734fdb1d102e84490e49e9fec23760cd @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21659: 5aed8d5e578103edb32ed0c1648f8f629980c290 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
5aed8d5e5781 drm/i915/dg2: Tile 4 plane format support
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/index.html
[-- Attachment #2: Type: text/html, Size: 6150 bytes --]
^ permalink raw reply [flat|nested] 28+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dg2: Tile 4 plane format support (rev5)
2021-11-22 21:14 [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support Stanislav Lisovskiy
` (3 preceding siblings ...)
2021-11-22 22:14 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dg2: Tile 4 plane format support (rev5) Patchwork
@ 2021-11-23 3:36 ` Patchwork
4 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2021-11-23 3:36 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30271 bytes --]
== Series Details ==
Series: drm/i915/dg2: Tile 4 plane format support (rev5)
URL : https://patchwork.freedesktop.org/series/95715/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10916_full -> Patchwork_21659_full
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_21659_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21659_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21659_full:
### IGT changes ###
#### Warnings ####
* igt@kms_content_protection@mei_interface:
- shard-kbl: [SKIP][1] ([fdo#109271]) -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-kbl2/igt@kms_content_protection@mei_interface.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-kbl7/igt@kms_content_protection@mei_interface.html
* igt@kms_sysfs_edid_timing:
- shard-kbl: [FAIL][3] ([IGT#2]) -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-kbl7/igt@kms_sysfs_edid_timing.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-kbl7/igt@kms_sysfs_edid_timing.html
Known issues
------------
Here are the changes found in Patchwork_21659_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +3 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-kbl4/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-kbl6/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-skl: NOTRUN -> [SKIP][7] ([fdo#109271]) +332 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-skl1/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-kbl: NOTRUN -> [FAIL][8] ([i915#2842])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-kbl2/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-iclb: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-iclb3/igt@gem_exec_fair@basic-pace@bcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-iclb5/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][13] -> [FAIL][14] ([i915#2849])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_suspend@basic-s0:
- shard-tglb: [PASS][15] -> [INCOMPLETE][16] ([i915#456])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-tglb1/igt@gem_exec_suspend@basic-s0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-tglb7/igt@gem_exec_suspend@basic-s0.html
* igt@gem_pread@exhaustion:
- shard-kbl: NOTRUN -> [WARN][17] ([i915#2658])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-kbl6/igt@gem_pread@exhaustion.html
* igt@gem_pxp@regular-baseline-src-copy-readible:
- shard-kbl: NOTRUN -> [SKIP][18] ([fdo#109271]) +104 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-kbl6/igt@gem_pxp@regular-baseline-src-copy-readible.html
* igt@gem_userptr_blits@vma-merge:
- shard-skl: NOTRUN -> [FAIL][19] ([i915#3318])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-skl1/igt@gem_userptr_blits@vma-merge.html
* igt@gen9_exec_parse@valid-registers:
- shard-tglb: NOTRUN -> [SKIP][20] ([i915#2856])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-tglb5/igt@gen9_exec_parse@valid-registers.html
* igt@i915_pm_dc@dc6-dpms:
- shard-skl: NOTRUN -> [FAIL][21] ([i915#454])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-skl10/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_big_fb@linear-32bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][22] ([fdo#111614])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-tglb5/igt@kms_big_fb@linear-32bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-180:
- shard-glk: [PASS][23] -> [DMESG-WARN][24] ([i915#118]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-glk5/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-glk8/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][25] ([i915#3743]) +3 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-skl8/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-skl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#3777]) +1 similar issue
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-skl9/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@yf-tiled-addfb:
- shard-tglb: NOTRUN -> [SKIP][27] ([fdo#111615])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-tglb5/igt@kms_big_fb@yf-tiled-addfb.html
* igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#3886]) +5 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-kbl6/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#3886]) +14 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-skl7/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][30] ([i915#3689] / [i915#3886])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-tglb5/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][31] ([i915#3689])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-tglb3/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_ccs.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#3886]) +2 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-apl3/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@hdmi-hpd-for-each-pipe:
- shard-kbl: NOTRUN -> [SKIP][33] ([fdo#109271] / [fdo#111827]) +6 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-kbl6/igt@kms_chamelium@hdmi-hpd-for-each-pipe.html
* igt@kms_chamelium@vga-hpd-after-suspend:
- shard-skl: NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +24 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-skl9/igt@kms_chamelium@vga-hpd-after-suspend.html
* igt@kms_color@pipe-b-ctm-0-5:
- shard-skl: [PASS][35] -> [DMESG-WARN][36] ([i915#1982])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-skl6/igt@kms_color@pipe-b-ctm-0-5.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-skl3/igt@kms_color@pipe-b-ctm-0-5.html
* igt@kms_color_chamelium@pipe-a-ctm-limited-range:
- shard-apl: NOTRUN -> [SKIP][37] ([fdo#109271] / [fdo#111827]) +6 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-apl4/igt@kms_color_chamelium@pipe-a-ctm-limited-range.html
* igt@kms_content_protection@srm:
- shard-kbl: NOTRUN -> [TIMEOUT][38] ([i915#1319])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-kbl2/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@pipe-b-cursor-32x10-rapid-movement:
- shard-tglb: NOTRUN -> [SKIP][39] ([i915#3359])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-tglb5/igt@kms_cursor_crc@pipe-b-cursor-32x10-rapid-movement.html
* igt@kms_cursor_crc@pipe-b-cursor-512x512-random:
- shard-tglb: NOTRUN -> [SKIP][40] ([fdo#109279] / [i915#3359])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-tglb5/igt@kms_cursor_crc@pipe-b-cursor-512x512-random.html
* igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
- shard-skl: [PASS][41] -> [FAIL][42] ([i915#2346])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
* igt@kms_cursor_legacy@pipe-d-torture-bo:
- shard-kbl: NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#533])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-kbl2/igt@kms_cursor_legacy@pipe-d-torture-bo.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled:
- shard-snb: NOTRUN -> [SKIP][44] ([fdo#109271]) +4 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-snb5/igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [PASS][45] -> [INCOMPLETE][46] ([i915#180] / [i915#1982])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-apl7/igt@kms_fbcon_fbt@fbc-suspend.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-apl2/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: [PASS][47] -> [FAIL][48] ([i915#79])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-skl: NOTRUN -> [FAIL][49] ([i915#79]) +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-apl: [PASS][50] -> [DMESG-WARN][51] ([i915#180]) +4 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-apl1/igt@kms_flip@flip-vs-suspend@a-dp1.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-apl8/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1:
- shard-skl: [PASS][52] -> [FAIL][53] ([i915#2122]) +2 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-skl6/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-skl3/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-skl: NOTRUN -> [SKIP][54] ([fdo#109271] / [i915#2672])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-skl7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
- shard-apl: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#2672])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-apl4/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt:
- shard-tglb: NOTRUN -> [SKIP][56] ([fdo#111825]) +4 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: NOTRUN -> [FAIL][57] ([i915#1188])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-skl1/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#533]) +2 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-skl7/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#533])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-apl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-skl: NOTRUN -> [FAIL][60] ([fdo#108145] / [i915#265])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][61] ([fdo#108145] / [i915#265]) +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-apl4/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-kbl: NOTRUN -> [FAIL][62] ([fdo#108145] / [i915#265]) +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-kbl6/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][63] ([i915#265])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-kbl6/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][64] ([i915#265])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-apl4/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_lowres@pipe-b-tiling-x:
- shard-tglb: NOTRUN -> [SKIP][65] ([i915#3536])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-tglb5/igt@kms_plane_lowres@pipe-b-tiling-x.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
- shard-skl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#2733])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-skl7/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-0:
- shard-apl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#658]) +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-apl4/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-2:
- shard-skl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#658]) +5 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-skl10/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
- shard-kbl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#658])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-kbl6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][70] -> [SKIP][71] ([fdo#109441]) +3 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-iclb7/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> [FAIL][72] ([IGT#2])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-apl6/igt@kms_sysfs_edid_timing.html
- shard-skl: NOTRUN -> [FAIL][73] ([IGT#2])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-skl9/igt@kms_sysfs_edid_timing.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-skl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#2437])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-skl7/igt@kms_writeback@writeback-invalid-parameters.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-apl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#2437])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-apl3/igt@kms_writeback@writeback-pixel-formats.html
* igt@perf@polling-parameterized:
- shard-skl: [PASS][76] -> [FAIL][77] ([i915#1542])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-skl6/igt@perf@polling-parameterized.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-skl10/igt@perf@polling-parameterized.html
* igt@perf@polling-small-buf:
- shard-skl: NOTRUN -> [FAIL][78] ([i915#1722])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-skl7/igt@perf@polling-small-buf.html
* igt@perf_pmu@rc6-suspend:
- shard-kbl: NOTRUN -> [DMESG-WARN][79] ([i915#180])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-kbl6/igt@perf_pmu@rc6-suspend.html
* igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name:
- shard-apl: NOTRUN -> [SKIP][80] ([fdo#109271]) +85 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-apl7/igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name.html
* igt@sysfs_clients@fair-3:
- shard-skl: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#2994]) +3 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-skl7/igt@sysfs_clients@fair-3.html
- shard-apl: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#2994])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-apl7/igt@sysfs_clients@fair-3.html
* igt@sysfs_clients@recycle:
- shard-tglb: NOTRUN -> [SKIP][83] ([i915#2994])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-tglb3/igt@sysfs_clients@recycle.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [FAIL][84] ([i915#2842]) -> [PASS][85]
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-iclb4/igt@gem_exec_fair@basic-none-share@rcs0.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-iclb2/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [FAIL][86] ([i915#2842]) -> [PASS][87]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-kbl2/igt@gem_exec_fair@basic-pace@vecs0.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [FAIL][88] ([i915#2842]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-glk9/igt@gem_exec_fair@basic-throttle@rcs0.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-glk7/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [DMESG-WARN][90] ([i915#180]) -> [PASS][91] +3 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-apl4/igt@gem_workarounds@suspend-resume-context.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-apl4/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][92] ([i915#454]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-iclb3/igt@i915_pm_dc@dc6-psr.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-tglb: [WARN][94] ([i915#2681] / [i915#2684]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-tglb1/igt@i915_pm_rc6_residency@rc6-fence.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-tglb6/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [INCOMPLETE][96] ([i915#3921]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-snb6/igt@i915_selftest@live@hangcheck.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-snb5/igt@i915_selftest@live@hangcheck.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-0:
- shard-glk: [DMESG-WARN][98] ([i915#118]) -> [PASS][99] +2 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-glk9/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-glk7/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-yf_tiled_ccs:
- shard-glk: [DMESG-WARN][100] ([i915#118] / [i915#1888]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-glk4/igt@kms_ccs@pipe-a-crc-primary-rotation-180-yf_tiled_ccs.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-glk9/igt@kms_ccs@pipe-a-crc-primary-rotation-180-yf_tiled_ccs.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-iclb: [FAIL][102] ([i915#2346]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-iclb6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@pipe-b-forked-bo:
- shard-kbl: [INCOMPLETE][104] -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-kbl7/igt@kms_cursor_legacy@pipe-b-forked-bo.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-kbl6/igt@kms_cursor_legacy@pipe-b-forked-bo.html
* igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled:
- shard-glk: [FAIL][106] -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-glk9/igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-glk7/igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [INCOMPLETE][108] ([i915#180] / [i915#636]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-kbl6/igt@kms_fbcon_fbt@fbc-suspend.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-kbl2/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1:
- shard-glk: [FAIL][110] ([i915#79]) -> [PASS][111] +1 similar issue
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-glk9/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-glk7/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile:
- shard-iclb: [SKIP][112] ([i915#3701]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-iclb7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw:
- shard-glk: [FAIL][114] ([i915#2546]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-glk1/igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-glk3/igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-tglb: [INCOMPLETE][116] ([i915#1373] / [i915#2828]) -> [PASS][117]
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-tglb7/igt@kms_hdr@bpc-switch-suspend.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-tglb5/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-iclb: [SKIP][118] ([fdo#109441]) -> [PASS][119] +3 similar issues
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-iclb6/igt@kms_psr@psr2_cursor_plane_onoff.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html
* igt@perf@short-reads:
- shard-skl: [FAIL][120] ([i915#51]) -> [PASS][121]
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-skl10/igt@perf@short-reads.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-skl4/igt@perf@short-reads.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][122] ([i915#2684]) -> [WARN][123] ([i915#1804] / [i915#2684])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-iclb2/igt@i915_pm_rc6_residency@rc6-fence.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-iclb7/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1:
- shard-iclb: [SKIP][124] ([i915#2920]) -> [SKIP][125] ([i915#658]) +3 similar issues
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-iclb7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4:
- shard-iclb: [SKIP][126] ([i915#658]) -> [SKIP][127] ([i915#2920]) +1 similar issue
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-iclb4/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [FAIL][128] ([i915#4148]) -> [SKIP][129] ([fdo#109642] / [fdo#111068] / [i915#658])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-iclb2/igt@kms_psr2_su@page_flip.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-iclb7/igt@kms_psr2_su@page_flip.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / [i915#4312] / [i915#602] / [i915#92]) -> ([FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138], [FAIL][139], [FAIL][140]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / [i915#4312] / [i915#602])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-kbl6/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-kbl6/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-kbl6/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-kbl2/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-kbl4/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-kbl6/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-kbl6/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-kbl6/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-kbl6/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-kbl6/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/shard-kbl6/igt@runner@aborted.html
- shard-apl: ([FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#3363] / [i915#4312]) -> ([FAIL][149], [FAIL][150], [FAIL][151], [FAIL][152], [FAIL][153], [FAIL][154], [FAIL][155], [FAIL][156]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / [i915#4312])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10916/shard-apl8/igt@runner@aborted.html
[142]: https://intel-g
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21659/index.html
[-- Attachment #2: Type: text/html, Size: 33962 bytes --]
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
2021-11-22 22:08 ` [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support Nanley Chery
@ 2021-11-23 8:13 ` Lisovskiy, Stanislav
2021-11-23 12:41 ` Chery, Nanley G
2021-11-23 16:20 ` Imre Deak
1 sibling, 1 reply; 28+ messages in thread
From: Lisovskiy, Stanislav @ 2021-11-23 8:13 UTC (permalink / raw)
To: Nanley Chery; +Cc: intel-gfx, Nanley Chery
On Mon, Nov 22, 2021 at 05:08:31PM -0500, Nanley Chery wrote:
> Hi Stanislav,
>
> Are there IGT tests for this modifier?
Hi Nanley
Yes, there should be plenty of those, not sure they
are all sent to upstream though.
We have a separate team doing this.
That modifier should be added to kms_plane_multiple
and many others
Stan
>
> On Mon, Nov 22, 2021 at 4:14 PM Stanislav Lisovskiy
> <stanislav.lisovskiy@intel.com> wrote:
> >
> > TileF(Tile4 in bspec) format is 4K tile organized into
> > 64B subtiles with same basic shape as for legacy TileY
> > which will be supported by Display13.
> >
> > v2: - Fixed wrong case condition(Jani Nikula)
> > - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
> >
> > v3: - s/I915_TILING_F/TILING_4/g
> > - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
> > - Removed unneeded fencing code
> >
> > v4: - Rebased, fixed merge conflict with new table-oriented
> > format modifier checking(Stan)
> > - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
> >
> > v5: - Still had to remove some Tile F mentionings
> > - Moved has_4tile from adlp to DG2(Ramalingam C)
> > - Check specifically for DG2, but not the Display13(Imre)
> >
> > v6: - Moved Tile4 assocating struct for modifier/display to
> > the beginning(Imre Deak)
> > - Removed unneeded case I915_FORMAT_MOD_4_TILED modifier
> > checks(Imre Deak)
> > - Fixed I915_FORMAT_MOD_4_TILED to be 9 instead of 12
> > (Imre Deak)
> >
> > v7: - Fixed display_ver to { 13, 13 }(Imre Deak)
> > - Removed redundant newline(Imre Deak)
> >
> > Reviewed-by: Imre Deak <imre.deak@intel.com>
> > Cc: Imre Deak <imre.deak@intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 1 +
> > drivers/gpu/drm/i915/display/intel_fb.c | 9 +++++++++
> > drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> > .../drm/i915/display/intel_plane_initial.c | 1 +
> > .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/i915_pci.c | 1 +
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_device_info.h | 1 +
> > drivers/gpu/drm/i915/intel_pm.c | 1 +
> > include/uapi/drm/drm_fourcc.h | 8 ++++++++
> > 11 files changed, 37 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index f3c9208a30b1..7429965d3682 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -7766,6 +7766,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state, struct int
> > case I915_FORMAT_MOD_X_TILED:
> > case I915_FORMAT_MOD_Y_TILED:
> > case I915_FORMAT_MOD_Yf_TILED:
> > + case I915_FORMAT_MOD_4_TILED:
> > break;
> > default:
> > drm_dbg_kms(&i915->drm,
> > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> > index c4a743d0913f..b7f1ef62072c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > @@ -139,6 +139,9 @@ struct intel_modifier_desc {
> >
> > static const struct intel_modifier_desc intel_modifiers[] = {
> > {
> > + .modifier = I915_FORMAT_MOD_4_TILED,
> > + .display_ver = { 13, 13 },
>
> I see that every other modifier has the plane_cap field set. Why is it
> okay for it to be zero here?
>
> > + }, {
> > .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> > .display_ver = { 12, 13 },
> > .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_MC,
> > @@ -544,6 +547,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> > return 128;
> > else
> > return 512;
> > + case I915_FORMAT_MOD_4_TILED:
> > + /*
> > + * Each 4K tile consists of 64B(8*8) subtiles, with
> > + * same shape as Y Tile(i.e 4*16B OWords)
> > + */
> > + return 128;
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> > return 128;
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index d0c34bc3af6c..0ceabe40d8c9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -898,6 +898,7 @@ static bool tiling_is_valid(struct drm_i915_private *i915,
> > case I915_FORMAT_MOD_Y_TILED:
> > case I915_FORMAT_MOD_Yf_TILED:
> > return DISPLAY_VER(i915) >= 9;
> > + case I915_FORMAT_MOD_4_TILED:
>
> The tile Y cases above check the display version. Should we do the same here?
>
> > case I915_FORMAT_MOD_X_TILED:
> > return true;
> > default:
> > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > index dcd698a02da2..d80855ee9b96 100644
> > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
> > case DRM_FORMAT_MOD_LINEAR:
> > case I915_FORMAT_MOD_X_TILED:
> > case I915_FORMAT_MOD_Y_TILED:
> > + case I915_FORMAT_MOD_4_TILED:
> > break;
> > default:
> > drm_dbg(&dev_priv->drm,
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 28890876bdeb..e5cda5bcbde4 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> > return PLANE_CTL_TILED_X;
> > case I915_FORMAT_MOD_Y_TILED:
> > return PLANE_CTL_TILED_Y;
> > + case I915_FORMAT_MOD_4_TILED:
> > + return PLANE_CTL_TILED_4;
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> > @@ -1971,9 +1973,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> > case DRM_FORMAT_Y216:
> > case DRM_FORMAT_XVYU12_16161616:
> > case DRM_FORMAT_XVYU16161616:
> > - if (modifier == DRM_FORMAT_MOD_LINEAR ||
> > - modifier == I915_FORMAT_MOD_X_TILED ||
> > - modifier == I915_FORMAT_MOD_Y_TILED)
> > + if (!intel_fb_is_ccs_modifier(modifier))
> > return true;
> > fallthrough;
> > default:
> > @@ -2299,11 +2299,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> > else
> > fb->modifier = I915_FORMAT_MOD_Y_TILED;
> > break;
> > - case PLANE_CTL_TILED_YF:
> > - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > - else
> > - fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
>
> To be safe, maybe add a static_assert(PLANE_CTL_TILED_YF ==
> PLANE_CTL_TILED_4); ?
>
> > + if (HAS_4TILE(dev_priv)) {
> > + fb->modifier = I915_FORMAT_MOD_4_TILED;
> > + } else {
> > + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > + else
> > + fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > + }
> > break;
> > default:
> > MISSING_CASE(tiling);
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 1bfadd9127fc..3d90bd732e91 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
> >
> > #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
> > +#define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
> > #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
> > #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
> > #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > index f01cba4ec283..403d3a581ce7 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -1044,6 +1044,7 @@ static const struct intel_device_info dg2_info = {
> > DGFX_FEATURES,
> > .graphics.rel = 55,
> > .media.rel = 55,
> > + .has_4tile = 1,
> > PLATFORM(INTEL_DG2),
> > .platform_engine_mask =
> > BIT(RCS0) | BIT(BCS0) |
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 3450818802c2..22d18a292430 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7284,6 +7284,7 @@ enum {
> > #define PLANE_CTL_TILED_X (1 << 10)
> > #define PLANE_CTL_TILED_Y (4 << 10)
> > #define PLANE_CTL_TILED_YF (5 << 10)
> > +#define PLANE_CTL_TILED_4 (5 << 10)
> > #define PLANE_CTL_ASYNC_FLIP (1 << 9)
> > #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> > #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> > index 669f0d26c3c3..67177e18704a 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -125,6 +125,7 @@ enum intel_ppgtt_type {
> > func(has_64bit_reloc); \
> > func(gpu_reset_clobbers_display); \
> > func(has_reset_engine); \
> > + func(has_4tile); \
> > func(has_global_mocs); \
> > func(has_gt_uc); \
> > func(has_l3_dpf); \
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 01fa3fac1b57..167704f0acf0 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -5386,6 +5386,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> > }
> >
> > wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
> > + modifier == I915_FORMAT_MOD_4_TILED ||
> > modifier == I915_FORMAT_MOD_Yf_TILED ||
> > modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > index 7f652c96845b..41184a94935d 100644
> > --- a/include/uapi/drm/drm_fourcc.h
> > +++ b/include/uapi/drm/drm_fourcc.h
> > @@ -564,6 +564,14 @@ extern "C" {
> > * pitch is required to be a multiple of 4 tile widths.
> > */
> > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> > +/*
> > + * Intel F-tiling(aka Tile4) layout
> > + *
>
> v4 and v5 attempted to get rid of the F-tile references, but this was
> left behind.
>
> > + * This is a tiled layout using 4Kb tiles in row-major layout.
> > + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
> > + * (16 bytes) chunks column-major..
>
> I can't picture how tile 4 is organized from this description. Could
> we update it?
> Here's a draft I came up with when wondering how I might do this myself:
>
> * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
> * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
> * only differs from Tile Y at the 256B granularity in between. At this
> * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
> * of 64B x 8 rows.
>
> -Nanley
>
> > + */
> > +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)
> >
> > /*
> > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > --
> > 2.24.1.485.gad05a3d8e5
> >
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
2021-11-23 8:13 ` Lisovskiy, Stanislav
@ 2021-11-23 12:41 ` Chery, Nanley G
2021-11-23 13:36 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 28+ messages in thread
From: Chery, Nanley G @ 2021-11-23 12:41 UTC (permalink / raw)
To: Lisovskiy, Stanislav, Nanley Chery; +Cc: intel-gfx
> -----Original Message-----
> From: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com>
> Sent: Tuesday, November 23, 2021 3:14 AM
> To: Nanley Chery <nanleychery@gmail.com>
> Cc: intel-gfx@lists.freedesktop.org; Chery, Nanley G
> <nanley.g.chery@intel.com>
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
>
> On Mon, Nov 22, 2021 at 05:08:31PM -0500, Nanley Chery wrote:
> > Hi Stanislav,
> >
> > Are there IGT tests for this modifier?
>
> Hi Nanley
>
> Yes, there should be plenty of those, not sure they
> are all sent to upstream though.
> We have a separate team doing this.
> That modifier should be added to kms_plane_multiple
> and many others
>
Okay, I'll be on the lookout for them.
> Stan
>
Looks like you missed the other review comments I left in my prior email.
-Nanley
> >
> > On Mon, Nov 22, 2021 at 4:14 PM Stanislav Lisovskiy
> > <stanislav.lisovskiy@intel.com> wrote:
> > >
> > > TileF(Tile4 in bspec) format is 4K tile organized into
> > > 64B subtiles with same basic shape as for legacy TileY
> > > which will be supported by Display13.
> > >
> > > v2: - Fixed wrong case condition(Jani Nikula)
> > > - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
> > >
> > > v3: - s/I915_TILING_F/TILING_4/g
> > > - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
> > > - Removed unneeded fencing code
> > >
> > > v4: - Rebased, fixed merge conflict with new table-oriented
> > > format modifier checking(Stan)
> > > - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
> > >
> > > v5: - Still had to remove some Tile F mentionings
> > > - Moved has_4tile from adlp to DG2(Ramalingam C)
> > > - Check specifically for DG2, but not the Display13(Imre)
> > >
> > > v6: - Moved Tile4 assocating struct for modifier/display to
> > > the beginning(Imre Deak)
> > > - Removed unneeded case I915_FORMAT_MOD_4_TILED modifier
> > > checks(Imre Deak)
> > > - Fixed I915_FORMAT_MOD_4_TILED to be 9 instead of 12
> > > (Imre Deak)
> > >
> > > v7: - Fixed display_ver to { 13, 13 }(Imre Deak)
> > > - Removed redundant newline(Imre Deak)
> > >
> > > Reviewed-by: Imre Deak <imre.deak@intel.com>
> > > Cc: Imre Deak <imre.deak@intel.com>
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 1 +
> > > drivers/gpu/drm/i915/display/intel_fb.c | 9 +++++++++
> > > drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> > > .../drm/i915/display/intel_plane_initial.c | 1 +
> > > .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
> > > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > > drivers/gpu/drm/i915/i915_pci.c | 1 +
> > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > drivers/gpu/drm/i915/intel_device_info.h | 1 +
> > > drivers/gpu/drm/i915/intel_pm.c | 1 +
> > > include/uapi/drm/drm_fourcc.h | 8 ++++++++
> > > 11 files changed, 37 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> > > index f3c9208a30b1..7429965d3682 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -7766,6 +7766,7 @@ static int intel_atomic_check_async(struct
> intel_atomic_state *state, struct int
> > > case I915_FORMAT_MOD_X_TILED:
> > > case I915_FORMAT_MOD_Y_TILED:
> > > case I915_FORMAT_MOD_Yf_TILED:
> > > + case I915_FORMAT_MOD_4_TILED:
> > > break;
> > > default:
> > > drm_dbg_kms(&i915->drm,
> > > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
> b/drivers/gpu/drm/i915/display/intel_fb.c
> > > index c4a743d0913f..b7f1ef62072c 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > > @@ -139,6 +139,9 @@ struct intel_modifier_desc {
> > >
> > > static const struct intel_modifier_desc intel_modifiers[] = {
> > > {
> > > + .modifier = I915_FORMAT_MOD_4_TILED,
> > > + .display_ver = { 13, 13 },
> >
> > I see that every other modifier has the plane_cap field set. Why is it
> > okay for it to be zero here?
> >
> > > + }, {
> > > .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> > > .display_ver = { 12, 13 },
> > > .plane_caps = INTEL_PLANE_CAP_TILING_Y |
> INTEL_PLANE_CAP_CCS_MC,
> > > @@ -544,6 +547,12 @@ intel_tile_width_bytes(const struct
> drm_framebuffer *fb, int color_plane)
> > > return 128;
> > > else
> > > return 512;
> > > + case I915_FORMAT_MOD_4_TILED:
> > > + /*
> > > + * Each 4K tile consists of 64B(8*8) subtiles, with
> > > + * same shape as Y Tile(i.e 4*16B OWords)
> > > + */
> > > + return 128;
> > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> > > return 128;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > index d0c34bc3af6c..0ceabe40d8c9 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > @@ -898,6 +898,7 @@ static bool tiling_is_valid(struct drm_i915_private
> *i915,
> > > case I915_FORMAT_MOD_Y_TILED:
> > > case I915_FORMAT_MOD_Yf_TILED:
> > > return DISPLAY_VER(i915) >= 9;
> > > + case I915_FORMAT_MOD_4_TILED:
> >
> > The tile Y cases above check the display version. Should we do the same here?
> >
> > > case I915_FORMAT_MOD_X_TILED:
> > > return true;
> > > default:
> > > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > index dcd698a02da2..d80855ee9b96 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
> > > case DRM_FORMAT_MOD_LINEAR:
> > > case I915_FORMAT_MOD_X_TILED:
> > > case I915_FORMAT_MOD_Y_TILED:
> > > + case I915_FORMAT_MOD_4_TILED:
> > > break;
> > > default:
> > > drm_dbg(&dev_priv->drm,
> > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > index 28890876bdeb..e5cda5bcbde4 100644
> > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> > > return PLANE_CTL_TILED_X;
> > > case I915_FORMAT_MOD_Y_TILED:
> > > return PLANE_CTL_TILED_Y;
> > > + case I915_FORMAT_MOD_4_TILED:
> > > + return PLANE_CTL_TILED_4;
> > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > return PLANE_CTL_TILED_Y |
> PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> > > @@ -1971,9 +1973,7 @@ static bool
> gen12_plane_format_mod_supported(struct drm_plane *_plane,
> > > case DRM_FORMAT_Y216:
> > > case DRM_FORMAT_XVYU12_16161616:
> > > case DRM_FORMAT_XVYU16161616:
> > > - if (modifier == DRM_FORMAT_MOD_LINEAR ||
> > > - modifier == I915_FORMAT_MOD_X_TILED ||
> > > - modifier == I915_FORMAT_MOD_Y_TILED)
> > > + if (!intel_fb_is_ccs_modifier(modifier))
> > > return true;
> > > fallthrough;
> > > default:
> > > @@ -2299,11 +2299,15 @@ skl_get_initial_plane_config(struct intel_crtc
> *crtc,
> > > else
> > > fb->modifier = I915_FORMAT_MOD_Y_TILED;
> > > break;
> > > - case PLANE_CTL_TILED_YF:
> > > - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > > - else
> > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > > + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
> >
> > To be safe, maybe add a static_assert(PLANE_CTL_TILED_YF ==
> > PLANE_CTL_TILED_4); ?
> >
> > > + if (HAS_4TILE(dev_priv)) {
> > > + fb->modifier = I915_FORMAT_MOD_4_TILED;
> > > + } else {
> > > + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > > + else
> > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > > + }
> > > break;
> > > default:
> > > MISSING_CASE(tiling);
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> > > index 1bfadd9127fc..3d90bd732e91 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,
> > > #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
> > >
> > > #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
> > > +#define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
> > > #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
> > > #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
> > > #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
> > > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> b/drivers/gpu/drm/i915/i915_pci.c
> > > index f01cba4ec283..403d3a581ce7 100644
> > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > @@ -1044,6 +1044,7 @@ static const struct intel_device_info dg2_info = {
> > > DGFX_FEATURES,
> > > .graphics.rel = 55,
> > > .media.rel = 55,
> > > + .has_4tile = 1,
> > > PLATFORM(INTEL_DG2),
> > > .platform_engine_mask =
> > > BIT(RCS0) | BIT(BCS0) |
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> > > index 3450818802c2..22d18a292430 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -7284,6 +7284,7 @@ enum {
> > > #define PLANE_CTL_TILED_X (1 << 10)
> > > #define PLANE_CTL_TILED_Y (4 << 10)
> > > #define PLANE_CTL_TILED_YF (5 << 10)
> > > +#define PLANE_CTL_TILED_4 (5 << 10)
> > > #define PLANE_CTL_ASYNC_FLIP (1 << 9)
> > > #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> > > #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
> > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> > > index 669f0d26c3c3..67177e18704a 100644
> > > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > > @@ -125,6 +125,7 @@ enum intel_ppgtt_type {
> > > func(has_64bit_reloc); \
> > > func(gpu_reset_clobbers_display); \
> > > func(has_reset_engine); \
> > > + func(has_4tile); \
> > > func(has_global_mocs); \
> > > func(has_gt_uc); \
> > > func(has_l3_dpf); \
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> > > index 01fa3fac1b57..167704f0acf0 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -5386,6 +5386,7 @@ skl_compute_wm_params(const struct
> intel_crtc_state *crtc_state,
> > > }
> > >
> > > wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
> > > + modifier == I915_FORMAT_MOD_4_TILED ||
> > > modifier == I915_FORMAT_MOD_Yf_TILED ||
> > > modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > > modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > > diff --git a/include/uapi/drm/drm_fourcc.h
> b/include/uapi/drm/drm_fourcc.h
> > > index 7f652c96845b..41184a94935d 100644
> > > --- a/include/uapi/drm/drm_fourcc.h
> > > +++ b/include/uapi/drm/drm_fourcc.h
> > > @@ -564,6 +564,14 @@ extern "C" {
> > > * pitch is required to be a multiple of 4 tile widths.
> > > */
> > > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> fourcc_mod_code(INTEL, 8)
> > > +/*
> > > + * Intel F-tiling(aka Tile4) layout
> > > + *
> >
> > v4 and v5 attempted to get rid of the F-tile references, but this was
> > left behind.
> >
> > > + * This is a tiled layout using 4Kb tiles in row-major layout.
> > > + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
> > > + * (16 bytes) chunks column-major..
> >
> > I can't picture how tile 4 is organized from this description. Could
> > we update it?
> > Here's a draft I came up with when wondering how I might do this myself:
> >
> > * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
> > * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
> > * only differs from Tile Y at the 256B granularity in between. At this
> > * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
> > * of 64B x 8 rows.
> >
> > -Nanley
> >
> > > + */
> > > +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)
> > >
> > > /*
> > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > > --
> > > 2.24.1.485.gad05a3d8e5
> > >
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
2021-11-23 12:41 ` Chery, Nanley G
@ 2021-11-23 13:36 ` Lisovskiy, Stanislav
2021-11-23 15:06 ` Chery, Nanley G
0 siblings, 1 reply; 28+ messages in thread
From: Lisovskiy, Stanislav @ 2021-11-23 13:36 UTC (permalink / raw)
To: Chery, Nanley G; +Cc: intel-gfx
On Tue, Nov 23, 2021 at 02:41:20PM +0200, Chery, Nanley G wrote:
>
>
> > -----Original Message-----
> > From: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com>
> > Sent: Tuesday, November 23, 2021 3:14 AM
> > To: Nanley Chery <nanleychery@gmail.com>
> > Cc: intel-gfx@lists.freedesktop.org; Chery, Nanley G
> > <nanley.g.chery@intel.com>
> > Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
> >
> > On Mon, Nov 22, 2021 at 05:08:31PM -0500, Nanley Chery wrote:
> > > Hi Stanislav,
> > >
> > > Are there IGT tests for this modifier?
> >
> > Hi Nanley
> >
> > Yes, there should be plenty of those, not sure they
> > are all sent to upstream though.
> > We have a separate team doing this.
> > That modifier should be added to kms_plane_multiple
> > and many others
> >
>
> Okay, I'll be on the lookout for them.
>
> > Stan
> >
>
> Looks like you missed the other review comments I left in my prior email.
Oh, sorry just saw those. I pushed this already, I will check those anyway
and sent additional patch, if needed.
Stan
>
> -Nanley
>
> > >
> > > On Mon, Nov 22, 2021 at 4:14 PM Stanislav Lisovskiy
> > > <stanislav.lisovskiy@intel.com> wrote:
> > > >
> > > > TileF(Tile4 in bspec) format is 4K tile organized into
> > > > 64B subtiles with same basic shape as for legacy TileY
> > > > which will be supported by Display13.
> > > >
> > > > v2: - Fixed wrong case condition(Jani Nikula)
> > > > - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
> > > >
> > > > v3: - s/I915_TILING_F/TILING_4/g
> > > > - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
> > > > - Removed unneeded fencing code
> > > >
> > > > v4: - Rebased, fixed merge conflict with new table-oriented
> > > > format modifier checking(Stan)
> > > > - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
> > > >
> > > > v5: - Still had to remove some Tile F mentionings
> > > > - Moved has_4tile from adlp to DG2(Ramalingam C)
> > > > - Check specifically for DG2, but not the Display13(Imre)
> > > >
> > > > v6: - Moved Tile4 assocating struct for modifier/display to
> > > > the beginning(Imre Deak)
> > > > - Removed unneeded case I915_FORMAT_MOD_4_TILED modifier
> > > > checks(Imre Deak)
> > > > - Fixed I915_FORMAT_MOD_4_TILED to be 9 instead of 12
> > > > (Imre Deak)
> > > >
> > > > v7: - Fixed display_ver to { 13, 13 }(Imre Deak)
> > > > - Removed redundant newline(Imre Deak)
> > > >
> > > > Reviewed-by: Imre Deak <imre.deak@intel.com>
> > > > Cc: Imre Deak <imre.deak@intel.com>
> > > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > > Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_display.c | 1 +
> > > > drivers/gpu/drm/i915/display/intel_fb.c | 9 +++++++++
> > > > drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> > > > .../drm/i915/display/intel_plane_initial.c | 1 +
> > > > .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
> > > > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > > > drivers/gpu/drm/i915/i915_pci.c | 1 +
> > > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > > drivers/gpu/drm/i915/intel_device_info.h | 1 +
> > > > drivers/gpu/drm/i915/intel_pm.c | 1 +
> > > > include/uapi/drm/drm_fourcc.h | 8 ++++++++
> > > > 11 files changed, 37 insertions(+), 8 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index f3c9208a30b1..7429965d3682 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -7766,6 +7766,7 @@ static int intel_atomic_check_async(struct
> > intel_atomic_state *state, struct int
> > > > case I915_FORMAT_MOD_X_TILED:
> > > > case I915_FORMAT_MOD_Y_TILED:
> > > > case I915_FORMAT_MOD_Yf_TILED:
> > > > + case I915_FORMAT_MOD_4_TILED:
> > > > break;
> > > > default:
> > > > drm_dbg_kms(&i915->drm,
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
> > b/drivers/gpu/drm/i915/display/intel_fb.c
> > > > index c4a743d0913f..b7f1ef62072c 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > > > @@ -139,6 +139,9 @@ struct intel_modifier_desc {
> > > >
> > > > static const struct intel_modifier_desc intel_modifiers[] = {
> > > > {
> > > > + .modifier = I915_FORMAT_MOD_4_TILED,
> > > > + .display_ver = { 13, 13 },
> > >
> > > I see that every other modifier has the plane_cap field set. Why is it
> > > okay for it to be zero here?
> > >
> > > > + }, {
> > > > .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> > > > .display_ver = { 12, 13 },
> > > > .plane_caps = INTEL_PLANE_CAP_TILING_Y |
> > INTEL_PLANE_CAP_CCS_MC,
> > > > @@ -544,6 +547,12 @@ intel_tile_width_bytes(const struct
> > drm_framebuffer *fb, int color_plane)
> > > > return 128;
> > > > else
> > > > return 512;
> > > > + case I915_FORMAT_MOD_4_TILED:
> > > > + /*
> > > > + * Each 4K tile consists of 64B(8*8) subtiles, with
> > > > + * same shape as Y Tile(i.e 4*16B OWords)
> > > > + */
> > > > + return 128;
> > > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > > if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> > > > return 128;
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > index d0c34bc3af6c..0ceabe40d8c9 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > @@ -898,6 +898,7 @@ static bool tiling_is_valid(struct drm_i915_private
> > *i915,
> > > > case I915_FORMAT_MOD_Y_TILED:
> > > > case I915_FORMAT_MOD_Yf_TILED:
> > > > return DISPLAY_VER(i915) >= 9;
> > > > + case I915_FORMAT_MOD_4_TILED:
> > >
> > > The tile Y cases above check the display version. Should we do the same here?
> > >
> > > > case I915_FORMAT_MOD_X_TILED:
> > > > return true;
> > > > default:
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > index dcd698a02da2..d80855ee9b96 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
> > > > case DRM_FORMAT_MOD_LINEAR:
> > > > case I915_FORMAT_MOD_X_TILED:
> > > > case I915_FORMAT_MOD_Y_TILED:
> > > > + case I915_FORMAT_MOD_4_TILED:
> > > > break;
> > > > default:
> > > > drm_dbg(&dev_priv->drm,
> > > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > index 28890876bdeb..e5cda5bcbde4 100644
> > > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> > > > return PLANE_CTL_TILED_X;
> > > > case I915_FORMAT_MOD_Y_TILED:
> > > > return PLANE_CTL_TILED_Y;
> > > > + case I915_FORMAT_MOD_4_TILED:
> > > > + return PLANE_CTL_TILED_4;
> > > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > > return PLANE_CTL_TILED_Y |
> > PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> > > > @@ -1971,9 +1973,7 @@ static bool
> > gen12_plane_format_mod_supported(struct drm_plane *_plane,
> > > > case DRM_FORMAT_Y216:
> > > > case DRM_FORMAT_XVYU12_16161616:
> > > > case DRM_FORMAT_XVYU16161616:
> > > > - if (modifier == DRM_FORMAT_MOD_LINEAR ||
> > > > - modifier == I915_FORMAT_MOD_X_TILED ||
> > > > - modifier == I915_FORMAT_MOD_Y_TILED)
> > > > + if (!intel_fb_is_ccs_modifier(modifier))
> > > > return true;
> > > > fallthrough;
> > > > default:
> > > > @@ -2299,11 +2299,15 @@ skl_get_initial_plane_config(struct intel_crtc
> > *crtc,
> > > > else
> > > > fb->modifier = I915_FORMAT_MOD_Y_TILED;
> > > > break;
> > > > - case PLANE_CTL_TILED_YF:
> > > > - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > - else
> > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > > > + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
> > >
> > > To be safe, maybe add a static_assert(PLANE_CTL_TILED_YF ==
> > > PLANE_CTL_TILED_4); ?
> > >
> > > > + if (HAS_4TILE(dev_priv)) {
> > > > + fb->modifier = I915_FORMAT_MOD_4_TILED;
> > > > + } else {
> > > > + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > + else
> > > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > > > + }
> > > > break;
> > > > default:
> > > > MISSING_CASE(tiling);
> > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > > > index 1bfadd9127fc..3d90bd732e91 100644
> > > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > > @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private
> > *i915,
> > > > #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
> > > >
> > > > #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
> > > > +#define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
> > > > #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
> > > > #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
> > > > #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
> > > > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > b/drivers/gpu/drm/i915/i915_pci.c
> > > > index f01cba4ec283..403d3a581ce7 100644
> > > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > > @@ -1044,6 +1044,7 @@ static const struct intel_device_info dg2_info = {
> > > > DGFX_FEATURES,
> > > > .graphics.rel = 55,
> > > > .media.rel = 55,
> > > > + .has_4tile = 1,
> > > > PLATFORM(INTEL_DG2),
> > > > .platform_engine_mask =
> > > > BIT(RCS0) | BIT(BCS0) |
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > > > index 3450818802c2..22d18a292430 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -7284,6 +7284,7 @@ enum {
> > > > #define PLANE_CTL_TILED_X (1 << 10)
> > > > #define PLANE_CTL_TILED_Y (4 << 10)
> > > > #define PLANE_CTL_TILED_YF (5 << 10)
> > > > +#define PLANE_CTL_TILED_4 (5 << 10)
> > > > #define PLANE_CTL_ASYNC_FLIP (1 << 9)
> > > > #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> > > > #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
> > > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> > b/drivers/gpu/drm/i915/intel_device_info.h
> > > > index 669f0d26c3c3..67177e18704a 100644
> > > > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > > > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > > > @@ -125,6 +125,7 @@ enum intel_ppgtt_type {
> > > > func(has_64bit_reloc); \
> > > > func(gpu_reset_clobbers_display); \
> > > > func(has_reset_engine); \
> > > > + func(has_4tile); \
> > > > func(has_global_mocs); \
> > > > func(has_gt_uc); \
> > > > func(has_l3_dpf); \
> > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > > > index 01fa3fac1b57..167704f0acf0 100644
> > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > @@ -5386,6 +5386,7 @@ skl_compute_wm_params(const struct
> > intel_crtc_state *crtc_state,
> > > > }
> > > >
> > > > wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
> > > > + modifier == I915_FORMAT_MOD_4_TILED ||
> > > > modifier == I915_FORMAT_MOD_Yf_TILED ||
> > > > modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > > > modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > diff --git a/include/uapi/drm/drm_fourcc.h
> > b/include/uapi/drm/drm_fourcc.h
> > > > index 7f652c96845b..41184a94935d 100644
> > > > --- a/include/uapi/drm/drm_fourcc.h
> > > > +++ b/include/uapi/drm/drm_fourcc.h
> > > > @@ -564,6 +564,14 @@ extern "C" {
> > > > * pitch is required to be a multiple of 4 tile widths.
> > > > */
> > > > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> > fourcc_mod_code(INTEL, 8)
> > > > +/*
> > > > + * Intel F-tiling(aka Tile4) layout
> > > > + *
> > >
> > > v4 and v5 attempted to get rid of the F-tile references, but this was
> > > left behind.
> > >
> > > > + * This is a tiled layout using 4Kb tiles in row-major layout.
> > > > + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
> > > > + * (16 bytes) chunks column-major..
> > >
> > > I can't picture how tile 4 is organized from this description. Could
> > > we update it?
> > > Here's a draft I came up with when wondering how I might do this myself:
> > >
> > > * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
> > > * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
> > > * only differs from Tile Y at the 256B granularity in between. At this
> > > * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
> > > * of 64B x 8 rows.
> > >
> > > -Nanley
> > >
> > > > + */
> > > > +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)
> > > >
> > > > /*
> > > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > > > --
> > > > 2.24.1.485.gad05a3d8e5
> > > >
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
2021-11-23 13:36 ` Lisovskiy, Stanislav
@ 2021-11-23 15:06 ` Chery, Nanley G
2021-11-23 15:22 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 28+ messages in thread
From: Chery, Nanley G @ 2021-11-23 15:06 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
> -----Original Message-----
> From: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com>
> Sent: Tuesday, November 23, 2021 8:37 AM
> To: Chery, Nanley G <nanley.g.chery@intel.com>
> Cc: Nanley Chery <nanleychery@gmail.com>; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
>
> On Tue, Nov 23, 2021 at 02:41:20PM +0200, Chery, Nanley G wrote:
> >
> >
> > > -----Original Message-----
> > > From: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com>
> > > Sent: Tuesday, November 23, 2021 3:14 AM
> > > To: Nanley Chery <nanleychery@gmail.com>
> > > Cc: intel-gfx@lists.freedesktop.org; Chery, Nanley G
> > > <nanley.g.chery@intel.com>
> > > Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format
> > > support
> > >
> > > On Mon, Nov 22, 2021 at 05:08:31PM -0500, Nanley Chery wrote:
> > > > Hi Stanislav,
> > > >
> > > > Are there IGT tests for this modifier?
> > >
> > > Hi Nanley
> > >
> > > Yes, there should be plenty of those, not sure they are all sent to
> > > upstream though.
> > > We have a separate team doing this.
> > > That modifier should be added to kms_plane_multiple and many others
> > >
> >
> > Okay, I'll be on the lookout for them.
> >
> > > Stan
> > >
> >
> > Looks like you missed the other review comments I left in my prior email.
>
> Oh, sorry just saw those. I pushed this already, I will check those anyway
> and sent additional patch, if needed.
>
Where has this been pushed to? We're still requiring an Ack from userspace/mesa to get new modifiers upstream, right?
-Nanley
> Stan
>
> >
> > -Nanley
> >
> > > >
> > > > On Mon, Nov 22, 2021 at 4:14 PM Stanislav Lisovskiy
> > > > <stanislav.lisovskiy@intel.com> wrote:
> > > > >
> > > > > TileF(Tile4 in bspec) format is 4K tile organized into
> > > > > 64B subtiles with same basic shape as for legacy TileY
> > > > > which will be supported by Display13.
> > > > >
> > > > > v2: - Fixed wrong case condition(Jani Nikula)
> > > > > - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
> > > > >
> > > > > v3: - s/I915_TILING_F/TILING_4/g
> > > > > - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
> > > > > - Removed unneeded fencing code
> > > > >
> > > > > v4: - Rebased, fixed merge conflict with new table-oriented
> > > > > format modifier checking(Stan)
> > > > > - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
> > > > >
> > > > > v5: - Still had to remove some Tile F mentionings
> > > > > - Moved has_4tile from adlp to DG2(Ramalingam C)
> > > > > - Check specifically for DG2, but not the Display13(Imre)
> > > > >
> > > > > v6: - Moved Tile4 assocating struct for modifier/display to
> > > > > the beginning(Imre Deak)
> > > > > - Removed unneeded case I915_FORMAT_MOD_4_TILED modifier
> > > > > checks(Imre Deak)
> > > > > - Fixed I915_FORMAT_MOD_4_TILED to be 9 instead of 12
> > > > > (Imre Deak)
> > > > >
> > > > > v7: - Fixed display_ver to { 13, 13 }(Imre Deak)
> > > > > - Removed redundant newline(Imre Deak)
> > > > >
> > > > > Reviewed-by: Imre Deak <imre.deak@intel.com>
> > > > > Cc: Imre Deak <imre.deak@intel.com>
> > > > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > > > Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/display/intel_display.c | 1 +
> > > > > drivers/gpu/drm/i915/display/intel_fb.c | 9 +++++++++
> > > > > drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> > > > > .../drm/i915/display/intel_plane_initial.c | 1 +
> > > > > .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
> > > > > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > > > > drivers/gpu/drm/i915/i915_pci.c | 1 +
> > > > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > > > drivers/gpu/drm/i915/intel_device_info.h | 1 +
> > > > > drivers/gpu/drm/i915/intel_pm.c | 1 +
> > > > > include/uapi/drm/drm_fourcc.h | 8 ++++++++
> > > > > 11 files changed, 37 insertions(+), 8 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > index f3c9208a30b1..7429965d3682 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > @@ -7766,6 +7766,7 @@ static int intel_atomic_check_async(struct
> > > intel_atomic_state *state, struct int
> > > > > case I915_FORMAT_MOD_X_TILED:
> > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > case I915_FORMAT_MOD_Yf_TILED:
> > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > break;
> > > > > default:
> > > > > drm_dbg_kms(&i915->drm,
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
> > > b/drivers/gpu/drm/i915/display/intel_fb.c
> > > > > index c4a743d0913f..b7f1ef62072c 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > > > > @@ -139,6 +139,9 @@ struct intel_modifier_desc {
> > > > >
> > > > > static const struct intel_modifier_desc intel_modifiers[] = {
> > > > > {
> > > > > + .modifier = I915_FORMAT_MOD_4_TILED,
> > > > > + .display_ver = { 13, 13 },
> > > >
> > > > I see that every other modifier has the plane_cap field set. Why is it
> > > > okay for it to be zero here?
> > > >
> > > > > + }, {
> > > > > .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> > > > > .display_ver = { 12, 13 },
> > > > > .plane_caps = INTEL_PLANE_CAP_TILING_Y |
> > > INTEL_PLANE_CAP_CCS_MC,
> > > > > @@ -544,6 +547,12 @@ intel_tile_width_bytes(const struct
> > > drm_framebuffer *fb, int color_plane)
> > > > > return 128;
> > > > > else
> > > > > return 512;
> > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > + /*
> > > > > + * Each 4K tile consists of 64B(8*8) subtiles, with
> > > > > + * same shape as Y Tile(i.e 4*16B OWords)
> > > > > + */
> > > > > + return 128;
> > > > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > > > if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> > > > > return 128;
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > index d0c34bc3af6c..0ceabe40d8c9 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > @@ -898,6 +898,7 @@ static bool tiling_is_valid(struct
> drm_i915_private
> > > *i915,
> > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > case I915_FORMAT_MOD_Yf_TILED:
> > > > > return DISPLAY_VER(i915) >= 9;
> > > > > + case I915_FORMAT_MOD_4_TILED:
> > > >
> > > > The tile Y cases above check the display version. Should we do the same
> here?
> > > >
> > > > > case I915_FORMAT_MOD_X_TILED:
> > > > > return true;
> > > > > default:
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > > index dcd698a02da2..d80855ee9b96 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > > @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc
> *crtc,
> > > > > case DRM_FORMAT_MOD_LINEAR:
> > > > > case I915_FORMAT_MOD_X_TILED:
> > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > break;
> > > > > default:
> > > > > drm_dbg(&dev_priv->drm,
> > > > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > index 28890876bdeb..e5cda5bcbde4 100644
> > > > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> > > > > return PLANE_CTL_TILED_X;
> > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > return PLANE_CTL_TILED_Y;
> > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > + return PLANE_CTL_TILED_4;
> > > > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > > > return PLANE_CTL_TILED_Y |
> > > PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> > > > > @@ -1971,9 +1973,7 @@ static bool
> > > gen12_plane_format_mod_supported(struct drm_plane *_plane,
> > > > > case DRM_FORMAT_Y216:
> > > > > case DRM_FORMAT_XVYU12_16161616:
> > > > > case DRM_FORMAT_XVYU16161616:
> > > > > - if (modifier == DRM_FORMAT_MOD_LINEAR ||
> > > > > - modifier == I915_FORMAT_MOD_X_TILED ||
> > > > > - modifier == I915_FORMAT_MOD_Y_TILED)
> > > > > + if (!intel_fb_is_ccs_modifier(modifier))
> > > > > return true;
> > > > > fallthrough;
> > > > > default:
> > > > > @@ -2299,11 +2299,15 @@ skl_get_initial_plane_config(struct
> intel_crtc
> > > *crtc,
> > > > > else
> > > > > fb->modifier = I915_FORMAT_MOD_Y_TILED;
> > > > > break;
> > > > > - case PLANE_CTL_TILED_YF:
> > > > > - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > > - else
> > > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > > > > + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on
> XE_LPD+ */
> > > >
> > > > To be safe, maybe add a static_assert(PLANE_CTL_TILED_YF ==
> > > > PLANE_CTL_TILED_4); ?
> > > >
> > > > > + if (HAS_4TILE(dev_priv)) {
> > > > > + fb->modifier = I915_FORMAT_MOD_4_TILED;
> > > > > + } else {
> > > > > + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > > + else
> > > > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > > > > + }
> > > > > break;
> > > > > default:
> > > > > MISSING_CASE(tiling);
> > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > b/drivers/gpu/drm/i915/i915_drv.h
> > > > > index 1bfadd9127fc..3d90bd732e91 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > > > @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct
> drm_i915_private
> > > *i915,
> > > > > #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv)
> == 7)
> > > > >
> > > > > #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
> > > > > +#define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
> > > > > #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
> > > > > #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
> > > > > #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
> > > > > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > > b/drivers/gpu/drm/i915/i915_pci.c
> > > > > index f01cba4ec283..403d3a581ce7 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > > > @@ -1044,6 +1044,7 @@ static const struct intel_device_info dg2_info
> = {
> > > > > DGFX_FEATURES,
> > > > > .graphics.rel = 55,
> > > > > .media.rel = 55,
> > > > > + .has_4tile = 1,
> > > > > PLATFORM(INTEL_DG2),
> > > > > .platform_engine_mask =
> > > > > BIT(RCS0) | BIT(BCS0) |
> > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > > > index 3450818802c2..22d18a292430 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > > @@ -7284,6 +7284,7 @@ enum {
> > > > > #define PLANE_CTL_TILED_X (1 << 10)
> > > > > #define PLANE_CTL_TILED_Y (4 << 10)
> > > > > #define PLANE_CTL_TILED_YF (5 << 10)
> > > > > +#define PLANE_CTL_TILED_4 (5 << 10)
> > > > > #define PLANE_CTL_ASYNC_FLIP (1 << 9)
> > > > > #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> > > > > #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /*
> TGL+ */
> > > > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> > > b/drivers/gpu/drm/i915/intel_device_info.h
> > > > > index 669f0d26c3c3..67177e18704a 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > > > > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > > > > @@ -125,6 +125,7 @@ enum intel_ppgtt_type {
> > > > > func(has_64bit_reloc); \
> > > > > func(gpu_reset_clobbers_display); \
> > > > > func(has_reset_engine); \
> > > > > + func(has_4tile); \
> > > > > func(has_global_mocs); \
> > > > > func(has_gt_uc); \
> > > > > func(has_l3_dpf); \
> > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > b/drivers/gpu/drm/i915/intel_pm.c
> > > > > index 01fa3fac1b57..167704f0acf0 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > @@ -5386,6 +5386,7 @@ skl_compute_wm_params(const struct
> > > intel_crtc_state *crtc_state,
> > > > > }
> > > > >
> > > > > wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
> > > > > + modifier == I915_FORMAT_MOD_4_TILED ||
> > > > > modifier == I915_FORMAT_MOD_Yf_TILED ||
> > > > > modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > > > > modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > > diff --git a/include/uapi/drm/drm_fourcc.h
> > > b/include/uapi/drm/drm_fourcc.h
> > > > > index 7f652c96845b..41184a94935d 100644
> > > > > --- a/include/uapi/drm/drm_fourcc.h
> > > > > +++ b/include/uapi/drm/drm_fourcc.h
> > > > > @@ -564,6 +564,14 @@ extern "C" {
> > > > > * pitch is required to be a multiple of 4 tile widths.
> > > > > */
> > > > > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> > > fourcc_mod_code(INTEL, 8)
> > > > > +/*
> > > > > + * Intel F-tiling(aka Tile4) layout
> > > > > + *
> > > >
> > > > v4 and v5 attempted to get rid of the F-tile references, but this was
> > > > left behind.
> > > >
> > > > > + * This is a tiled layout using 4Kb tiles in row-major layout.
> > > > > + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
> > > > > + * (16 bytes) chunks column-major..
> > > >
> > > > I can't picture how tile 4 is organized from this description. Could
> > > > we update it?
> > > > Here's a draft I came up with when wondering how I might do this myself:
> > > >
> > > > * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
> > > > * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
> > > > * only differs from Tile Y at the 256B granularity in between. At this
> > > > * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
> > > > * of 64B x 8 rows.
> > > >
> > > > -Nanley
> > > >
> > > > > + */
> > > > > +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)
> > > > >
> > > > > /*
> > > > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > > > > --
> > > > > 2.24.1.485.gad05a3d8e5
> > > > >
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
2021-11-23 15:06 ` Chery, Nanley G
@ 2021-11-23 15:22 ` Lisovskiy, Stanislav
2021-11-23 15:59 ` Chery, Nanley G
0 siblings, 1 reply; 28+ messages in thread
From: Lisovskiy, Stanislav @ 2021-11-23 15:22 UTC (permalink / raw)
To: Chery, Nanley G; +Cc: intel-gfx
On Tue, Nov 23, 2021 at 05:06:22PM +0200, Chery, Nanley G wrote:
>
>
> > -----Original Message-----
> > From: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com>
> > Sent: Tuesday, November 23, 2021 8:37 AM
> > To: Chery, Nanley G <nanley.g.chery@intel.com>
> > Cc: Nanley Chery <nanleychery@gmail.com>; intel-gfx@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
> >
> > On Tue, Nov 23, 2021 at 02:41:20PM +0200, Chery, Nanley G wrote:
> > >
> > >
> > > > -----Original Message-----
> > > > From: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com>
> > > > Sent: Tuesday, November 23, 2021 3:14 AM
> > > > To: Nanley Chery <nanleychery@gmail.com>
> > > > Cc: intel-gfx@lists.freedesktop.org; Chery, Nanley G
> > > > <nanley.g.chery@intel.com>
> > > > Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format
> > > > support
> > > >
> > > > On Mon, Nov 22, 2021 at 05:08:31PM -0500, Nanley Chery wrote:
> > > > > Hi Stanislav,
> > > > >
> > > > > Are there IGT tests for this modifier?
> > > >
> > > > Hi Nanley
> > > >
> > > > Yes, there should be plenty of those, not sure they are all sent to
> > > > upstream though.
> > > > We have a separate team doing this.
> > > > That modifier should be added to kms_plane_multiple and many others
> > > >
> > >
> > > Okay, I'll be on the lookout for them.
> > >
> > > > Stan
> > > >
> > >
> > > Looks like you missed the other review comments I left in my prior email.
> >
> > Oh, sorry just saw those. I pushed this already, I will check those anyway
> > and sent additional patch, if needed.
> >
>
> Where has this been pushed to? We're still requiring an Ack from userspace/mesa to get new modifiers upstream, right?
It was pushed to drm-intel-next. To be honest, I was not aware that this requires userspace/mesa ack.
How do we proceed then? Should I revert and push the fixed version or do we wait until IGT
part gets merged?
Stan
>
> -Nanley
>
> > Stan
> >
> > >
> > > -Nanley
> > >
> > > > >
> > > > > On Mon, Nov 22, 2021 at 4:14 PM Stanislav Lisovskiy
> > > > > <stanislav.lisovskiy@intel.com> wrote:
> > > > > >
> > > > > > TileF(Tile4 in bspec) format is 4K tile organized into
> > > > > > 64B subtiles with same basic shape as for legacy TileY
> > > > > > which will be supported by Display13.
> > > > > >
> > > > > > v2: - Fixed wrong case condition(Jani Nikula)
> > > > > > - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
> > > > > >
> > > > > > v3: - s/I915_TILING_F/TILING_4/g
> > > > > > - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
> > > > > > - Removed unneeded fencing code
> > > > > >
> > > > > > v4: - Rebased, fixed merge conflict with new table-oriented
> > > > > > format modifier checking(Stan)
> > > > > > - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
> > > > > >
> > > > > > v5: - Still had to remove some Tile F mentionings
> > > > > > - Moved has_4tile from adlp to DG2(Ramalingam C)
> > > > > > - Check specifically for DG2, but not the Display13(Imre)
> > > > > >
> > > > > > v6: - Moved Tile4 assocating struct for modifier/display to
> > > > > > the beginning(Imre Deak)
> > > > > > - Removed unneeded case I915_FORMAT_MOD_4_TILED modifier
> > > > > > checks(Imre Deak)
> > > > > > - Fixed I915_FORMAT_MOD_4_TILED to be 9 instead of 12
> > > > > > (Imre Deak)
> > > > > >
> > > > > > v7: - Fixed display_ver to { 13, 13 }(Imre Deak)
> > > > > > - Removed redundant newline(Imre Deak)
> > > > > >
> > > > > > Reviewed-by: Imre Deak <imre.deak@intel.com>
> > > > > > Cc: Imre Deak <imre.deak@intel.com>
> > > > > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > > > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > > > > Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/display/intel_display.c | 1 +
> > > > > > drivers/gpu/drm/i915/display/intel_fb.c | 9 +++++++++
> > > > > > drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> > > > > > .../drm/i915/display/intel_plane_initial.c | 1 +
> > > > > > .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
> > > > > > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > > > > > drivers/gpu/drm/i915/i915_pci.c | 1 +
> > > > > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > > > > drivers/gpu/drm/i915/intel_device_info.h | 1 +
> > > > > > drivers/gpu/drm/i915/intel_pm.c | 1 +
> > > > > > include/uapi/drm/drm_fourcc.h | 8 ++++++++
> > > > > > 11 files changed, 37 insertions(+), 8 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > index f3c9208a30b1..7429965d3682 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > @@ -7766,6 +7766,7 @@ static int intel_atomic_check_async(struct
> > > > intel_atomic_state *state, struct int
> > > > > > case I915_FORMAT_MOD_X_TILED:
> > > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > > case I915_FORMAT_MOD_Yf_TILED:
> > > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > > break;
> > > > > > default:
> > > > > > drm_dbg_kms(&i915->drm,
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
> > > > b/drivers/gpu/drm/i915/display/intel_fb.c
> > > > > > index c4a743d0913f..b7f1ef62072c 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > > > > > @@ -139,6 +139,9 @@ struct intel_modifier_desc {
> > > > > >
> > > > > > static const struct intel_modifier_desc intel_modifiers[] = {
> > > > > > {
> > > > > > + .modifier = I915_FORMAT_MOD_4_TILED,
> > > > > > + .display_ver = { 13, 13 },
> > > > >
> > > > > I see that every other modifier has the plane_cap field set. Why is it
> > > > > okay for it to be zero here?
> > > > >
> > > > > > + }, {
> > > > > > .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> > > > > > .display_ver = { 12, 13 },
> > > > > > .plane_caps = INTEL_PLANE_CAP_TILING_Y |
> > > > INTEL_PLANE_CAP_CCS_MC,
> > > > > > @@ -544,6 +547,12 @@ intel_tile_width_bytes(const struct
> > > > drm_framebuffer *fb, int color_plane)
> > > > > > return 128;
> > > > > > else
> > > > > > return 512;
> > > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > > + /*
> > > > > > + * Each 4K tile consists of 64B(8*8) subtiles, with
> > > > > > + * same shape as Y Tile(i.e 4*16B OWords)
> > > > > > + */
> > > > > > + return 128;
> > > > > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > > > > if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> > > > > > return 128;
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > > index d0c34bc3af6c..0ceabe40d8c9 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > > @@ -898,6 +898,7 @@ static bool tiling_is_valid(struct
> > drm_i915_private
> > > > *i915,
> > > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > > case I915_FORMAT_MOD_Yf_TILED:
> > > > > > return DISPLAY_VER(i915) >= 9;
> > > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > >
> > > > > The tile Y cases above check the display version. Should we do the same
> > here?
> > > > >
> > > > > > case I915_FORMAT_MOD_X_TILED:
> > > > > > return true;
> > > > > > default:
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > > > index dcd698a02da2..d80855ee9b96 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > > > @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc
> > *crtc,
> > > > > > case DRM_FORMAT_MOD_LINEAR:
> > > > > > case I915_FORMAT_MOD_X_TILED:
> > > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > > break;
> > > > > > default:
> > > > > > drm_dbg(&dev_priv->drm,
> > > > > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > > index 28890876bdeb..e5cda5bcbde4 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > > @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> > > > > > return PLANE_CTL_TILED_X;
> > > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > > return PLANE_CTL_TILED_Y;
> > > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > > + return PLANE_CTL_TILED_4;
> > > > > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > > > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > > > > return PLANE_CTL_TILED_Y |
> > > > PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> > > > > > @@ -1971,9 +1973,7 @@ static bool
> > > > gen12_plane_format_mod_supported(struct drm_plane *_plane,
> > > > > > case DRM_FORMAT_Y216:
> > > > > > case DRM_FORMAT_XVYU12_16161616:
> > > > > > case DRM_FORMAT_XVYU16161616:
> > > > > > - if (modifier == DRM_FORMAT_MOD_LINEAR ||
> > > > > > - modifier == I915_FORMAT_MOD_X_TILED ||
> > > > > > - modifier == I915_FORMAT_MOD_Y_TILED)
> > > > > > + if (!intel_fb_is_ccs_modifier(modifier))
> > > > > > return true;
> > > > > > fallthrough;
> > > > > > default:
> > > > > > @@ -2299,11 +2299,15 @@ skl_get_initial_plane_config(struct
> > intel_crtc
> > > > *crtc,
> > > > > > else
> > > > > > fb->modifier = I915_FORMAT_MOD_Y_TILED;
> > > > > > break;
> > > > > > - case PLANE_CTL_TILED_YF:
> > > > > > - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > > > - else
> > > > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > > > > > + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on
> > XE_LPD+ */
> > > > >
> > > > > To be safe, maybe add a static_assert(PLANE_CTL_TILED_YF ==
> > > > > PLANE_CTL_TILED_4); ?
> > > > >
> > > > > > + if (HAS_4TILE(dev_priv)) {
> > > > > > + fb->modifier = I915_FORMAT_MOD_4_TILED;
> > > > > > + } else {
> > > > > > + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > > > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > > > + else
> > > > > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > > > > > + }
> > > > > > break;
> > > > > > default:
> > > > > > MISSING_CASE(tiling);
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > > b/drivers/gpu/drm/i915/i915_drv.h
> > > > > > index 1bfadd9127fc..3d90bd732e91 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > > > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > > > > @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct
> > drm_i915_private
> > > > *i915,
> > > > > > #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv)
> > == 7)
> > > > > >
> > > > > > #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
> > > > > > +#define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
> > > > > > #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
> > > > > > #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
> > > > > > #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > > > b/drivers/gpu/drm/i915/i915_pci.c
> > > > > > index f01cba4ec283..403d3a581ce7 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > > > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > > > > @@ -1044,6 +1044,7 @@ static const struct intel_device_info dg2_info
> > = {
> > > > > > DGFX_FEATURES,
> > > > > > .graphics.rel = 55,
> > > > > > .media.rel = 55,
> > > > > > + .has_4tile = 1,
> > > > > > PLATFORM(INTEL_DG2),
> > > > > > .platform_engine_mask =
> > > > > > BIT(RCS0) | BIT(BCS0) |
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > > b/drivers/gpu/drm/i915/i915_reg.h
> > > > > > index 3450818802c2..22d18a292430 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > > > @@ -7284,6 +7284,7 @@ enum {
> > > > > > #define PLANE_CTL_TILED_X (1 << 10)
> > > > > > #define PLANE_CTL_TILED_Y (4 << 10)
> > > > > > #define PLANE_CTL_TILED_YF (5 << 10)
> > > > > > +#define PLANE_CTL_TILED_4 (5 << 10)
> > > > > > #define PLANE_CTL_ASYNC_FLIP (1 << 9)
> > > > > > #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> > > > > > #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /*
> > TGL+ */
> > > > > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> > > > b/drivers/gpu/drm/i915/intel_device_info.h
> > > > > > index 669f0d26c3c3..67177e18704a 100644
> > > > > > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > > > > > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > > > > > @@ -125,6 +125,7 @@ enum intel_ppgtt_type {
> > > > > > func(has_64bit_reloc); \
> > > > > > func(gpu_reset_clobbers_display); \
> > > > > > func(has_reset_engine); \
> > > > > > + func(has_4tile); \
> > > > > > func(has_global_mocs); \
> > > > > > func(has_gt_uc); \
> > > > > > func(has_l3_dpf); \
> > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > > b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > index 01fa3fac1b57..167704f0acf0 100644
> > > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > @@ -5386,6 +5386,7 @@ skl_compute_wm_params(const struct
> > > > intel_crtc_state *crtc_state,
> > > > > > }
> > > > > >
> > > > > > wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
> > > > > > + modifier == I915_FORMAT_MOD_4_TILED ||
> > > > > > modifier == I915_FORMAT_MOD_Yf_TILED ||
> > > > > > modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > > > > > modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > > > diff --git a/include/uapi/drm/drm_fourcc.h
> > > > b/include/uapi/drm/drm_fourcc.h
> > > > > > index 7f652c96845b..41184a94935d 100644
> > > > > > --- a/include/uapi/drm/drm_fourcc.h
> > > > > > +++ b/include/uapi/drm/drm_fourcc.h
> > > > > > @@ -564,6 +564,14 @@ extern "C" {
> > > > > > * pitch is required to be a multiple of 4 tile widths.
> > > > > > */
> > > > > > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> > > > fourcc_mod_code(INTEL, 8)
> > > > > > +/*
> > > > > > + * Intel F-tiling(aka Tile4) layout
> > > > > > + *
> > > > >
> > > > > v4 and v5 attempted to get rid of the F-tile references, but this was
> > > > > left behind.
> > > > >
> > > > > > + * This is a tiled layout using 4Kb tiles in row-major layout.
> > > > > > + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
> > > > > > + * (16 bytes) chunks column-major..
> > > > >
> > > > > I can't picture how tile 4 is organized from this description. Could
> > > > > we update it?
> > > > > Here's a draft I came up with when wondering how I might do this myself:
> > > > >
> > > > > * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
> > > > > * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
> > > > > * only differs from Tile Y at the 256B granularity in between. At this
> > > > > * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
> > > > > * of 64B x 8 rows.
> > > > >
> > > > > -Nanley
> > > > >
> > > > > > + */
> > > > > > +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)
> > > > > >
> > > > > > /*
> > > > > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > > > > > --
> > > > > > 2.24.1.485.gad05a3d8e5
> > > > > >
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
2021-11-23 15:22 ` Lisovskiy, Stanislav
@ 2021-11-23 15:59 ` Chery, Nanley G
0 siblings, 0 replies; 28+ messages in thread
From: Chery, Nanley G @ 2021-11-23 15:59 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
> -----Original Message-----
> From: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com>
> Sent: Tuesday, November 23, 2021 10:23 AM
> To: Chery, Nanley G <nanley.g.chery@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Deak, Imre <imre.deak@intel.com>
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
>
> On Tue, Nov 23, 2021 at 05:06:22PM +0200, Chery, Nanley G wrote:
> >
> >
> > > -----Original Message-----
> > > From: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com>
> > > Sent: Tuesday, November 23, 2021 8:37 AM
> > > To: Chery, Nanley G <nanley.g.chery@intel.com>
> > > Cc: Nanley Chery <nanleychery@gmail.com>;
> > > intel-gfx@lists.freedesktop.org
> > > Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format
> > > support
> > >
> > > On Tue, Nov 23, 2021 at 02:41:20PM +0200, Chery, Nanley G wrote:
> > > >
> > > >
> > > > > -----Original Message-----
> > > > > From: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com>
> > > > > Sent: Tuesday, November 23, 2021 3:14 AM
> > > > > To: Nanley Chery <nanleychery@gmail.com>
> > > > > Cc: intel-gfx@lists.freedesktop.org; Chery, Nanley G
> > > > > <nanley.g.chery@intel.com>
> > > > > Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane
> > > > > format support
> > > > >
> > > > > On Mon, Nov 22, 2021 at 05:08:31PM -0500, Nanley Chery wrote:
> > > > > > Hi Stanislav,
> > > > > >
> > > > > > Are there IGT tests for this modifier?
> > > > >
> > > > > Hi Nanley
> > > > >
> > > > > Yes, there should be plenty of those, not sure they are all sent
> > > > > to upstream though.
> > > > > We have a separate team doing this.
> > > > > That modifier should be added to kms_plane_multiple and many
> > > > > others
> > > > >
> > > >
> > > > Okay, I'll be on the lookout for them.
> > > >
> > > > > Stan
> > > > >
> > > >
> > > > Looks like you missed the other review comments I left in my prior email.
> > >
> > > Oh, sorry just saw those. I pushed this already, I will check those
> > > anyway and sent additional patch, if needed.
> > >
> >
> > Where has this been pushed to? We're still requiring an Ack from
> userspace/mesa to get new modifiers upstream, right?
>
> It was pushed to drm-intel-next. To be honest, I was not aware that this requires
> userspace/mesa ack.
>
Yeah, I don't think much of the process has been documented. Might be good for us
to discuss and/or put something together. The ack was something we did in the last
cycle and it seemed like something we were going to do for this one as well.
> How do we proceed then? Should I revert and push the fixed version or do we
> wait until IGT part gets merged?
>
Reverting and waiting for IGT tests to at least be on the list seems like a reasonable
plan to me. I also think it's a good idea to continue waiting on an ack from mesa as
well. I'll be OOO this week for holidays, but I'm happy to discuss the latter bit when
I get back.
-Nanley
> Stan
>
> >
> > -Nanley
> >
> > > Stan
> > >
> > > >
> > > > -Nanley
> > > >
> > > > > >
> > > > > > On Mon, Nov 22, 2021 at 4:14 PM Stanislav Lisovskiy
> > > > > > <stanislav.lisovskiy@intel.com> wrote:
> > > > > > >
> > > > > > > TileF(Tile4 in bspec) format is 4K tile organized into 64B
> > > > > > > subtiles with same basic shape as for legacy TileY which
> > > > > > > will be supported by Display13.
> > > > > > >
> > > > > > > v2: - Fixed wrong case condition(Jani Nikula)
> > > > > > > - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
> > > > > > >
> > > > > > > v3: - s/I915_TILING_F/TILING_4/g
> > > > > > > - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
> > > > > > > - Removed unneeded fencing code
> > > > > > >
> > > > > > > v4: - Rebased, fixed merge conflict with new table-oriented
> > > > > > > format modifier checking(Stan)
> > > > > > > - Replaced the rest of "Tile F" mentions to "Tile
> > > > > > > 4"(Stan)
> > > > > > >
> > > > > > > v5: - Still had to remove some Tile F mentionings
> > > > > > > - Moved has_4tile from adlp to DG2(Ramalingam C)
> > > > > > > - Check specifically for DG2, but not the
> > > > > > > Display13(Imre)
> > > > > > >
> > > > > > > v6: - Moved Tile4 assocating struct for modifier/display to
> > > > > > > the beginning(Imre Deak)
> > > > > > > - Removed unneeded case I915_FORMAT_MOD_4_TILED modifier
> > > > > > > checks(Imre Deak)
> > > > > > > - Fixed I915_FORMAT_MOD_4_TILED to be 9 instead of 12
> > > > > > > (Imre Deak)
> > > > > > >
> > > > > > > v7: - Fixed display_ver to { 13, 13 }(Imre Deak)
> > > > > > > - Removed redundant newline(Imre Deak)
> > > > > > >
> > > > > > > Reviewed-by: Imre Deak <imre.deak@intel.com>
> > > > > > > Cc: Imre Deak <imre.deak@intel.com>
> > > > > > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > > > > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > > > > > Signed-off-by: Stanislav Lisovskiy
> > > > > > > <stanislav.lisovskiy@intel.com>
> > > > > > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > > > > > Signed-off-by: Juha-Pekka Heikkilä
> > > > > > > <juha-pekka.heikkila@intel.com>
> > > > > > > ---
> > > > > > > drivers/gpu/drm/i915/display/intel_display.c | 1 +
> > > > > > > drivers/gpu/drm/i915/display/intel_fb.c | 9 +++++++++
> > > > > > > drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> > > > > > > .../drm/i915/display/intel_plane_initial.c | 1 +
> > > > > > > .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
> > > > > > > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > > > > > > drivers/gpu/drm/i915/i915_pci.c | 1 +
> > > > > > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > > > > > drivers/gpu/drm/i915/intel_device_info.h | 1 +
> > > > > > > drivers/gpu/drm/i915/intel_pm.c | 1 +
> > > > > > > include/uapi/drm/drm_fourcc.h | 8 ++++++++
> > > > > > > 11 files changed, 37 insertions(+), 8 deletions(-)
> > > > > > >
> > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > > index f3c9208a30b1..7429965d3682 100644
> > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > > @@ -7766,6 +7766,7 @@ static int
> > > > > > > intel_atomic_check_async(struct
> > > > > intel_atomic_state *state, struct int
> > > > > > > case I915_FORMAT_MOD_X_TILED:
> > > > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > > > case I915_FORMAT_MOD_Yf_TILED:
> > > > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > > > break;
> > > > > > > default:
> > > > > > > drm_dbg_kms(&i915->drm, diff --git
> > > > > > > a/drivers/gpu/drm/i915/display/intel_fb.c
> > > > > b/drivers/gpu/drm/i915/display/intel_fb.c
> > > > > > > index c4a743d0913f..b7f1ef62072c 100644
> > > > > > > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > > > > > > @@ -139,6 +139,9 @@ struct intel_modifier_desc {
> > > > > > >
> > > > > > > static const struct intel_modifier_desc intel_modifiers[] = {
> > > > > > > {
> > > > > > > + .modifier = I915_FORMAT_MOD_4_TILED,
> > > > > > > + .display_ver = { 13, 13 },
> > > > > >
> > > > > > I see that every other modifier has the plane_cap field set.
> > > > > > Why is it okay for it to be zero here?
> > > > > >
> > > > > > > + }, {
> > > > > > > .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> > > > > > > .display_ver = { 12, 13 },
> > > > > > > .plane_caps = INTEL_PLANE_CAP_TILING_Y |
> > > > > INTEL_PLANE_CAP_CCS_MC,
> > > > > > > @@ -544,6 +547,12 @@ intel_tile_width_bytes(const struct
> > > > > drm_framebuffer *fb, int color_plane)
> > > > > > > return 128;
> > > > > > > else
> > > > > > > return 512;
> > > > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > > > + /*
> > > > > > > + * Each 4K tile consists of 64B(8*8) subtiles, with
> > > > > > > + * same shape as Y Tile(i.e 4*16B OWords)
> > > > > > > + */
> > > > > > > + return 128;
> > > > > > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > > > > > if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> > > > > > > return 128; diff --git
> > > > > > > a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > > > index d0c34bc3af6c..0ceabe40d8c9 100644
> > > > > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > > > @@ -898,6 +898,7 @@ static bool tiling_is_valid(struct
> > > drm_i915_private
> > > > > *i915,
> > > > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > > > case I915_FORMAT_MOD_Yf_TILED:
> > > > > > > return DISPLAY_VER(i915) >= 9;
> > > > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > >
> > > > > > The tile Y cases above check the display version. Should we do
> > > > > > the same
> > > here?
> > > > > >
> > > > > > > case I915_FORMAT_MOD_X_TILED:
> > > > > > > return true;
> > > > > > > default:
> > > > > > > diff --git
> > > > > > > a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > > b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > > > > index dcd698a02da2..d80855ee9b96 100644
> > > > > > > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > > > > @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct
> > > > > > > intel_crtc
> > > *crtc,
> > > > > > > case DRM_FORMAT_MOD_LINEAR:
> > > > > > > case I915_FORMAT_MOD_X_TILED:
> > > > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > > > break;
> > > > > > > default:
> > > > > > > drm_dbg(&dev_priv->drm, diff --git
> > > > > > > a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > > > index 28890876bdeb..e5cda5bcbde4 100644
> > > > > > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > > > @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64
> fb_modifier)
> > > > > > > return PLANE_CTL_TILED_X;
> > > > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > > > return PLANE_CTL_TILED_Y;
> > > > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > > > + return PLANE_CTL_TILED_4;
> > > > > > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > > > > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > > > > > return PLANE_CTL_TILED_Y |
> > > > > PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> > > > > > > @@ -1971,9 +1973,7 @@ static bool
> > > > > gen12_plane_format_mod_supported(struct drm_plane *_plane,
> > > > > > > case DRM_FORMAT_Y216:
> > > > > > > case DRM_FORMAT_XVYU12_16161616:
> > > > > > > case DRM_FORMAT_XVYU16161616:
> > > > > > > - if (modifier == DRM_FORMAT_MOD_LINEAR ||
> > > > > > > - modifier == I915_FORMAT_MOD_X_TILED ||
> > > > > > > - modifier == I915_FORMAT_MOD_Y_TILED)
> > > > > > > + if (!intel_fb_is_ccs_modifier(modifier))
> > > > > > > return true;
> > > > > > > fallthrough;
> > > > > > > default:
> > > > > > > @@ -2299,11 +2299,15 @@ skl_get_initial_plane_config(struct
> > > intel_crtc
> > > > > *crtc,
> > > > > > > else
> > > > > > > fb->modifier = I915_FORMAT_MOD_Y_TILED;
> > > > > > > break;
> > > > > > > - case PLANE_CTL_TILED_YF:
> > > > > > > - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > > > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > > > > - else
> > > > > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > > > > > > + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on
> > > XE_LPD+ */
> > > > > >
> > > > > > To be safe, maybe add a static_assert(PLANE_CTL_TILED_YF ==
> > > > > > PLANE_CTL_TILED_4); ?
> > > > > >
> > > > > > > + if (HAS_4TILE(dev_priv)) {
> > > > > > > + fb->modifier = I915_FORMAT_MOD_4_TILED;
> > > > > > > + } else {
> > > > > > > + if (val &
> PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > > > > > + fb->modifier =
> I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > > > > + else
> > > > > > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > > > > > > + }
> > > > > > > break;
> > > > > > > default:
> > > > > > > MISSING_CASE(tiling); diff --git
> > > > > > > a/drivers/gpu/drm/i915/i915_drv.h
> > > > > b/drivers/gpu/drm/i915/i915_drv.h
> > > > > > > index 1bfadd9127fc..3d90bd732e91 100644
> > > > > > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > > > > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > > > > > @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct
> > > drm_i915_private
> > > > > *i915,
> > > > > > > #define CMDPARSER_USES_GGTT(dev_priv)
> > > > > > > (GRAPHICS_VER(dev_priv)
> > > == 7)
> > > > > > >
> > > > > > > #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
> > > > > > > +#define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
> > > > > > > #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
> > > > > > > #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
> > > > > > > #define HAS_SECURE_BATCHES(dev_priv)
> > > > > > > (GRAPHICS_VER(dev_priv) < 6) diff --git
> > > > > > > a/drivers/gpu/drm/i915/i915_pci.c
> > > > > b/drivers/gpu/drm/i915/i915_pci.c
> > > > > > > index f01cba4ec283..403d3a581ce7 100644
> > > > > > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > > > > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > > > > > @@ -1044,6 +1044,7 @@ static const struct intel_device_info
> > > > > > > dg2_info
> > > = {
> > > > > > > DGFX_FEATURES,
> > > > > > > .graphics.rel = 55,
> > > > > > > .media.rel = 55,
> > > > > > > + .has_4tile = 1,
> > > > > > > PLATFORM(INTEL_DG2),
> > > > > > > .platform_engine_mask =
> > > > > > > BIT(RCS0) | BIT(BCS0) | diff --git
> > > > > > > a/drivers/gpu/drm/i915/i915_reg.h
> > > > > b/drivers/gpu/drm/i915/i915_reg.h
> > > > > > > index 3450818802c2..22d18a292430 100644
> > > > > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > > > > @@ -7284,6 +7284,7 @@ enum {
> > > > > > > #define PLANE_CTL_TILED_X (1 << 10)
> > > > > > > #define PLANE_CTL_TILED_Y (4 << 10)
> > > > > > > #define PLANE_CTL_TILED_YF (5 << 10)
> > > > > > > +#define PLANE_CTL_TILED_4 (5 << 10)
> > > > > > > #define PLANE_CTL_ASYNC_FLIP (1 << 9)
> > > > > > > #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> > > > > > > #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /*
> > > TGL+ */
> > > > > > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> > > > > b/drivers/gpu/drm/i915/intel_device_info.h
> > > > > > > index 669f0d26c3c3..67177e18704a 100644
> > > > > > > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > > > > > > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > > > > > > @@ -125,6 +125,7 @@ enum intel_ppgtt_type {
> > > > > > > func(has_64bit_reloc); \
> > > > > > > func(gpu_reset_clobbers_display); \
> > > > > > > func(has_reset_engine); \
> > > > > > > + func(has_4tile); \
> > > > > > > func(has_global_mocs); \
> > > > > > > func(has_gt_uc); \
> > > > > > > func(has_l3_dpf); \
> > > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > > > b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > index 01fa3fac1b57..167704f0acf0 100644
> > > > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > > @@ -5386,6 +5386,7 @@ skl_compute_wm_params(const struct
> > > > > intel_crtc_state *crtc_state,
> > > > > > > }
> > > > > > >
> > > > > > > wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
> > > > > > > + modifier == I915_FORMAT_MOD_4_TILED ||
> > > > > > > modifier == I915_FORMAT_MOD_Yf_TILED ||
> > > > > > > modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > > > > > > modifier ==
> > > > > > > I915_FORMAT_MOD_Yf_TILED_CCS; diff --git
> > > > > > > a/include/uapi/drm/drm_fourcc.h
> > > > > b/include/uapi/drm/drm_fourcc.h
> > > > > > > index 7f652c96845b..41184a94935d 100644
> > > > > > > --- a/include/uapi/drm/drm_fourcc.h
> > > > > > > +++ b/include/uapi/drm/drm_fourcc.h
> > > > > > > @@ -564,6 +564,14 @@ extern "C" {
> > > > > > > * pitch is required to be a multiple of 4 tile widths.
> > > > > > > */
> > > > > > > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> > > > > fourcc_mod_code(INTEL, 8)
> > > > > > > +/*
> > > > > > > + * Intel F-tiling(aka Tile4) layout
> > > > > > > + *
> > > > > >
> > > > > > v4 and v5 attempted to get rid of the F-tile references, but
> > > > > > this was left behind.
> > > > > >
> > > > > > > + * This is a tiled layout using 4Kb tiles in row-major layout.
> > > > > > > + * Within the tile pixels are laid out in 64 byte units /
> > > > > > > + sub-tiles in OWORD
> > > > > > > + * (16 bytes) chunks column-major..
> > > > > >
> > > > > > I can't picture how tile 4 is organized from this description.
> > > > > > Could we update it?
> > > > > > Here's a draft I came up with when wondering how I might do this
> myself:
> > > > > >
> > > > > > * This is a tiled layout using 4KB tiles in a row-major
> > > > > > layout. It has the same
> > > > > > * shape as Tile Y at two granularities: 4KB (128B x 32) and
> > > > > > 64B (16B x 4). It
> > > > > > * only differs from Tile Y at the 256B granularity in between.
> > > > > > At this
> > > > > > * granularity, Tile Y has a shape of 16B x 32 rows, but this
> > > > > > tiling has a shape
> > > > > > * of 64B x 8 rows.
> > > > > >
> > > > > > -Nanley
> > > > > >
> > > > > > > + */
> > > > > > > +#define I915_FORMAT_MOD_4_TILED
> fourcc_mod_code(INTEL, 9)
> > > > > > >
> > > > > > > /*
> > > > > > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines)
> > > > > > > -sized macroblocks
> > > > > > > --
> > > > > > > 2.24.1.485.gad05a3d8e5
> > > > > > >
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
2021-11-22 22:08 ` [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support Nanley Chery
2021-11-23 8:13 ` Lisovskiy, Stanislav
@ 2021-11-23 16:20 ` Imre Deak
1 sibling, 0 replies; 28+ messages in thread
From: Imre Deak @ 2021-11-23 16:20 UTC (permalink / raw)
To: Nanley Chery; +Cc: intel-gfx, Nanley Chery
On Mon, Nov 22, 2021 at 05:08:31PM -0500, Nanley Chery wrote:
> Hi Stanislav,
>
> Are there IGT tests for this modifier?
>
> On Mon, Nov 22, 2021 at 4:14 PM Stanislav Lisovskiy
> <stanislav.lisovskiy@intel.com> wrote:
> >
> > TileF(Tile4 in bspec) format is 4K tile organized into
> > 64B subtiles with same basic shape as for legacy TileY
> > which will be supported by Display13.
> >
> > v2: - Fixed wrong case condition(Jani Nikula)
> > - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
> >
> > v3: - s/I915_TILING_F/TILING_4/g
> > - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
> > - Removed unneeded fencing code
> >
> > v4: - Rebased, fixed merge conflict with new table-oriented
> > format modifier checking(Stan)
> > - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
> >
> > v5: - Still had to remove some Tile F mentionings
> > - Moved has_4tile from adlp to DG2(Ramalingam C)
> > - Check specifically for DG2, but not the Display13(Imre)
> >
> > v6: - Moved Tile4 assocating struct for modifier/display to
> > the beginning(Imre Deak)
> > - Removed unneeded case I915_FORMAT_MOD_4_TILED modifier
> > checks(Imre Deak)
> > - Fixed I915_FORMAT_MOD_4_TILED to be 9 instead of 12
> > (Imre Deak)
> >
> > v7: - Fixed display_ver to { 13, 13 }(Imre Deak)
> > - Removed redundant newline(Imre Deak)
> >
> > Reviewed-by: Imre Deak <imre.deak@intel.com>
> > Cc: Imre Deak <imre.deak@intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 1 +
> > drivers/gpu/drm/i915/display/intel_fb.c | 9 +++++++++
> > drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> > .../drm/i915/display/intel_plane_initial.c | 1 +
> > .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/i915_pci.c | 1 +
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_device_info.h | 1 +
> > drivers/gpu/drm/i915/intel_pm.c | 1 +
> > include/uapi/drm/drm_fourcc.h | 8 ++++++++
> > 11 files changed, 37 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index f3c9208a30b1..7429965d3682 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -7766,6 +7766,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state, struct int
> > case I915_FORMAT_MOD_X_TILED:
> > case I915_FORMAT_MOD_Y_TILED:
> > case I915_FORMAT_MOD_Yf_TILED:
> > + case I915_FORMAT_MOD_4_TILED:
> > break;
> > default:
> > drm_dbg_kms(&i915->drm,
> > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> > index c4a743d0913f..b7f1ef62072c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > @@ -139,6 +139,9 @@ struct intel_modifier_desc {
> >
> > static const struct intel_modifier_desc intel_modifiers[] = {
> > {
> > + .modifier = I915_FORMAT_MOD_4_TILED,
> > + .display_ver = { 13, 13 },
>
> I see that every other modifier has the plane_cap field set. Why is it
> okay for it to be zero here?
Yes, missed this. The INTEL_PLANE_CAP_TILING_4 flag needs to be added
and returned from skl_get_plane_caps() for HAS_4TILE() platforms and
here we need to set this flag.
> > + }, {
> > .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> > .display_ver = { 12, 13 },
> > .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_MC,
> > @@ -544,6 +547,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> > return 128;
> > else
> > return 512;
> > + case I915_FORMAT_MOD_4_TILED:
> > + /*
> > + * Each 4K tile consists of 64B(8*8) subtiles, with
> > + * same shape as Y Tile(i.e 4*16B OWords)
> > + */
> > + return 128;
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> > return 128;
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index d0c34bc3af6c..0ceabe40d8c9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -898,6 +898,7 @@ static bool tiling_is_valid(struct drm_i915_private *i915,
> > case I915_FORMAT_MOD_Y_TILED:
> > case I915_FORMAT_MOD_Yf_TILED:
> > return DISPLAY_VER(i915) >= 9;
> > + case I915_FORMAT_MOD_4_TILED:
>
> The tile Y cases above check the display version. Should we do the same here?
I don't think we need a display version check (here or above), since
the modifiers will be passed to this func only on platforms supporting
them.
> > case I915_FORMAT_MOD_X_TILED:
> > return true;
> > default:
> > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > index dcd698a02da2..d80855ee9b96 100644
> > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
> > case DRM_FORMAT_MOD_LINEAR:
> > case I915_FORMAT_MOD_X_TILED:
> > case I915_FORMAT_MOD_Y_TILED:
> > + case I915_FORMAT_MOD_4_TILED:
> > break;
> > default:
> > drm_dbg(&dev_priv->drm,
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 28890876bdeb..e5cda5bcbde4 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> > return PLANE_CTL_TILED_X;
> > case I915_FORMAT_MOD_Y_TILED:
> > return PLANE_CTL_TILED_Y;
> > + case I915_FORMAT_MOD_4_TILED:
> > + return PLANE_CTL_TILED_4;
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> > @@ -1971,9 +1973,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> > case DRM_FORMAT_Y216:
> > case DRM_FORMAT_XVYU12_16161616:
> > case DRM_FORMAT_XVYU16161616:
> > - if (modifier == DRM_FORMAT_MOD_LINEAR ||
> > - modifier == I915_FORMAT_MOD_X_TILED ||
> > - modifier == I915_FORMAT_MOD_Y_TILED)
> > + if (!intel_fb_is_ccs_modifier(modifier))
> > return true;
> > fallthrough;
> > default:
> > @@ -2299,11 +2299,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> > else
> > fb->modifier = I915_FORMAT_MOD_Y_TILED;
> > break;
> > - case PLANE_CTL_TILED_YF:
> > - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > - else
> > - fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
>
> To be safe, maybe add a static_assert(PLANE_CTL_TILED_YF ==
> PLANE_CTL_TILED_4); ?
>
> > + if (HAS_4TILE(dev_priv)) {
> > + fb->modifier = I915_FORMAT_MOD_4_TILED;
> > + } else {
> > + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > + else
> > + fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > + }
> > break;
> > default:
> > MISSING_CASE(tiling);
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 1bfadd9127fc..3d90bd732e91 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
> >
> > #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
> > +#define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
> > #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
> > #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
> > #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > index f01cba4ec283..403d3a581ce7 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -1044,6 +1044,7 @@ static const struct intel_device_info dg2_info = {
> > DGFX_FEATURES,
> > .graphics.rel = 55,
> > .media.rel = 55,
> > + .has_4tile = 1,
> > PLATFORM(INTEL_DG2),
> > .platform_engine_mask =
> > BIT(RCS0) | BIT(BCS0) |
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 3450818802c2..22d18a292430 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7284,6 +7284,7 @@ enum {
> > #define PLANE_CTL_TILED_X (1 << 10)
> > #define PLANE_CTL_TILED_Y (4 << 10)
> > #define PLANE_CTL_TILED_YF (5 << 10)
> > +#define PLANE_CTL_TILED_4 (5 << 10)
> > #define PLANE_CTL_ASYNC_FLIP (1 << 9)
> > #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> > #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> > index 669f0d26c3c3..67177e18704a 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -125,6 +125,7 @@ enum intel_ppgtt_type {
> > func(has_64bit_reloc); \
> > func(gpu_reset_clobbers_display); \
> > func(has_reset_engine); \
> > + func(has_4tile); \
> > func(has_global_mocs); \
> > func(has_gt_uc); \
> > func(has_l3_dpf); \
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 01fa3fac1b57..167704f0acf0 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -5386,6 +5386,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> > }
> >
> > wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
> > + modifier == I915_FORMAT_MOD_4_TILED ||
> > modifier == I915_FORMAT_MOD_Yf_TILED ||
> > modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > index 7f652c96845b..41184a94935d 100644
> > --- a/include/uapi/drm/drm_fourcc.h
> > +++ b/include/uapi/drm/drm_fourcc.h
> > @@ -564,6 +564,14 @@ extern "C" {
> > * pitch is required to be a multiple of 4 tile widths.
> > */
> > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> > +/*
> > + * Intel F-tiling(aka Tile4) layout
> > + *
>
> v4 and v5 attempted to get rid of the F-tile references, but this was
> left behind.
>
> > + * This is a tiled layout using 4Kb tiles in row-major layout.
> > + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
> > + * (16 bytes) chunks column-major..
>
> I can't picture how tile 4 is organized from this description. Could
> we update it?
> Here's a draft I came up with when wondering how I might do this myself:
>
> * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
> * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
> * only differs from Tile Y at the 256B granularity in between. At this
> * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
> * of 64B x 8 rows.
>
> -Nanley
>
> > + */
> > +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)
> >
> > /*
> > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > --
> > 2.24.1.485.gad05a3d8e5
> >
^ permalink raw reply [flat|nested] 28+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
@ 2021-11-25 11:10 Stanislav Lisovskiy
0 siblings, 0 replies; 28+ messages in thread
From: Stanislav Lisovskiy @ 2021-11-25 11:10 UTC (permalink / raw)
To: intel-gfx; +Cc: nanley.g.chery
Tile4 in bspec format is 4K tile organized into
64B subtiles with same basic shape as for legacy TileY
which will be supported by Display13.
v2: - Moved Tile4 assocating struct for modifier/display to
the beginning(Imre Deak)
- Removed unneeded case I915_FORMAT_MOD_4_TILED modifier
checks(Imre Deak)
- Fixed I915_FORMAT_MOD_4_TILED to be 9 instead of 12
(Imre Deak)
v3: - Rebased patch on top of new changes related to plane_caps.
- Added static assert to check that PLANE_CTL_TILING_YF
matches PLANE_CTL_TILING_4(Nanley Chery)
- Fixed naming and layout description for Tile 4 in drm uapi
header(Nanley Chery)
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_fb.c | 15 +++++++++++-
drivers/gpu/drm/i915/display/intel_fb.h | 1 +
drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
.../drm/i915/display/intel_plane_initial.c | 1 +
.../drm/i915/display/skl_universal_plane.c | 23 ++++++++++++-------
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 1 +
include/uapi/drm/drm_fourcc.h | 11 +++++++++
12 files changed, 49 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b2d51cd79d6c..760e1bb92876 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7769,6 +7769,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state, struct int
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
+ case I915_FORMAT_MOD_4_TILED:
break;
default:
drm_dbg_kms(&i915->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index c4a743d0913f..153f759513a3 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -134,11 +134,16 @@ struct intel_modifier_desc {
INTEL_PLANE_CAP_CCS_MC)
#define INTEL_PLANE_CAP_TILING_MASK (INTEL_PLANE_CAP_TILING_X | \
INTEL_PLANE_CAP_TILING_Y | \
- INTEL_PLANE_CAP_TILING_Yf)
+ INTEL_PLANE_CAP_TILING_Yf | \
+ INTEL_PLANE_CAP_TILING_4)
#define INTEL_PLANE_CAP_TILING_NONE 0
static const struct intel_modifier_desc intel_modifiers[] = {
{
+ .modifier = I915_FORMAT_MOD_4_TILED,
+ .display_ver = { 13, 14 },
+ .plane_caps = INTEL_PLANE_CAP_TILING_4,
+ }, {
.modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
.display_ver = { 12, 13 },
.plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_MC,
@@ -544,6 +549,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
return 128;
else
return 512;
+ case I915_FORMAT_MOD_4_TILED:
+ /*
+ * Each 4K tile consists of 64B(8*8) subtiles, with
+ * same shape as Y Tile(i.e 4*16B OWords)
+ */
+ return 128;
case I915_FORMAT_MOD_Y_TILED_CCS:
if (intel_fb_is_ccs_aux_plane(fb, color_plane))
return 128;
@@ -649,6 +660,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
return I915_TILING_Y;
case INTEL_PLANE_CAP_TILING_X:
return I915_TILING_X;
+ case INTEL_PLANE_CAP_TILING_4:
case INTEL_PLANE_CAP_TILING_Yf:
case INTEL_PLANE_CAP_TILING_NONE:
return I915_TILING_NONE;
@@ -726,6 +738,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED:
+ case I915_FORMAT_MOD_4_TILED:
case I915_FORMAT_MOD_Yf_TILED:
return 1 * 1024 * 1024;
default:
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
index b54997175d6d..e46fb05799f8 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -27,6 +27,7 @@ struct intel_plane_state;
#define INTEL_PLANE_CAP_TILING_X BIT(3)
#define INTEL_PLANE_CAP_TILING_Y BIT(4)
#define INTEL_PLANE_CAP_TILING_Yf BIT(5)
+#define INTEL_PLANE_CAP_TILING_4 BIT(6)
bool intel_fb_is_ccs_modifier(u64 modifier);
bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier);
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index d0c34bc3af6c..0ceabe40d8c9 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -898,6 +898,7 @@ static bool tiling_is_valid(struct drm_i915_private *i915,
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
return DISPLAY_VER(i915) >= 9;
+ case I915_FORMAT_MOD_4_TILED:
case I915_FORMAT_MOD_X_TILED:
return true;
default:
diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index dcd698a02da2..d80855ee9b96 100644
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
+ case I915_FORMAT_MOD_4_TILED:
break;
default:
drm_dbg(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 28890876bdeb..b6a866882fcb 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
return PLANE_CTL_TILED_X;
case I915_FORMAT_MOD_Y_TILED:
return PLANE_CTL_TILED_Y;
+ case I915_FORMAT_MOD_4_TILED:
+ return PLANE_CTL_TILED_4;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
@@ -1971,9 +1973,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_Y216:
case DRM_FORMAT_XVYU12_16161616:
case DRM_FORMAT_XVYU16161616:
- if (modifier == DRM_FORMAT_MOD_LINEAR ||
- modifier == I915_FORMAT_MOD_X_TILED ||
- modifier == I915_FORMAT_MOD_Y_TILED)
+ if (!intel_fb_is_ccs_modifier(modifier))
return true;
fallthrough;
default:
@@ -2066,6 +2066,8 @@ static u8 skl_get_plane_caps(struct drm_i915_private *i915,
caps |= INTEL_PLANE_CAP_TILING_Y;
if (DISPLAY_VER(i915) < 12)
caps |= INTEL_PLANE_CAP_TILING_Yf;
+ if (HAS_4TILE(i915))
+ caps |= INTEL_PLANE_CAP_TILING_4;
if (skl_plane_has_rc_ccs(i915, pipe, plane_id)) {
caps |= INTEL_PLANE_CAP_CCS_RC;
@@ -2238,6 +2240,7 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
unsigned int aligned_height;
struct drm_framebuffer *fb;
struct intel_framebuffer *intel_fb;
+ static_assert(PLANE_CTL_TILED_YF == PLANE_CTL_TILED_4);
if (!plane->get_hw_state(plane, &pipe))
return;
@@ -2299,11 +2302,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
else
fb->modifier = I915_FORMAT_MOD_Y_TILED;
break;
- case PLANE_CTL_TILED_YF:
- if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
- fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
- else
- fb->modifier = I915_FORMAT_MOD_Yf_TILED;
+ case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
+ if (HAS_4TILE(dev_priv)) {
+ fb->modifier = I915_FORMAT_MOD_4_TILED;
+ } else {
+ if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
+ fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
+ else
+ fb->modifier = I915_FORMAT_MOD_Yf_TILED;
+ }
break;
default:
MISSING_CASE(tiling);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1bfadd9127fc..7781ccd05a33 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
#define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
+#define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
#define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
#define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
#define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f01cba4ec283..403d3a581ce7 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1044,6 +1044,7 @@ static const struct intel_device_info dg2_info = {
DGFX_FEATURES,
.graphics.rel = 55,
.media.rel = 55,
+ .has_4tile = 1,
PLATFORM(INTEL_DG2),
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3450818802c2..22d18a292430 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7284,6 +7284,7 @@ enum {
#define PLANE_CTL_TILED_X (1 << 10)
#define PLANE_CTL_TILED_Y (4 << 10)
#define PLANE_CTL_TILED_YF (5 << 10)
+#define PLANE_CTL_TILED_4 (5 << 10)
#define PLANE_CTL_ASYNC_FLIP (1 << 9)
#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 669f0d26c3c3..67177e18704a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -125,6 +125,7 @@ enum intel_ppgtt_type {
func(has_64bit_reloc); \
func(gpu_reset_clobbers_display); \
func(has_reset_engine); \
+ func(has_4tile); \
func(has_global_mocs); \
func(has_gt_uc); \
func(has_l3_dpf); \
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 01fa3fac1b57..167704f0acf0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5386,6 +5386,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
}
wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
+ modifier == I915_FORMAT_MOD_4_TILED ||
modifier == I915_FORMAT_MOD_Yf_TILED ||
modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 7f652c96845b..a146c6df1066 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -565,6 +565,17 @@ extern "C" {
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
+/*
+ * Intel Tile 4 layout
+ *
+ * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
+ * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
+ * only differs from Tile Y at the 256B granularity in between. At this
+ * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
+ * of 64B x 8 rows.
+ */
+#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.24.1.485.gad05a3d8e5
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
@ 2021-11-18 12:24 Stanislav Lisovskiy
0 siblings, 0 replies; 28+ messages in thread
From: Stanislav Lisovskiy @ 2021-11-18 12:24 UTC (permalink / raw)
To: intel-gfx
TileF(Tile4 in bspec) format is 4K tile organized into
64B subtiles with same basic shape as for legacy TileY
which will be supported by Display13.
v2: - Fixed wrong case condition(Jani Nikula)
- Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
v3: - s/I915_TILING_F/TILING_4/g
- s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
- Removed unneeded fencing code
v4: - Rebased, fixed merge conflict with new table-oriented
format modifier checking(Stan)
- Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
v5: - Still had to remove some Tile F mentionings
- Moved has_4tile from adlp to DG2(Ramalingam C)
- Check specifically for DG2, but not the Display13(Imre)
v6: - Moved Tile4 assocating struct for modifier/display to
the beginning(Imre Deak)
- Removed unneeded case I915_FORMAT_MOD_4_TILED modifier
checks(Imre Deak)
- Fixed I915_FORMAT_MOD_4_TILED to be 9 instead of 12
(Imre Deak)
Reviewed-by: Imre Deak <imre.deak@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_fb.c | 10 ++++++++++
drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
.../drm/i915/display/intel_plane_initial.c | 1 +
.../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 1 +
include/uapi/drm/drm_fourcc.h | 8 ++++++++
11 files changed, 38 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f3c9208a30b1..7429965d3682 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7766,6 +7766,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state, struct int
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
+ case I915_FORMAT_MOD_4_TILED:
break;
default:
drm_dbg_kms(&i915->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index c4a743d0913f..2a0c562f6494 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -139,6 +139,9 @@ struct intel_modifier_desc {
static const struct intel_modifier_desc intel_modifiers[] = {
{
+ .modifier = I915_FORMAT_MOD_4_TILED,
+ .display_ver = { 12, 13 },
+ }, {
.modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
.display_ver = { 12, 13 },
.plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_MC,
@@ -184,6 +187,7 @@ static const struct intel_modifier_desc intel_modifiers[] = {
.modifier = I915_FORMAT_MOD_Yf_TILED,
.display_ver = { 9, 11 },
.plane_caps = INTEL_PLANE_CAP_TILING_Yf,
+
}, {
.modifier = I915_FORMAT_MOD_Y_TILED,
.display_ver = { 9, 13 },
@@ -544,6 +548,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
return 128;
else
return 512;
+ case I915_FORMAT_MOD_4_TILED:
+ /*
+ * Each 4K tile consists of 64B(8*8) subtiles, with
+ * same shape as Y Tile(i.e 4*16B OWords)
+ */
+ return 128;
case I915_FORMAT_MOD_Y_TILED_CCS:
if (intel_fb_is_ccs_aux_plane(fb, color_plane))
return 128;
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index d0c34bc3af6c..0ceabe40d8c9 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -898,6 +898,7 @@ static bool tiling_is_valid(struct drm_i915_private *i915,
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
return DISPLAY_VER(i915) >= 9;
+ case I915_FORMAT_MOD_4_TILED:
case I915_FORMAT_MOD_X_TILED:
return true;
default:
diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index dcd698a02da2..d80855ee9b96 100644
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
+ case I915_FORMAT_MOD_4_TILED:
break;
default:
drm_dbg(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 28890876bdeb..e5cda5bcbde4 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
return PLANE_CTL_TILED_X;
case I915_FORMAT_MOD_Y_TILED:
return PLANE_CTL_TILED_Y;
+ case I915_FORMAT_MOD_4_TILED:
+ return PLANE_CTL_TILED_4;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
@@ -1971,9 +1973,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_Y216:
case DRM_FORMAT_XVYU12_16161616:
case DRM_FORMAT_XVYU16161616:
- if (modifier == DRM_FORMAT_MOD_LINEAR ||
- modifier == I915_FORMAT_MOD_X_TILED ||
- modifier == I915_FORMAT_MOD_Y_TILED)
+ if (!intel_fb_is_ccs_modifier(modifier))
return true;
fallthrough;
default:
@@ -2299,11 +2299,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
else
fb->modifier = I915_FORMAT_MOD_Y_TILED;
break;
- case PLANE_CTL_TILED_YF:
- if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
- fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
- else
- fb->modifier = I915_FORMAT_MOD_Yf_TILED;
+ case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
+ if (HAS_4TILE(dev_priv)) {
+ fb->modifier = I915_FORMAT_MOD_4_TILED;
+ } else {
+ if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
+ fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
+ else
+ fb->modifier = I915_FORMAT_MOD_Yf_TILED;
+ }
break;
default:
MISSING_CASE(tiling);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f2a546d58481..bb0400f1c679 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
#define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
+#define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
#define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
#define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
#define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 8449ce843b91..5dff145e46db 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1038,6 +1038,7 @@ static const struct intel_device_info dg2_info = {
DGFX_FEATURES,
.graphics.rel = 55,
.media.rel = 55,
+ .has_4tile = 1,
PLATFORM(INTEL_DG2),
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f15ffc53e858..7813a56473e5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7279,6 +7279,7 @@ enum {
#define PLANE_CTL_TILED_X (1 << 10)
#define PLANE_CTL_TILED_Y (4 << 10)
#define PLANE_CTL_TILED_YF (5 << 10)
+#define PLANE_CTL_TILED_4 (5 << 10)
#define PLANE_CTL_ASYNC_FLIP (1 << 9)
#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 669f0d26c3c3..67177e18704a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -125,6 +125,7 @@ enum intel_ppgtt_type {
func(has_64bit_reloc); \
func(gpu_reset_clobbers_display); \
func(has_reset_engine); \
+ func(has_4tile); \
func(has_global_mocs); \
func(has_gt_uc); \
func(has_l3_dpf); \
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 89dc7f69baf3..310588354202 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5378,6 +5378,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
}
wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
+ modifier == I915_FORMAT_MOD_4_TILED ||
modifier == I915_FORMAT_MOD_Yf_TILED ||
modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 7f652c96845b..41184a94935d 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -564,6 +564,14 @@ extern "C" {
* pitch is required to be a multiple of 4 tile widths.
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
+/*
+ * Intel F-tiling(aka Tile4) layout
+ *
+ * This is a tiled layout using 4Kb tiles in row-major layout.
+ * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
+ * (16 bytes) chunks column-major..
+ */
+#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
--
2.24.1.485.gad05a3d8e5
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
2021-11-17 11:01 Stanislav Lisovskiy
@ 2021-11-17 14:33 ` Imre Deak
0 siblings, 0 replies; 28+ messages in thread
From: Imre Deak @ 2021-11-17 14:33 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Wed, Nov 17, 2021 at 01:01:00PM +0200, Stanislav Lisovskiy wrote:
> TileF(Tile4 in bspec) format is 4K tile organized into
> 64B subtiles with same basic shape as for legacy TileY
> which will be supported by Display13.
>
> v2: - Fixed wrong case condition(Jani Nikula)
> - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
>
> v3: - s/I915_TILING_F/TILING_4/g
> - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
> - Removed unneeded fencing code
>
> v4: - Rebased, fixed merge conflict with new table-oriented
> format modifier checking(Stan)
> - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
>
> v5: - Still had to remove some Tile F mentionings
> - Moved has_4tile from adlp to DG2(Ramalingam)
> - Check specifically for DG2, but not the Display13(Imre)
>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 1 +
> drivers/gpu/drm/i915/display/intel_fb.c | 10 ++++++++++
> drivers/gpu/drm/i915/display/intel_fbc.c | 2 ++
> .../drm/i915/display/intel_plane_initial.c | 1 +
> .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 1 +
> include/uapi/drm/drm_fourcc.h | 8 ++++++++
> 11 files changed, 39 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 0ceee8ac6671..eaea986dff99 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7743,6 +7743,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state, struct int
> case I915_FORMAT_MOD_X_TILED:
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Yf_TILED:
> + case I915_FORMAT_MOD_4_TILED:
> break;
> default:
> drm_dbg_kms(&i915->drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> index c4a743d0913f..a3d465e111d8 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -184,6 +184,9 @@ static const struct intel_modifier_desc intel_modifiers[] = {
> .modifier = I915_FORMAT_MOD_Yf_TILED,
> .display_ver = { 9, 11 },
> .plane_caps = INTEL_PLANE_CAP_TILING_Yf,
> + }, {
> + .modifier = I915_FORMAT_MOD_4_TILED,
> + .display_ver = { 12, 13 },
Starting from display version 13. The list is priority ordered so this
needs to be the first item.
> }, {
> .modifier = I915_FORMAT_MOD_Y_TILED,
> .display_ver = { 9, 13 },
> @@ -544,6 +547,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> return 128;
> else
> return 512;
> + case I915_FORMAT_MOD_4_TILED:
> + /*
> + * Each 4K tile consists of 64B(8*8) subtiles, with
> + * same shape as Y Tile(i.e 4*16B OWords)
> + */
> + return 128;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> return 128;
> @@ -726,6 +735,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Yf_TILED_CCS:
> case I915_FORMAT_MOD_Y_TILED:
> + case I915_FORMAT_MOD_4_TILED:
The 4-tiled formats need to be mapped via DPT on all platforms, which is
handled earlier in the func, so handling it here shouldn't be needed.
> case I915_FORMAT_MOD_Yf_TILED:
> return 1 * 1024 * 1024;
> default:
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index d0c34bc3af6c..5f2ad0f4bd81 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -898,6 +898,8 @@ static bool tiling_is_valid(struct drm_i915_private *i915,
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Yf_TILED:
> return DISPLAY_VER(i915) >= 9;
> + case I915_FORMAT_MOD_4_TILED:
> + return HAS_4TILE(i915);
Could return true always, since only HAS_4TILE() platforms will use/pass
to this func the modifier.
> case I915_FORMAT_MOD_X_TILED:
> return true;
> default:
> diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> index dcd698a02da2..d80855ee9b96 100644
> --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
> case DRM_FORMAT_MOD_LINEAR:
> case I915_FORMAT_MOD_X_TILED:
> case I915_FORMAT_MOD_Y_TILED:
> + case I915_FORMAT_MOD_4_TILED:
> break;
> default:
> drm_dbg(&dev_priv->drm,
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 28890876bdeb..000c99ae4042 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> return PLANE_CTL_TILED_X;
> case I915_FORMAT_MOD_Y_TILED:
> return PLANE_CTL_TILED_Y;
> + case I915_FORMAT_MOD_4_TILED:
> + return PLANE_CTL_TILED_4;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> @@ -1971,9 +1973,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> case DRM_FORMAT_Y216:
> case DRM_FORMAT_XVYU12_16161616:
> case DRM_FORMAT_XVYU16161616:
> - if (modifier == DRM_FORMAT_MOD_LINEAR ||
> - modifier == I915_FORMAT_MOD_X_TILED ||
> - modifier == I915_FORMAT_MOD_Y_TILED)
> + if (!intel_fb_is_ccs_modifier(modifier))
> return true;
> fallthrough;
> default:
> @@ -2299,11 +2299,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> else
> fb->modifier = I915_FORMAT_MOD_Y_TILED;
> break;
> - case PLANE_CTL_TILED_YF:
> - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> - else
> - fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
> + if ((DISPLAY_VER(dev_priv) >= 13) && HAS_4TILE(dev_priv)) {
Could be just HAS_4TILE().
> + fb->modifier = I915_FORMAT_MOD_4_TILED;
> + } else {
> + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> + else
> + fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> + }
> break;
> default:
> MISSING_CASE(tiling);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6f9f20a10c0c..d4be97419332 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
>
> #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
> +#define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
> #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
> #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
> #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 4c7fcc5f9a97..49da25d736af 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -1037,6 +1037,7 @@ static const struct intel_device_info dg2_info = {
> DGFX_FEATURES,
> .graphics.rel = 55,
> .media.rel = 55,
> + .has_4tile = 1,
> PLATFORM(INTEL_DG2),
> .platform_engine_mask =
> BIT(RCS0) | BIT(BCS0) |
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f15ffc53e858..7813a56473e5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7279,6 +7279,7 @@ enum {
> #define PLANE_CTL_TILED_X (1 << 10)
> #define PLANE_CTL_TILED_Y (4 << 10)
> #define PLANE_CTL_TILED_YF (5 << 10)
> +#define PLANE_CTL_TILED_4 (5 << 10)
> #define PLANE_CTL_ASYNC_FLIP (1 << 9)
> #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 669f0d26c3c3..67177e18704a 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -125,6 +125,7 @@ enum intel_ppgtt_type {
> func(has_64bit_reloc); \
> func(gpu_reset_clobbers_display); \
> func(has_reset_engine); \
> + func(has_4tile); \
> func(has_global_mocs); \
> func(has_gt_uc); \
> func(has_l3_dpf); \
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 89dc7f69baf3..310588354202 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5378,6 +5378,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> }
>
> wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
> + modifier == I915_FORMAT_MOD_4_TILED ||
> modifier == I915_FORMAT_MOD_Yf_TILED ||
> modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 7f652c96845b..cb64d810c15d 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -564,6 +564,14 @@ extern "C" {
> * pitch is required to be a multiple of 4 tile widths.
> */
> #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> +/*
> + * Intel F-tiling(aka Tile4) layout
> + *
> + * This is a tiled layout using 4Kb tiles in row-major layout.
> + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
> + * (16 bytes) chunks column-major..
> + */
> +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 12)
The encoding should be 9. I requested keeping this at 12 originally, but
that request can be ignored, as there is no need to reserve the space
for ADLP modifiers.
With the above comments addressed the patch looks ok:
Reviewed-by: Imre Deak <imre.deak@intel.com>
>
> /*
> * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> --
> 2.24.1.485.gad05a3d8e5
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
@ 2021-11-17 11:01 Stanislav Lisovskiy
2021-11-17 14:33 ` Imre Deak
0 siblings, 1 reply; 28+ messages in thread
From: Stanislav Lisovskiy @ 2021-11-17 11:01 UTC (permalink / raw)
To: intel-gfx
TileF(Tile4 in bspec) format is 4K tile organized into
64B subtiles with same basic shape as for legacy TileY
which will be supported by Display13.
v2: - Fixed wrong case condition(Jani Nikula)
- Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
v3: - s/I915_TILING_F/TILING_4/g
- s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
- Removed unneeded fencing code
v4: - Rebased, fixed merge conflict with new table-oriented
format modifier checking(Stan)
- Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
v5: - Still had to remove some Tile F mentionings
- Moved has_4tile from adlp to DG2(Ramalingam)
- Check specifically for DG2, but not the Display13(Imre)
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_fb.c | 10 ++++++++++
drivers/gpu/drm/i915/display/intel_fbc.c | 2 ++
.../drm/i915/display/intel_plane_initial.c | 1 +
.../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 1 +
include/uapi/drm/drm_fourcc.h | 8 ++++++++
11 files changed, 39 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0ceee8ac6671..eaea986dff99 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7743,6 +7743,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state, struct int
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
+ case I915_FORMAT_MOD_4_TILED:
break;
default:
drm_dbg_kms(&i915->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index c4a743d0913f..a3d465e111d8 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -184,6 +184,9 @@ static const struct intel_modifier_desc intel_modifiers[] = {
.modifier = I915_FORMAT_MOD_Yf_TILED,
.display_ver = { 9, 11 },
.plane_caps = INTEL_PLANE_CAP_TILING_Yf,
+ }, {
+ .modifier = I915_FORMAT_MOD_4_TILED,
+ .display_ver = { 12, 13 },
}, {
.modifier = I915_FORMAT_MOD_Y_TILED,
.display_ver = { 9, 13 },
@@ -544,6 +547,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
return 128;
else
return 512;
+ case I915_FORMAT_MOD_4_TILED:
+ /*
+ * Each 4K tile consists of 64B(8*8) subtiles, with
+ * same shape as Y Tile(i.e 4*16B OWords)
+ */
+ return 128;
case I915_FORMAT_MOD_Y_TILED_CCS:
if (intel_fb_is_ccs_aux_plane(fb, color_plane))
return 128;
@@ -726,6 +735,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED:
+ case I915_FORMAT_MOD_4_TILED:
case I915_FORMAT_MOD_Yf_TILED:
return 1 * 1024 * 1024;
default:
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index d0c34bc3af6c..5f2ad0f4bd81 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -898,6 +898,8 @@ static bool tiling_is_valid(struct drm_i915_private *i915,
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
return DISPLAY_VER(i915) >= 9;
+ case I915_FORMAT_MOD_4_TILED:
+ return HAS_4TILE(i915);
case I915_FORMAT_MOD_X_TILED:
return true;
default:
diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index dcd698a02da2..d80855ee9b96 100644
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
+ case I915_FORMAT_MOD_4_TILED:
break;
default:
drm_dbg(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 28890876bdeb..000c99ae4042 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
return PLANE_CTL_TILED_X;
case I915_FORMAT_MOD_Y_TILED:
return PLANE_CTL_TILED_Y;
+ case I915_FORMAT_MOD_4_TILED:
+ return PLANE_CTL_TILED_4;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
@@ -1971,9 +1973,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_Y216:
case DRM_FORMAT_XVYU12_16161616:
case DRM_FORMAT_XVYU16161616:
- if (modifier == DRM_FORMAT_MOD_LINEAR ||
- modifier == I915_FORMAT_MOD_X_TILED ||
- modifier == I915_FORMAT_MOD_Y_TILED)
+ if (!intel_fb_is_ccs_modifier(modifier))
return true;
fallthrough;
default:
@@ -2299,11 +2299,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
else
fb->modifier = I915_FORMAT_MOD_Y_TILED;
break;
- case PLANE_CTL_TILED_YF:
- if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
- fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
- else
- fb->modifier = I915_FORMAT_MOD_Yf_TILED;
+ case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
+ if ((DISPLAY_VER(dev_priv) >= 13) && HAS_4TILE(dev_priv)) {
+ fb->modifier = I915_FORMAT_MOD_4_TILED;
+ } else {
+ if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
+ fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
+ else
+ fb->modifier = I915_FORMAT_MOD_Yf_TILED;
+ }
break;
default:
MISSING_CASE(tiling);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6f9f20a10c0c..d4be97419332 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
#define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
+#define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
#define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
#define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
#define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 4c7fcc5f9a97..49da25d736af 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1037,6 +1037,7 @@ static const struct intel_device_info dg2_info = {
DGFX_FEATURES,
.graphics.rel = 55,
.media.rel = 55,
+ .has_4tile = 1,
PLATFORM(INTEL_DG2),
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f15ffc53e858..7813a56473e5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7279,6 +7279,7 @@ enum {
#define PLANE_CTL_TILED_X (1 << 10)
#define PLANE_CTL_TILED_Y (4 << 10)
#define PLANE_CTL_TILED_YF (5 << 10)
+#define PLANE_CTL_TILED_4 (5 << 10)
#define PLANE_CTL_ASYNC_FLIP (1 << 9)
#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 669f0d26c3c3..67177e18704a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -125,6 +125,7 @@ enum intel_ppgtt_type {
func(has_64bit_reloc); \
func(gpu_reset_clobbers_display); \
func(has_reset_engine); \
+ func(has_4tile); \
func(has_global_mocs); \
func(has_gt_uc); \
func(has_l3_dpf); \
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 89dc7f69baf3..310588354202 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5378,6 +5378,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
}
wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
+ modifier == I915_FORMAT_MOD_4_TILED ||
modifier == I915_FORMAT_MOD_Yf_TILED ||
modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 7f652c96845b..cb64d810c15d 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -564,6 +564,14 @@ extern "C" {
* pitch is required to be a multiple of 4 tile widths.
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
+/*
+ * Intel F-tiling(aka Tile4) layout
+ *
+ * This is a tiled layout using 4Kb tiles in row-major layout.
+ * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
+ * (16 bytes) chunks column-major..
+ */
+#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 12)
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
--
2.24.1.485.gad05a3d8e5
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
2021-10-28 7:53 ` Imre Deak
@ 2021-10-28 7:57 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 28+ messages in thread
From: Lisovskiy, Stanislav @ 2021-10-28 7:57 UTC (permalink / raw)
To: Imre Deak
Cc: intel-gfx, jani.saarinen, matthew.d.roper, ramalingam.c, ville.syrjala
On Thu, Oct 28, 2021 at 10:53:25AM +0300, Imre Deak wrote:
> On Thu, Oct 28, 2021 at 10:49:34AM +0300, Lisovskiy, Stanislav wrote:
> > On Thu, Oct 28, 2021 at 10:39:42AM +0300, Imre Deak wrote:
> > > On Thu, Oct 28, 2021 at 09:58:52AM +0300, Lisovskiy, Stanislav wrote:
> > > > On Wed, Oct 27, 2021 at 07:56:25PM +0300, Imre Deak wrote:
> > > > > On Wed, Oct 27, 2021 at 06:46:53PM +0300, Stanislav Lisovskiy wrote:
> > > > > > TileF(Tile4 in bspec) format is 4K tile organized into
> > > > > > 64B subtiles with same basic shape as for legacy TileY
> > > > > > which will be supported by Display13.
> > > > >
> > > > > Is it supported on all D13 or only on DG2? Could you point to the bspec
> > > > > page describing this?
> > > >
> > > > Yes, it is supported on all D13 to my undertanding.
> > > > Check with BSpec 44917
> > >
> > > Thanks.
> > >
> > > Based on that page it's only supported on DG2 (and that's how the driver
> > > worked so far in the internal tree).
> >
> > I think its supported on some other platforms as well - when you click the Tile 4
> > section, check platform names in the brackets.
>
> Right, but from Display 13 platforms it's only DG2 (and not ADL-P the
> only other D13 platform).
True.
>
> >
> > Stan
> >
> > >
> > > > Stan
> > > >
> > > > >
> > > > > >
> > > > > > v2: - Fixed wrong case condition(Jani Nikula)
> > > > > > - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
> > > > > >
> > > > > > v3: - s/I915_TILING_F/TILING_4/g
> > > > > > - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
> > > > > > - Removed unneeded fencing code
> > > > > >
> > > > > > v4: - Rebased, fixed merge conflict with new table-oriented
> > > > > > format modifier checking(Stan)
> > > > > > - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
> > > > > >
> > > > > > Cc: Imre Deak <imre.deak@intel.com>
> > > > > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > > > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > > > > Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/display/intel_display.c | 1 +
> > > > > > drivers/gpu/drm/i915/display/intel_fb.c | 11 ++++++++++
> > > > > > drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> > > > > > .../drm/i915/display/intel_plane_initial.c | 1 +
> > > > > > .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
> > > > > > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > > > > > drivers/gpu/drm/i915/i915_pci.c | 1 +
> > > > > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > > > > drivers/gpu/drm/i915/intel_device_info.h | 1 +
> > > > > > drivers/gpu/drm/i915/intel_pm.c | 1 +
> > > > > > include/uapi/drm/drm_fourcc.h | 8 ++++++++
> > > > > > 11 files changed, 39 insertions(+), 8 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > index 79cd158503b3..9b3913d73213 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > @@ -7755,6 +7755,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
> > > > > > case I915_FORMAT_MOD_X_TILED:
> > > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > > case I915_FORMAT_MOD_Yf_TILED:
> > > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > > break;
> > > > > > default:
> > > > > > drm_dbg_kms(&i915->drm,
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> > > > > > index 9ce1d273dc7e..d3dec51285f7 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > > > > > @@ -188,6 +188,10 @@ static const struct intel_modifier_desc intel_modifiers[] = {
> > > > > > .modifier = I915_FORMAT_MOD_Yf_TILED,
> > > > > > .display_ver = { 9, 11 },
> > > > > > .tiling = I915_TILING_NONE,
> > > > > > + }, {
> > > > > > + .modifier = I915_FORMAT_MOD_4_TILED,
> > > > > > + .display_ver = { 12, 13 },
> > > > >
> > > > > From display_ver 13.
> > > > >
> > > > > > + .tiling = I915_TILING_NONE,
> > > > > > }, {
> > > > > > .modifier = I915_FORMAT_MOD_Y_TILED,
> > > > > > .display_ver = { 9, 13 },
> > > > > > @@ -575,6 +579,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> > > > > > return 128;
> > > > > > else
> > > > > > return 512;
> > > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > > + /*
> > > > > > + * Each 4K tile consists of 64B(8*8) subtiles, with
> > > > > > + * same shape as Y Tile(i.e 4*16B OWords)
> > > > > > + */
> > > > > > + return 128;
> > > > > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > > > > if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> > > > > > return 128;
> > > > > > @@ -743,6 +753,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> > > > > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > > > > case I915_FORMAT_MOD_Yf_TILED_CCS:
> > > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > > case I915_FORMAT_MOD_Yf_TILED:
> > > > > > return 1 * 1024 * 1024;
> > > > > > default:
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > > index 1f66de77a6b1..f079a771f802 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > > @@ -747,6 +747,7 @@ static bool tiling_is_valid(struct drm_i915_private *dev_priv,
> > > > > > case DRM_FORMAT_MOD_LINEAR:
> > > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > > case I915_FORMAT_MOD_Yf_TILED:
> > > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > > return DISPLAY_VER(dev_priv) >= 9;
> > > > > > case I915_FORMAT_MOD_X_TILED:
> > > > > > return true;
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > > > index dcd698a02da2..d80855ee9b96 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > > > @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
> > > > > > case DRM_FORMAT_MOD_LINEAR:
> > > > > > case I915_FORMAT_MOD_X_TILED:
> > > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > > break;
> > > > > > default:
> > > > > > drm_dbg(&dev_priv->drm,
> > > > > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > > index 69fd56de83a7..aeca96925feb 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > > @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> > > > > > return PLANE_CTL_TILED_X;
> > > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > > return PLANE_CTL_TILED_Y;
> > > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > > + return PLANE_CTL_TILED_4;
> > > > > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > > > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > > > > return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> > > > > > @@ -1930,9 +1932,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> > > > > > case DRM_FORMAT_Y216:
> > > > > > case DRM_FORMAT_XVYU12_16161616:
> > > > > > case DRM_FORMAT_XVYU16161616:
> > > > > > - if (modifier == DRM_FORMAT_MOD_LINEAR ||
> > > > > > - modifier == I915_FORMAT_MOD_X_TILED ||
> > > > > > - modifier == I915_FORMAT_MOD_Y_TILED)
> > > > > > + if (!intel_fb_is_ccs_modifier(modifier))
> > > > > > return true;
> > > > > > fallthrough;
> > > > > > default:
> > > > > > @@ -2241,11 +2241,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> > > > > > else
> > > > > > fb->modifier = I915_FORMAT_MOD_Y_TILED;
> > > > > > break;
> > > > > > - case PLANE_CTL_TILED_YF:
> > > > > > - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > > > - else
> > > > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > > > > > + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
> > > > > > + if (DISPLAY_VER(dev_priv) >= 13) {
> > > > > > + fb->modifier = I915_FORMAT_MOD_4_TILED;
> > > > > > + } else {
> > > > > > + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > > > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > > > + else
> > > > > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > > > > > + }
> > > > > > break;
> > > > > > default:
> > > > > > MISSING_CASE(tiling);
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > > > > index 19e6700a4315..0a32ce800677 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > > > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > > > > @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > > > > > #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
> > > > > >
> > > > > > #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
> > > > > > +#define HAS_FTILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
> > > > > > #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
> > > > > > #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
> > > > > > #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > > > > > index 169837de395d..8831b1885934 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > > > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > > > > @@ -972,6 +972,7 @@ static const struct intel_device_info adl_p_info = {
> > > > > > .display.has_cdclk_crawl = 1,
> > > > > > .display.has_modular_fia = 1,
> > > > > > .display.has_psr_hw_tracking = 0,
> > > > > > + .has_4tile = 1, \
> > > > >
> > > > > If it's only on DG2 then it should be added there.
> > > > >
> > > > > > .platform_engine_mask =
> > > > > > BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> > > > > > .ppgtt_size = 48,
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > > > > index 7c97bc352497..b70b72b032ef 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > > > @@ -7195,6 +7195,7 @@ enum {
> > > > > > #define PLANE_CTL_TILED_X (1 << 10)
> > > > > > #define PLANE_CTL_TILED_Y (4 << 10)
> > > > > > #define PLANE_CTL_TILED_YF (5 << 10)
> > > > > > +#define PLANE_CTL_TILED_4 (5 << 10)
> > > > > > #define PLANE_CTL_ASYNC_FLIP (1 << 9)
> > > > > > #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> > > > > > #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
> > > > > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> > > > > > index 8e6f48d1eb7b..6c543a152250 100644
> > > > > > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > > > > > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > > > > > @@ -125,6 +125,7 @@ enum intel_ppgtt_type {
> > > > > > func(has_64bit_reloc); \
> > > > > > func(gpu_reset_clobbers_display); \
> > > > > > func(has_reset_engine); \
> > > > > > + func(has_4tile); \
> > > > > > func(has_global_mocs); \
> > > > > > func(has_gt_uc); \
> > > > > > func(has_l3_dpf); \
> > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > index cffb3df35a63..1ac1af0a7f2d 100644
> > > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > @@ -5378,6 +5378,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> > > > > > }
> > > > > >
> > > > > > wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
> > > > > > + modifier == I915_FORMAT_MOD_4_TILED ||
> > > > > > modifier == I915_FORMAT_MOD_Yf_TILED ||
> > > > > > modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > > > > > modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > > > > > index 45a914850be0..982b0a9fa78b 100644
> > > > > > --- a/include/uapi/drm/drm_fourcc.h
> > > > > > +++ b/include/uapi/drm/drm_fourcc.h
> > > > > > @@ -558,6 +558,14 @@ extern "C" {
> > > > > > * pitch is required to be a multiple of 4 tile widths.
> > > > > > */
> > > > > > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> > > > > > +/*
> > > > > > + * Intel F-tiling(aka Tile4) layout
> > > > > > + *
> > > > > > + * This is a tiled layout using 4Kb tiles in row-major layout.
> > > > > > + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
> > > > > > + * (16 bytes) chunks column-major..
> > > > > > + */
> > > > > > +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 12)
> > > > > >
> > > > > > /*
> > > > > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > > > > > --
> > > > > > 2.24.1.485.gad05a3d8e5
> > > > > >
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
2021-10-28 7:49 ` Lisovskiy, Stanislav
@ 2021-10-28 7:53 ` Imre Deak
2021-10-28 7:57 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 28+ messages in thread
From: Imre Deak @ 2021-10-28 7:53 UTC (permalink / raw)
To: Lisovskiy, Stanislav
Cc: intel-gfx, jani.saarinen, matthew.d.roper, ramalingam.c, ville.syrjala
On Thu, Oct 28, 2021 at 10:49:34AM +0300, Lisovskiy, Stanislav wrote:
> On Thu, Oct 28, 2021 at 10:39:42AM +0300, Imre Deak wrote:
> > On Thu, Oct 28, 2021 at 09:58:52AM +0300, Lisovskiy, Stanislav wrote:
> > > On Wed, Oct 27, 2021 at 07:56:25PM +0300, Imre Deak wrote:
> > > > On Wed, Oct 27, 2021 at 06:46:53PM +0300, Stanislav Lisovskiy wrote:
> > > > > TileF(Tile4 in bspec) format is 4K tile organized into
> > > > > 64B subtiles with same basic shape as for legacy TileY
> > > > > which will be supported by Display13.
> > > >
> > > > Is it supported on all D13 or only on DG2? Could you point to the bspec
> > > > page describing this?
> > >
> > > Yes, it is supported on all D13 to my undertanding.
> > > Check with BSpec 44917
> >
> > Thanks.
> >
> > Based on that page it's only supported on DG2 (and that's how the driver
> > worked so far in the internal tree).
>
> I think its supported on some other platforms as well - when you click the Tile 4
> section, check platform names in the brackets.
Right, but from Display 13 platforms it's only DG2 (and not ADL-P the
only other D13 platform).
>
> Stan
>
> >
> > > Stan
> > >
> > > >
> > > > >
> > > > > v2: - Fixed wrong case condition(Jani Nikula)
> > > > > - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
> > > > >
> > > > > v3: - s/I915_TILING_F/TILING_4/g
> > > > > - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
> > > > > - Removed unneeded fencing code
> > > > >
> > > > > v4: - Rebased, fixed merge conflict with new table-oriented
> > > > > format modifier checking(Stan)
> > > > > - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
> > > > >
> > > > > Cc: Imre Deak <imre.deak@intel.com>
> > > > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > > > Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/display/intel_display.c | 1 +
> > > > > drivers/gpu/drm/i915/display/intel_fb.c | 11 ++++++++++
> > > > > drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> > > > > .../drm/i915/display/intel_plane_initial.c | 1 +
> > > > > .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
> > > > > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > > > > drivers/gpu/drm/i915/i915_pci.c | 1 +
> > > > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > > > drivers/gpu/drm/i915/intel_device_info.h | 1 +
> > > > > drivers/gpu/drm/i915/intel_pm.c | 1 +
> > > > > include/uapi/drm/drm_fourcc.h | 8 ++++++++
> > > > > 11 files changed, 39 insertions(+), 8 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > index 79cd158503b3..9b3913d73213 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > @@ -7755,6 +7755,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
> > > > > case I915_FORMAT_MOD_X_TILED:
> > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > case I915_FORMAT_MOD_Yf_TILED:
> > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > break;
> > > > > default:
> > > > > drm_dbg_kms(&i915->drm,
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> > > > > index 9ce1d273dc7e..d3dec51285f7 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > > > > @@ -188,6 +188,10 @@ static const struct intel_modifier_desc intel_modifiers[] = {
> > > > > .modifier = I915_FORMAT_MOD_Yf_TILED,
> > > > > .display_ver = { 9, 11 },
> > > > > .tiling = I915_TILING_NONE,
> > > > > + }, {
> > > > > + .modifier = I915_FORMAT_MOD_4_TILED,
> > > > > + .display_ver = { 12, 13 },
> > > >
> > > > From display_ver 13.
> > > >
> > > > > + .tiling = I915_TILING_NONE,
> > > > > }, {
> > > > > .modifier = I915_FORMAT_MOD_Y_TILED,
> > > > > .display_ver = { 9, 13 },
> > > > > @@ -575,6 +579,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> > > > > return 128;
> > > > > else
> > > > > return 512;
> > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > + /*
> > > > > + * Each 4K tile consists of 64B(8*8) subtiles, with
> > > > > + * same shape as Y Tile(i.e 4*16B OWords)
> > > > > + */
> > > > > + return 128;
> > > > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > > > if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> > > > > return 128;
> > > > > @@ -743,6 +753,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> > > > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > > > case I915_FORMAT_MOD_Yf_TILED_CCS:
> > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > case I915_FORMAT_MOD_Yf_TILED:
> > > > > return 1 * 1024 * 1024;
> > > > > default:
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > index 1f66de77a6b1..f079a771f802 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > @@ -747,6 +747,7 @@ static bool tiling_is_valid(struct drm_i915_private *dev_priv,
> > > > > case DRM_FORMAT_MOD_LINEAR:
> > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > case I915_FORMAT_MOD_Yf_TILED:
> > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > return DISPLAY_VER(dev_priv) >= 9;
> > > > > case I915_FORMAT_MOD_X_TILED:
> > > > > return true;
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > > index dcd698a02da2..d80855ee9b96 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > > @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
> > > > > case DRM_FORMAT_MOD_LINEAR:
> > > > > case I915_FORMAT_MOD_X_TILED:
> > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > break;
> > > > > default:
> > > > > drm_dbg(&dev_priv->drm,
> > > > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > index 69fd56de83a7..aeca96925feb 100644
> > > > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> > > > > return PLANE_CTL_TILED_X;
> > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > return PLANE_CTL_TILED_Y;
> > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > + return PLANE_CTL_TILED_4;
> > > > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > > > return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> > > > > @@ -1930,9 +1932,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> > > > > case DRM_FORMAT_Y216:
> > > > > case DRM_FORMAT_XVYU12_16161616:
> > > > > case DRM_FORMAT_XVYU16161616:
> > > > > - if (modifier == DRM_FORMAT_MOD_LINEAR ||
> > > > > - modifier == I915_FORMAT_MOD_X_TILED ||
> > > > > - modifier == I915_FORMAT_MOD_Y_TILED)
> > > > > + if (!intel_fb_is_ccs_modifier(modifier))
> > > > > return true;
> > > > > fallthrough;
> > > > > default:
> > > > > @@ -2241,11 +2241,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> > > > > else
> > > > > fb->modifier = I915_FORMAT_MOD_Y_TILED;
> > > > > break;
> > > > > - case PLANE_CTL_TILED_YF:
> > > > > - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > > - else
> > > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > > > > + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
> > > > > + if (DISPLAY_VER(dev_priv) >= 13) {
> > > > > + fb->modifier = I915_FORMAT_MOD_4_TILED;
> > > > > + } else {
> > > > > + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > > + else
> > > > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > > > > + }
> > > > > break;
> > > > > default:
> > > > > MISSING_CASE(tiling);
> > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > > > index 19e6700a4315..0a32ce800677 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > > > @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > > > > #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
> > > > >
> > > > > #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
> > > > > +#define HAS_FTILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
> > > > > #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
> > > > > #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
> > > > > #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
> > > > > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > > > > index 169837de395d..8831b1885934 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > > > @@ -972,6 +972,7 @@ static const struct intel_device_info adl_p_info = {
> > > > > .display.has_cdclk_crawl = 1,
> > > > > .display.has_modular_fia = 1,
> > > > > .display.has_psr_hw_tracking = 0,
> > > > > + .has_4tile = 1, \
> > > >
> > > > If it's only on DG2 then it should be added there.
> > > >
> > > > > .platform_engine_mask =
> > > > > BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> > > > > .ppgtt_size = 48,
> > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > > > index 7c97bc352497..b70b72b032ef 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > > @@ -7195,6 +7195,7 @@ enum {
> > > > > #define PLANE_CTL_TILED_X (1 << 10)
> > > > > #define PLANE_CTL_TILED_Y (4 << 10)
> > > > > #define PLANE_CTL_TILED_YF (5 << 10)
> > > > > +#define PLANE_CTL_TILED_4 (5 << 10)
> > > > > #define PLANE_CTL_ASYNC_FLIP (1 << 9)
> > > > > #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> > > > > #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
> > > > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> > > > > index 8e6f48d1eb7b..6c543a152250 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > > > > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > > > > @@ -125,6 +125,7 @@ enum intel_ppgtt_type {
> > > > > func(has_64bit_reloc); \
> > > > > func(gpu_reset_clobbers_display); \
> > > > > func(has_reset_engine); \
> > > > > + func(has_4tile); \
> > > > > func(has_global_mocs); \
> > > > > func(has_gt_uc); \
> > > > > func(has_l3_dpf); \
> > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > index cffb3df35a63..1ac1af0a7f2d 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > @@ -5378,6 +5378,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> > > > > }
> > > > >
> > > > > wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
> > > > > + modifier == I915_FORMAT_MOD_4_TILED ||
> > > > > modifier == I915_FORMAT_MOD_Yf_TILED ||
> > > > > modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > > > > modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > > > > index 45a914850be0..982b0a9fa78b 100644
> > > > > --- a/include/uapi/drm/drm_fourcc.h
> > > > > +++ b/include/uapi/drm/drm_fourcc.h
> > > > > @@ -558,6 +558,14 @@ extern "C" {
> > > > > * pitch is required to be a multiple of 4 tile widths.
> > > > > */
> > > > > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> > > > > +/*
> > > > > + * Intel F-tiling(aka Tile4) layout
> > > > > + *
> > > > > + * This is a tiled layout using 4Kb tiles in row-major layout.
> > > > > + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
> > > > > + * (16 bytes) chunks column-major..
> > > > > + */
> > > > > +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 12)
> > > > >
> > > > > /*
> > > > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > > > > --
> > > > > 2.24.1.485.gad05a3d8e5
> > > > >
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
2021-10-28 7:39 ` Imre Deak
@ 2021-10-28 7:49 ` Lisovskiy, Stanislav
2021-10-28 7:53 ` Imre Deak
0 siblings, 1 reply; 28+ messages in thread
From: Lisovskiy, Stanislav @ 2021-10-28 7:49 UTC (permalink / raw)
To: Imre Deak
Cc: intel-gfx, jani.saarinen, matthew.d.roper, ramalingam.c, ville.syrjala
On Thu, Oct 28, 2021 at 10:39:42AM +0300, Imre Deak wrote:
> On Thu, Oct 28, 2021 at 09:58:52AM +0300, Lisovskiy, Stanislav wrote:
> > On Wed, Oct 27, 2021 at 07:56:25PM +0300, Imre Deak wrote:
> > > On Wed, Oct 27, 2021 at 06:46:53PM +0300, Stanislav Lisovskiy wrote:
> > > > TileF(Tile4 in bspec) format is 4K tile organized into
> > > > 64B subtiles with same basic shape as for legacy TileY
> > > > which will be supported by Display13.
> > >
> > > Is it supported on all D13 or only on DG2? Could you point to the bspec
> > > page describing this?
> >
> > Yes, it is supported on all D13 to my undertanding.
> > Check with BSpec 44917
>
> Thanks.
>
> Based on that page it's only supported on DG2 (and that's how the driver
> worked so far in the internal tree).
I think its supported on some other platforms as well - when you click the Tile 4
section, check platform names in the brackets.
Stan
>
> > Stan
> >
> > >
> > > >
> > > > v2: - Fixed wrong case condition(Jani Nikula)
> > > > - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
> > > >
> > > > v3: - s/I915_TILING_F/TILING_4/g
> > > > - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
> > > > - Removed unneeded fencing code
> > > >
> > > > v4: - Rebased, fixed merge conflict with new table-oriented
> > > > format modifier checking(Stan)
> > > > - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
> > > >
> > > > Cc: Imre Deak <imre.deak@intel.com>
> > > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > > Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_display.c | 1 +
> > > > drivers/gpu/drm/i915/display/intel_fb.c | 11 ++++++++++
> > > > drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> > > > .../drm/i915/display/intel_plane_initial.c | 1 +
> > > > .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
> > > > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > > > drivers/gpu/drm/i915/i915_pci.c | 1 +
> > > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > > drivers/gpu/drm/i915/intel_device_info.h | 1 +
> > > > drivers/gpu/drm/i915/intel_pm.c | 1 +
> > > > include/uapi/drm/drm_fourcc.h | 8 ++++++++
> > > > 11 files changed, 39 insertions(+), 8 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index 79cd158503b3..9b3913d73213 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -7755,6 +7755,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
> > > > case I915_FORMAT_MOD_X_TILED:
> > > > case I915_FORMAT_MOD_Y_TILED:
> > > > case I915_FORMAT_MOD_Yf_TILED:
> > > > + case I915_FORMAT_MOD_4_TILED:
> > > > break;
> > > > default:
> > > > drm_dbg_kms(&i915->drm,
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> > > > index 9ce1d273dc7e..d3dec51285f7 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > > > @@ -188,6 +188,10 @@ static const struct intel_modifier_desc intel_modifiers[] = {
> > > > .modifier = I915_FORMAT_MOD_Yf_TILED,
> > > > .display_ver = { 9, 11 },
> > > > .tiling = I915_TILING_NONE,
> > > > + }, {
> > > > + .modifier = I915_FORMAT_MOD_4_TILED,
> > > > + .display_ver = { 12, 13 },
> > >
> > > From display_ver 13.
> > >
> > > > + .tiling = I915_TILING_NONE,
> > > > }, {
> > > > .modifier = I915_FORMAT_MOD_Y_TILED,
> > > > .display_ver = { 9, 13 },
> > > > @@ -575,6 +579,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> > > > return 128;
> > > > else
> > > > return 512;
> > > > + case I915_FORMAT_MOD_4_TILED:
> > > > + /*
> > > > + * Each 4K tile consists of 64B(8*8) subtiles, with
> > > > + * same shape as Y Tile(i.e 4*16B OWords)
> > > > + */
> > > > + return 128;
> > > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > > if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> > > > return 128;
> > > > @@ -743,6 +753,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> > > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > > case I915_FORMAT_MOD_Yf_TILED_CCS:
> > > > case I915_FORMAT_MOD_Y_TILED:
> > > > + case I915_FORMAT_MOD_4_TILED:
> > > > case I915_FORMAT_MOD_Yf_TILED:
> > > > return 1 * 1024 * 1024;
> > > > default:
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > index 1f66de77a6b1..f079a771f802 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > @@ -747,6 +747,7 @@ static bool tiling_is_valid(struct drm_i915_private *dev_priv,
> > > > case DRM_FORMAT_MOD_LINEAR:
> > > > case I915_FORMAT_MOD_Y_TILED:
> > > > case I915_FORMAT_MOD_Yf_TILED:
> > > > + case I915_FORMAT_MOD_4_TILED:
> > > > return DISPLAY_VER(dev_priv) >= 9;
> > > > case I915_FORMAT_MOD_X_TILED:
> > > > return true;
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > index dcd698a02da2..d80855ee9b96 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
> > > > case DRM_FORMAT_MOD_LINEAR:
> > > > case I915_FORMAT_MOD_X_TILED:
> > > > case I915_FORMAT_MOD_Y_TILED:
> > > > + case I915_FORMAT_MOD_4_TILED:
> > > > break;
> > > > default:
> > > > drm_dbg(&dev_priv->drm,
> > > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > index 69fd56de83a7..aeca96925feb 100644
> > > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> > > > return PLANE_CTL_TILED_X;
> > > > case I915_FORMAT_MOD_Y_TILED:
> > > > return PLANE_CTL_TILED_Y;
> > > > + case I915_FORMAT_MOD_4_TILED:
> > > > + return PLANE_CTL_TILED_4;
> > > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > > return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> > > > @@ -1930,9 +1932,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> > > > case DRM_FORMAT_Y216:
> > > > case DRM_FORMAT_XVYU12_16161616:
> > > > case DRM_FORMAT_XVYU16161616:
> > > > - if (modifier == DRM_FORMAT_MOD_LINEAR ||
> > > > - modifier == I915_FORMAT_MOD_X_TILED ||
> > > > - modifier == I915_FORMAT_MOD_Y_TILED)
> > > > + if (!intel_fb_is_ccs_modifier(modifier))
> > > > return true;
> > > > fallthrough;
> > > > default:
> > > > @@ -2241,11 +2241,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> > > > else
> > > > fb->modifier = I915_FORMAT_MOD_Y_TILED;
> > > > break;
> > > > - case PLANE_CTL_TILED_YF:
> > > > - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > - else
> > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > > > + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
> > > > + if (DISPLAY_VER(dev_priv) >= 13) {
> > > > + fb->modifier = I915_FORMAT_MOD_4_TILED;
> > > > + } else {
> > > > + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > + else
> > > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > > > + }
> > > > break;
> > > > default:
> > > > MISSING_CASE(tiling);
> > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > > index 19e6700a4315..0a32ce800677 100644
> > > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > > @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > > > #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
> > > >
> > > > #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
> > > > +#define HAS_FTILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
> > > > #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
> > > > #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
> > > > #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
> > > > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > > > index 169837de395d..8831b1885934 100644
> > > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > > @@ -972,6 +972,7 @@ static const struct intel_device_info adl_p_info = {
> > > > .display.has_cdclk_crawl = 1,
> > > > .display.has_modular_fia = 1,
> > > > .display.has_psr_hw_tracking = 0,
> > > > + .has_4tile = 1, \
> > >
> > > If it's only on DG2 then it should be added there.
> > >
> > > > .platform_engine_mask =
> > > > BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> > > > .ppgtt_size = 48,
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > > index 7c97bc352497..b70b72b032ef 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -7195,6 +7195,7 @@ enum {
> > > > #define PLANE_CTL_TILED_X (1 << 10)
> > > > #define PLANE_CTL_TILED_Y (4 << 10)
> > > > #define PLANE_CTL_TILED_YF (5 << 10)
> > > > +#define PLANE_CTL_TILED_4 (5 << 10)
> > > > #define PLANE_CTL_ASYNC_FLIP (1 << 9)
> > > > #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> > > > #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
> > > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> > > > index 8e6f48d1eb7b..6c543a152250 100644
> > > > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > > > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > > > @@ -125,6 +125,7 @@ enum intel_ppgtt_type {
> > > > func(has_64bit_reloc); \
> > > > func(gpu_reset_clobbers_display); \
> > > > func(has_reset_engine); \
> > > > + func(has_4tile); \
> > > > func(has_global_mocs); \
> > > > func(has_gt_uc); \
> > > > func(has_l3_dpf); \
> > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > index cffb3df35a63..1ac1af0a7f2d 100644
> > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > @@ -5378,6 +5378,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> > > > }
> > > >
> > > > wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
> > > > + modifier == I915_FORMAT_MOD_4_TILED ||
> > > > modifier == I915_FORMAT_MOD_Yf_TILED ||
> > > > modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > > > modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > > > index 45a914850be0..982b0a9fa78b 100644
> > > > --- a/include/uapi/drm/drm_fourcc.h
> > > > +++ b/include/uapi/drm/drm_fourcc.h
> > > > @@ -558,6 +558,14 @@ extern "C" {
> > > > * pitch is required to be a multiple of 4 tile widths.
> > > > */
> > > > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> > > > +/*
> > > > + * Intel F-tiling(aka Tile4) layout
> > > > + *
> > > > + * This is a tiled layout using 4Kb tiles in row-major layout.
> > > > + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
> > > > + * (16 bytes) chunks column-major..
> > > > + */
> > > > +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 12)
> > > >
> > > > /*
> > > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > > > --
> > > > 2.24.1.485.gad05a3d8e5
> > > >
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
2021-10-28 6:58 ` Lisovskiy, Stanislav
@ 2021-10-28 7:39 ` Imre Deak
2021-10-28 7:49 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 28+ messages in thread
From: Imre Deak @ 2021-10-28 7:39 UTC (permalink / raw)
To: Lisovskiy, Stanislav
Cc: intel-gfx, jani.saarinen, matthew.d.roper, ramalingam.c, ville.syrjala
On Thu, Oct 28, 2021 at 09:58:52AM +0300, Lisovskiy, Stanislav wrote:
> On Wed, Oct 27, 2021 at 07:56:25PM +0300, Imre Deak wrote:
> > On Wed, Oct 27, 2021 at 06:46:53PM +0300, Stanislav Lisovskiy wrote:
> > > TileF(Tile4 in bspec) format is 4K tile organized into
> > > 64B subtiles with same basic shape as for legacy TileY
> > > which will be supported by Display13.
> >
> > Is it supported on all D13 or only on DG2? Could you point to the bspec
> > page describing this?
>
> Yes, it is supported on all D13 to my undertanding.
> Check with BSpec 44917
Thanks.
Based on that page it's only supported on DG2 (and that's how the driver
worked so far in the internal tree).
> Stan
>
> >
> > >
> > > v2: - Fixed wrong case condition(Jani Nikula)
> > > - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
> > >
> > > v3: - s/I915_TILING_F/TILING_4/g
> > > - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
> > > - Removed unneeded fencing code
> > >
> > > v4: - Rebased, fixed merge conflict with new table-oriented
> > > format modifier checking(Stan)
> > > - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
> > >
> > > Cc: Imre Deak <imre.deak@intel.com>
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 1 +
> > > drivers/gpu/drm/i915/display/intel_fb.c | 11 ++++++++++
> > > drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> > > .../drm/i915/display/intel_plane_initial.c | 1 +
> > > .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
> > > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > > drivers/gpu/drm/i915/i915_pci.c | 1 +
> > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > drivers/gpu/drm/i915/intel_device_info.h | 1 +
> > > drivers/gpu/drm/i915/intel_pm.c | 1 +
> > > include/uapi/drm/drm_fourcc.h | 8 ++++++++
> > > 11 files changed, 39 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 79cd158503b3..9b3913d73213 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -7755,6 +7755,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
> > > case I915_FORMAT_MOD_X_TILED:
> > > case I915_FORMAT_MOD_Y_TILED:
> > > case I915_FORMAT_MOD_Yf_TILED:
> > > + case I915_FORMAT_MOD_4_TILED:
> > > break;
> > > default:
> > > drm_dbg_kms(&i915->drm,
> > > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> > > index 9ce1d273dc7e..d3dec51285f7 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > > @@ -188,6 +188,10 @@ static const struct intel_modifier_desc intel_modifiers[] = {
> > > .modifier = I915_FORMAT_MOD_Yf_TILED,
> > > .display_ver = { 9, 11 },
> > > .tiling = I915_TILING_NONE,
> > > + }, {
> > > + .modifier = I915_FORMAT_MOD_4_TILED,
> > > + .display_ver = { 12, 13 },
> >
> > From display_ver 13.
> >
> > > + .tiling = I915_TILING_NONE,
> > > }, {
> > > .modifier = I915_FORMAT_MOD_Y_TILED,
> > > .display_ver = { 9, 13 },
> > > @@ -575,6 +579,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> > > return 128;
> > > else
> > > return 512;
> > > + case I915_FORMAT_MOD_4_TILED:
> > > + /*
> > > + * Each 4K tile consists of 64B(8*8) subtiles, with
> > > + * same shape as Y Tile(i.e 4*16B OWords)
> > > + */
> > > + return 128;
> > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> > > return 128;
> > > @@ -743,6 +753,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > case I915_FORMAT_MOD_Yf_TILED_CCS:
> > > case I915_FORMAT_MOD_Y_TILED:
> > > + case I915_FORMAT_MOD_4_TILED:
> > > case I915_FORMAT_MOD_Yf_TILED:
> > > return 1 * 1024 * 1024;
> > > default:
> > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > index 1f66de77a6b1..f079a771f802 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > @@ -747,6 +747,7 @@ static bool tiling_is_valid(struct drm_i915_private *dev_priv,
> > > case DRM_FORMAT_MOD_LINEAR:
> > > case I915_FORMAT_MOD_Y_TILED:
> > > case I915_FORMAT_MOD_Yf_TILED:
> > > + case I915_FORMAT_MOD_4_TILED:
> > > return DISPLAY_VER(dev_priv) >= 9;
> > > case I915_FORMAT_MOD_X_TILED:
> > > return true;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > index dcd698a02da2..d80855ee9b96 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
> > > case DRM_FORMAT_MOD_LINEAR:
> > > case I915_FORMAT_MOD_X_TILED:
> > > case I915_FORMAT_MOD_Y_TILED:
> > > + case I915_FORMAT_MOD_4_TILED:
> > > break;
> > > default:
> > > drm_dbg(&dev_priv->drm,
> > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > index 69fd56de83a7..aeca96925feb 100644
> > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> > > return PLANE_CTL_TILED_X;
> > > case I915_FORMAT_MOD_Y_TILED:
> > > return PLANE_CTL_TILED_Y;
> > > + case I915_FORMAT_MOD_4_TILED:
> > > + return PLANE_CTL_TILED_4;
> > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> > > @@ -1930,9 +1932,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> > > case DRM_FORMAT_Y216:
> > > case DRM_FORMAT_XVYU12_16161616:
> > > case DRM_FORMAT_XVYU16161616:
> > > - if (modifier == DRM_FORMAT_MOD_LINEAR ||
> > > - modifier == I915_FORMAT_MOD_X_TILED ||
> > > - modifier == I915_FORMAT_MOD_Y_TILED)
> > > + if (!intel_fb_is_ccs_modifier(modifier))
> > > return true;
> > > fallthrough;
> > > default:
> > > @@ -2241,11 +2241,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> > > else
> > > fb->modifier = I915_FORMAT_MOD_Y_TILED;
> > > break;
> > > - case PLANE_CTL_TILED_YF:
> > > - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > > - else
> > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > > + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
> > > + if (DISPLAY_VER(dev_priv) >= 13) {
> > > + fb->modifier = I915_FORMAT_MOD_4_TILED;
> > > + } else {
> > > + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > > + else
> > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > > + }
> > > break;
> > > default:
> > > MISSING_CASE(tiling);
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > index 19e6700a4315..0a32ce800677 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > > #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
> > >
> > > #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
> > > +#define HAS_FTILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
> > > #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
> > > #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
> > > #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
> > > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > > index 169837de395d..8831b1885934 100644
> > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > @@ -972,6 +972,7 @@ static const struct intel_device_info adl_p_info = {
> > > .display.has_cdclk_crawl = 1,
> > > .display.has_modular_fia = 1,
> > > .display.has_psr_hw_tracking = 0,
> > > + .has_4tile = 1, \
> >
> > If it's only on DG2 then it should be added there.
> >
> > > .platform_engine_mask =
> > > BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> > > .ppgtt_size = 48,
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 7c97bc352497..b70b72b032ef 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -7195,6 +7195,7 @@ enum {
> > > #define PLANE_CTL_TILED_X (1 << 10)
> > > #define PLANE_CTL_TILED_Y (4 << 10)
> > > #define PLANE_CTL_TILED_YF (5 << 10)
> > > +#define PLANE_CTL_TILED_4 (5 << 10)
> > > #define PLANE_CTL_ASYNC_FLIP (1 << 9)
> > > #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> > > #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
> > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> > > index 8e6f48d1eb7b..6c543a152250 100644
> > > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > > @@ -125,6 +125,7 @@ enum intel_ppgtt_type {
> > > func(has_64bit_reloc); \
> > > func(gpu_reset_clobbers_display); \
> > > func(has_reset_engine); \
> > > + func(has_4tile); \
> > > func(has_global_mocs); \
> > > func(has_gt_uc); \
> > > func(has_l3_dpf); \
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index cffb3df35a63..1ac1af0a7f2d 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -5378,6 +5378,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> > > }
> > >
> > > wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
> > > + modifier == I915_FORMAT_MOD_4_TILED ||
> > > modifier == I915_FORMAT_MOD_Yf_TILED ||
> > > modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > > modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > > index 45a914850be0..982b0a9fa78b 100644
> > > --- a/include/uapi/drm/drm_fourcc.h
> > > +++ b/include/uapi/drm/drm_fourcc.h
> > > @@ -558,6 +558,14 @@ extern "C" {
> > > * pitch is required to be a multiple of 4 tile widths.
> > > */
> > > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> > > +/*
> > > + * Intel F-tiling(aka Tile4) layout
> > > + *
> > > + * This is a tiled layout using 4Kb tiles in row-major layout.
> > > + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
> > > + * (16 bytes) chunks column-major..
> > > + */
> > > +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 12)
> > >
> > > /*
> > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > > --
> > > 2.24.1.485.gad05a3d8e5
> > >
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
2021-10-27 20:33 ` Ramalingam C
@ 2021-10-28 7:02 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 28+ messages in thread
From: Lisovskiy, Stanislav @ 2021-10-28 7:02 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx, jani.saarinen, matthew.d.roper, ville.syrjala
On Thu, Oct 28, 2021 at 02:03:49AM +0530, Ramalingam C wrote:
> On 2021-10-27 at 18:46:53 +0300, Stanislav Lisovskiy wrote:
> > TileF(Tile4 in bspec) format is 4K tile organized into
> > 64B subtiles with same basic shape as for legacy TileY
> > which will be supported by Display13.
> >
> > v2: - Fixed wrong case condition(Jani Nikula)
> > - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
> >
> > v3: - s/I915_TILING_F/TILING_4/g
> > - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
> > - Removed unneeded fencing code
> >
> > v4: - Rebased, fixed merge conflict with new table-oriented
> > format modifier checking(Stan)
> > - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
> >
> > Cc: Imre Deak <imre.deak@intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 1 +
> > drivers/gpu/drm/i915/display/intel_fb.c | 11 ++++++++++
> > drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> > .../drm/i915/display/intel_plane_initial.c | 1 +
> > .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/i915_pci.c | 1 +
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_device_info.h | 1 +
> > drivers/gpu/drm/i915/intel_pm.c | 1 +
> > include/uapi/drm/drm_fourcc.h | 8 ++++++++
> > 11 files changed, 39 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 79cd158503b3..9b3913d73213 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -7755,6 +7755,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
> > case I915_FORMAT_MOD_X_TILED:
> > case I915_FORMAT_MOD_Y_TILED:
> > case I915_FORMAT_MOD_Yf_TILED:
> > + case I915_FORMAT_MOD_4_TILED:
> > break;
> > default:
> > drm_dbg_kms(&i915->drm,
> > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> > index 9ce1d273dc7e..d3dec51285f7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > @@ -188,6 +188,10 @@ static const struct intel_modifier_desc intel_modifiers[] = {
> > .modifier = I915_FORMAT_MOD_Yf_TILED,
> > .display_ver = { 9, 11 },
> > .tiling = I915_TILING_NONE,
> > + }, {
> > + .modifier = I915_FORMAT_MOD_4_TILED,
> > + .display_ver = { 12, 13 },
> > + .tiling = I915_TILING_NONE,
> > }, {
> > .modifier = I915_FORMAT_MOD_Y_TILED,
> > .display_ver = { 9, 13 },
> > @@ -575,6 +579,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> > return 128;
> > else
> > return 512;
> > + case I915_FORMAT_MOD_4_TILED:
> > + /*
> > + * Each 4K tile consists of 64B(8*8) subtiles, with
> > + * same shape as Y Tile(i.e 4*16B OWords)
> > + */
> > + return 128;
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> > return 128;
> > @@ -743,6 +753,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > case I915_FORMAT_MOD_Yf_TILED_CCS:
> > case I915_FORMAT_MOD_Y_TILED:
> > + case I915_FORMAT_MOD_4_TILED:
> > case I915_FORMAT_MOD_Yf_TILED:
> > return 1 * 1024 * 1024;
> > default:
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index 1f66de77a6b1..f079a771f802 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -747,6 +747,7 @@ static bool tiling_is_valid(struct drm_i915_private *dev_priv,
> > case DRM_FORMAT_MOD_LINEAR:
> > case I915_FORMAT_MOD_Y_TILED:
> > case I915_FORMAT_MOD_Yf_TILED:
> > + case I915_FORMAT_MOD_4_TILED:
> > return DISPLAY_VER(dev_priv) >= 9;
> > case I915_FORMAT_MOD_X_TILED:
> > return true;
> > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > index dcd698a02da2..d80855ee9b96 100644
> > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
> > case DRM_FORMAT_MOD_LINEAR:
> > case I915_FORMAT_MOD_X_TILED:
> > case I915_FORMAT_MOD_Y_TILED:
> > + case I915_FORMAT_MOD_4_TILED:
> > break;
> > default:
> > drm_dbg(&dev_priv->drm,
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 69fd56de83a7..aeca96925feb 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> > return PLANE_CTL_TILED_X;
> > case I915_FORMAT_MOD_Y_TILED:
> > return PLANE_CTL_TILED_Y;
> > + case I915_FORMAT_MOD_4_TILED:
> > + return PLANE_CTL_TILED_4;
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> > @@ -1930,9 +1932,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> > case DRM_FORMAT_Y216:
> > case DRM_FORMAT_XVYU12_16161616:
> > case DRM_FORMAT_XVYU16161616:
> > - if (modifier == DRM_FORMAT_MOD_LINEAR ||
> > - modifier == I915_FORMAT_MOD_X_TILED ||
> > - modifier == I915_FORMAT_MOD_Y_TILED)
> > + if (!intel_fb_is_ccs_modifier(modifier))
> > return true;
> > fallthrough;
> > default:
> > @@ -2241,11 +2241,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> > else
> > fb->modifier = I915_FORMAT_MOD_Y_TILED;
> > break;
> > - case PLANE_CTL_TILED_YF:
> > - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > - else
> > - fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
> > + if (DISPLAY_VER(dev_priv) >= 13) {
> > + fb->modifier = I915_FORMAT_MOD_4_TILED;
> > + } else {
> > + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > + else
> > + fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > + }
> > break;
> > default:
> > MISSING_CASE(tiling);
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 19e6700a4315..0a32ce800677 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
> >
> > #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
> > +#define HAS_FTILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
> > #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
> > #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
> > #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > index 169837de395d..8831b1885934 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -972,6 +972,7 @@ static const struct intel_device_info adl_p_info = {
> > .display.has_cdclk_crawl = 1,
> > .display.has_modular_fia = 1,
> > .display.has_psr_hw_tracking = 0,
> > + .has_4tile = 1, \
> This is applied in wrong place. fixed as part of the series i am preparing.
>
> Ram
I think the structure is still adl_p_info in your patch, do you mean it should be inserted
in other place?
Stan
> > .platform_engine_mask =
> > BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> > .ppgtt_size = 48,
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 7c97bc352497..b70b72b032ef 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7195,6 +7195,7 @@ enum {
> > #define PLANE_CTL_TILED_X (1 << 10)
> > #define PLANE_CTL_TILED_Y (4 << 10)
> > #define PLANE_CTL_TILED_YF (5 << 10)
> > +#define PLANE_CTL_TILED_4 (5 << 10)
> > #define PLANE_CTL_ASYNC_FLIP (1 << 9)
> > #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> > #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> > index 8e6f48d1eb7b..6c543a152250 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -125,6 +125,7 @@ enum intel_ppgtt_type {
> > func(has_64bit_reloc); \
> > func(gpu_reset_clobbers_display); \
> > func(has_reset_engine); \
> > + func(has_4tile); \
> > func(has_global_mocs); \
> > func(has_gt_uc); \
> > func(has_l3_dpf); \
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index cffb3df35a63..1ac1af0a7f2d 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -5378,6 +5378,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> > }
> >
> > wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
> > + modifier == I915_FORMAT_MOD_4_TILED ||
> > modifier == I915_FORMAT_MOD_Yf_TILED ||
> > modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > index 45a914850be0..982b0a9fa78b 100644
> > --- a/include/uapi/drm/drm_fourcc.h
> > +++ b/include/uapi/drm/drm_fourcc.h
> > @@ -558,6 +558,14 @@ extern "C" {
> > * pitch is required to be a multiple of 4 tile widths.
> > */
> > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> > +/*
> > + * Intel F-tiling(aka Tile4) layout
> > + *
> > + * This is a tiled layout using 4Kb tiles in row-major layout.
> > + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
> > + * (16 bytes) chunks column-major..
> > + */
> > +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 12)
> >
> > /*
> > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > --
> > 2.24.1.485.gad05a3d8e5
> >
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
2021-10-27 16:56 ` Imre Deak
@ 2021-10-28 6:58 ` Lisovskiy, Stanislav
2021-10-28 7:39 ` Imre Deak
0 siblings, 1 reply; 28+ messages in thread
From: Lisovskiy, Stanislav @ 2021-10-28 6:58 UTC (permalink / raw)
To: Imre Deak
Cc: intel-gfx, jani.saarinen, matthew.d.roper, ramalingam.c, ville.syrjala
On Wed, Oct 27, 2021 at 07:56:25PM +0300, Imre Deak wrote:
> On Wed, Oct 27, 2021 at 06:46:53PM +0300, Stanislav Lisovskiy wrote:
> > TileF(Tile4 in bspec) format is 4K tile organized into
> > 64B subtiles with same basic shape as for legacy TileY
> > which will be supported by Display13.
>
> Is it supported on all D13 or only on DG2? Could you point to the bspec
> page describing this?
Yes, it is supported on all D13 to my undertanding.
Check with BSpec 44917
Stan
>
> >
> > v2: - Fixed wrong case condition(Jani Nikula)
> > - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
> >
> > v3: - s/I915_TILING_F/TILING_4/g
> > - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
> > - Removed unneeded fencing code
> >
> > v4: - Rebased, fixed merge conflict with new table-oriented
> > format modifier checking(Stan)
> > - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
> >
> > Cc: Imre Deak <imre.deak@intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 1 +
> > drivers/gpu/drm/i915/display/intel_fb.c | 11 ++++++++++
> > drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> > .../drm/i915/display/intel_plane_initial.c | 1 +
> > .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/i915_pci.c | 1 +
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_device_info.h | 1 +
> > drivers/gpu/drm/i915/intel_pm.c | 1 +
> > include/uapi/drm/drm_fourcc.h | 8 ++++++++
> > 11 files changed, 39 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 79cd158503b3..9b3913d73213 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -7755,6 +7755,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
> > case I915_FORMAT_MOD_X_TILED:
> > case I915_FORMAT_MOD_Y_TILED:
> > case I915_FORMAT_MOD_Yf_TILED:
> > + case I915_FORMAT_MOD_4_TILED:
> > break;
> > default:
> > drm_dbg_kms(&i915->drm,
> > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> > index 9ce1d273dc7e..d3dec51285f7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > @@ -188,6 +188,10 @@ static const struct intel_modifier_desc intel_modifiers[] = {
> > .modifier = I915_FORMAT_MOD_Yf_TILED,
> > .display_ver = { 9, 11 },
> > .tiling = I915_TILING_NONE,
> > + }, {
> > + .modifier = I915_FORMAT_MOD_4_TILED,
> > + .display_ver = { 12, 13 },
>
> From display_ver 13.
>
> > + .tiling = I915_TILING_NONE,
> > }, {
> > .modifier = I915_FORMAT_MOD_Y_TILED,
> > .display_ver = { 9, 13 },
> > @@ -575,6 +579,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> > return 128;
> > else
> > return 512;
> > + case I915_FORMAT_MOD_4_TILED:
> > + /*
> > + * Each 4K tile consists of 64B(8*8) subtiles, with
> > + * same shape as Y Tile(i.e 4*16B OWords)
> > + */
> > + return 128;
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> > return 128;
> > @@ -743,6 +753,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > case I915_FORMAT_MOD_Yf_TILED_CCS:
> > case I915_FORMAT_MOD_Y_TILED:
> > + case I915_FORMAT_MOD_4_TILED:
> > case I915_FORMAT_MOD_Yf_TILED:
> > return 1 * 1024 * 1024;
> > default:
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index 1f66de77a6b1..f079a771f802 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -747,6 +747,7 @@ static bool tiling_is_valid(struct drm_i915_private *dev_priv,
> > case DRM_FORMAT_MOD_LINEAR:
> > case I915_FORMAT_MOD_Y_TILED:
> > case I915_FORMAT_MOD_Yf_TILED:
> > + case I915_FORMAT_MOD_4_TILED:
> > return DISPLAY_VER(dev_priv) >= 9;
> > case I915_FORMAT_MOD_X_TILED:
> > return true;
> > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > index dcd698a02da2..d80855ee9b96 100644
> > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
> > case DRM_FORMAT_MOD_LINEAR:
> > case I915_FORMAT_MOD_X_TILED:
> > case I915_FORMAT_MOD_Y_TILED:
> > + case I915_FORMAT_MOD_4_TILED:
> > break;
> > default:
> > drm_dbg(&dev_priv->drm,
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 69fd56de83a7..aeca96925feb 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> > return PLANE_CTL_TILED_X;
> > case I915_FORMAT_MOD_Y_TILED:
> > return PLANE_CTL_TILED_Y;
> > + case I915_FORMAT_MOD_4_TILED:
> > + return PLANE_CTL_TILED_4;
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> > @@ -1930,9 +1932,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> > case DRM_FORMAT_Y216:
> > case DRM_FORMAT_XVYU12_16161616:
> > case DRM_FORMAT_XVYU16161616:
> > - if (modifier == DRM_FORMAT_MOD_LINEAR ||
> > - modifier == I915_FORMAT_MOD_X_TILED ||
> > - modifier == I915_FORMAT_MOD_Y_TILED)
> > + if (!intel_fb_is_ccs_modifier(modifier))
> > return true;
> > fallthrough;
> > default:
> > @@ -2241,11 +2241,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> > else
> > fb->modifier = I915_FORMAT_MOD_Y_TILED;
> > break;
> > - case PLANE_CTL_TILED_YF:
> > - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > - else
> > - fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
> > + if (DISPLAY_VER(dev_priv) >= 13) {
> > + fb->modifier = I915_FORMAT_MOD_4_TILED;
> > + } else {
> > + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > + else
> > + fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > + }
> > break;
> > default:
> > MISSING_CASE(tiling);
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 19e6700a4315..0a32ce800677 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
> >
> > #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
> > +#define HAS_FTILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
> > #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
> > #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
> > #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > index 169837de395d..8831b1885934 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -972,6 +972,7 @@ static const struct intel_device_info adl_p_info = {
> > .display.has_cdclk_crawl = 1,
> > .display.has_modular_fia = 1,
> > .display.has_psr_hw_tracking = 0,
> > + .has_4tile = 1, \
>
> If it's only on DG2 then it should be added there.
>
> > .platform_engine_mask =
> > BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> > .ppgtt_size = 48,
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 7c97bc352497..b70b72b032ef 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7195,6 +7195,7 @@ enum {
> > #define PLANE_CTL_TILED_X (1 << 10)
> > #define PLANE_CTL_TILED_Y (4 << 10)
> > #define PLANE_CTL_TILED_YF (5 << 10)
> > +#define PLANE_CTL_TILED_4 (5 << 10)
> > #define PLANE_CTL_ASYNC_FLIP (1 << 9)
> > #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> > #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> > index 8e6f48d1eb7b..6c543a152250 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -125,6 +125,7 @@ enum intel_ppgtt_type {
> > func(has_64bit_reloc); \
> > func(gpu_reset_clobbers_display); \
> > func(has_reset_engine); \
> > + func(has_4tile); \
> > func(has_global_mocs); \
> > func(has_gt_uc); \
> > func(has_l3_dpf); \
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index cffb3df35a63..1ac1af0a7f2d 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -5378,6 +5378,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> > }
> >
> > wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
> > + modifier == I915_FORMAT_MOD_4_TILED ||
> > modifier == I915_FORMAT_MOD_Yf_TILED ||
> > modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > index 45a914850be0..982b0a9fa78b 100644
> > --- a/include/uapi/drm/drm_fourcc.h
> > +++ b/include/uapi/drm/drm_fourcc.h
> > @@ -558,6 +558,14 @@ extern "C" {
> > * pitch is required to be a multiple of 4 tile widths.
> > */
> > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> > +/*
> > + * Intel F-tiling(aka Tile4) layout
> > + *
> > + * This is a tiled layout using 4Kb tiles in row-major layout.
> > + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
> > + * (16 bytes) chunks column-major..
> > + */
> > +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 12)
> >
> > /*
> > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > --
> > 2.24.1.485.gad05a3d8e5
> >
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
2021-10-27 15:46 Stanislav Lisovskiy
2021-10-27 16:56 ` Imre Deak
@ 2021-10-27 20:33 ` Ramalingam C
2021-10-28 7:02 ` Lisovskiy, Stanislav
1 sibling, 1 reply; 28+ messages in thread
From: Ramalingam C @ 2021-10-27 20:33 UTC (permalink / raw)
To: Stanislav Lisovskiy
Cc: intel-gfx, jani.saarinen, matthew.d.roper, ville.syrjala
On 2021-10-27 at 18:46:53 +0300, Stanislav Lisovskiy wrote:
> TileF(Tile4 in bspec) format is 4K tile organized into
> 64B subtiles with same basic shape as for legacy TileY
> which will be supported by Display13.
>
> v2: - Fixed wrong case condition(Jani Nikula)
> - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
>
> v3: - s/I915_TILING_F/TILING_4/g
> - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
> - Removed unneeded fencing code
>
> v4: - Rebased, fixed merge conflict with new table-oriented
> format modifier checking(Stan)
> - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 1 +
> drivers/gpu/drm/i915/display/intel_fb.c | 11 ++++++++++
> drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> .../drm/i915/display/intel_plane_initial.c | 1 +
> .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 1 +
> include/uapi/drm/drm_fourcc.h | 8 ++++++++
> 11 files changed, 39 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 79cd158503b3..9b3913d73213 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7755,6 +7755,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
> case I915_FORMAT_MOD_X_TILED:
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Yf_TILED:
> + case I915_FORMAT_MOD_4_TILED:
> break;
> default:
> drm_dbg_kms(&i915->drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> index 9ce1d273dc7e..d3dec51285f7 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -188,6 +188,10 @@ static const struct intel_modifier_desc intel_modifiers[] = {
> .modifier = I915_FORMAT_MOD_Yf_TILED,
> .display_ver = { 9, 11 },
> .tiling = I915_TILING_NONE,
> + }, {
> + .modifier = I915_FORMAT_MOD_4_TILED,
> + .display_ver = { 12, 13 },
> + .tiling = I915_TILING_NONE,
> }, {
> .modifier = I915_FORMAT_MOD_Y_TILED,
> .display_ver = { 9, 13 },
> @@ -575,6 +579,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> return 128;
> else
> return 512;
> + case I915_FORMAT_MOD_4_TILED:
> + /*
> + * Each 4K tile consists of 64B(8*8) subtiles, with
> + * same shape as Y Tile(i.e 4*16B OWords)
> + */
> + return 128;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> return 128;
> @@ -743,6 +753,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Yf_TILED_CCS:
> case I915_FORMAT_MOD_Y_TILED:
> + case I915_FORMAT_MOD_4_TILED:
> case I915_FORMAT_MOD_Yf_TILED:
> return 1 * 1024 * 1024;
> default:
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 1f66de77a6b1..f079a771f802 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -747,6 +747,7 @@ static bool tiling_is_valid(struct drm_i915_private *dev_priv,
> case DRM_FORMAT_MOD_LINEAR:
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Yf_TILED:
> + case I915_FORMAT_MOD_4_TILED:
> return DISPLAY_VER(dev_priv) >= 9;
> case I915_FORMAT_MOD_X_TILED:
> return true;
> diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> index dcd698a02da2..d80855ee9b96 100644
> --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
> case DRM_FORMAT_MOD_LINEAR:
> case I915_FORMAT_MOD_X_TILED:
> case I915_FORMAT_MOD_Y_TILED:
> + case I915_FORMAT_MOD_4_TILED:
> break;
> default:
> drm_dbg(&dev_priv->drm,
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 69fd56de83a7..aeca96925feb 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> return PLANE_CTL_TILED_X;
> case I915_FORMAT_MOD_Y_TILED:
> return PLANE_CTL_TILED_Y;
> + case I915_FORMAT_MOD_4_TILED:
> + return PLANE_CTL_TILED_4;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> @@ -1930,9 +1932,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> case DRM_FORMAT_Y216:
> case DRM_FORMAT_XVYU12_16161616:
> case DRM_FORMAT_XVYU16161616:
> - if (modifier == DRM_FORMAT_MOD_LINEAR ||
> - modifier == I915_FORMAT_MOD_X_TILED ||
> - modifier == I915_FORMAT_MOD_Y_TILED)
> + if (!intel_fb_is_ccs_modifier(modifier))
> return true;
> fallthrough;
> default:
> @@ -2241,11 +2241,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> else
> fb->modifier = I915_FORMAT_MOD_Y_TILED;
> break;
> - case PLANE_CTL_TILED_YF:
> - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> - else
> - fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
> + if (DISPLAY_VER(dev_priv) >= 13) {
> + fb->modifier = I915_FORMAT_MOD_4_TILED;
> + } else {
> + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> + else
> + fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> + }
> break;
> default:
> MISSING_CASE(tiling);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 19e6700a4315..0a32ce800677 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
>
> #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
> +#define HAS_FTILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
> #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
> #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
> #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 169837de395d..8831b1885934 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -972,6 +972,7 @@ static const struct intel_device_info adl_p_info = {
> .display.has_cdclk_crawl = 1,
> .display.has_modular_fia = 1,
> .display.has_psr_hw_tracking = 0,
> + .has_4tile = 1, \
This is applied in wrong place. fixed as part of the series i am preparing.
Ram
> .platform_engine_mask =
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> .ppgtt_size = 48,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7c97bc352497..b70b72b032ef 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7195,6 +7195,7 @@ enum {
> #define PLANE_CTL_TILED_X (1 << 10)
> #define PLANE_CTL_TILED_Y (4 << 10)
> #define PLANE_CTL_TILED_YF (5 << 10)
> +#define PLANE_CTL_TILED_4 (5 << 10)
> #define PLANE_CTL_ASYNC_FLIP (1 << 9)
> #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 8e6f48d1eb7b..6c543a152250 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -125,6 +125,7 @@ enum intel_ppgtt_type {
> func(has_64bit_reloc); \
> func(gpu_reset_clobbers_display); \
> func(has_reset_engine); \
> + func(has_4tile); \
> func(has_global_mocs); \
> func(has_gt_uc); \
> func(has_l3_dpf); \
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index cffb3df35a63..1ac1af0a7f2d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5378,6 +5378,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> }
>
> wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
> + modifier == I915_FORMAT_MOD_4_TILED ||
> modifier == I915_FORMAT_MOD_Yf_TILED ||
> modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 45a914850be0..982b0a9fa78b 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -558,6 +558,14 @@ extern "C" {
> * pitch is required to be a multiple of 4 tile widths.
> */
> #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> +/*
> + * Intel F-tiling(aka Tile4) layout
> + *
> + * This is a tiled layout using 4Kb tiles in row-major layout.
> + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
> + * (16 bytes) chunks column-major..
> + */
> +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 12)
>
> /*
> * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> --
> 2.24.1.485.gad05a3d8e5
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
2021-10-27 15:46 Stanislav Lisovskiy
@ 2021-10-27 16:56 ` Imre Deak
2021-10-28 6:58 ` Lisovskiy, Stanislav
2021-10-27 20:33 ` Ramalingam C
1 sibling, 1 reply; 28+ messages in thread
From: Imre Deak @ 2021-10-27 16:56 UTC (permalink / raw)
To: Stanislav Lisovskiy
Cc: intel-gfx, jani.saarinen, matthew.d.roper, ramalingam.c, ville.syrjala
On Wed, Oct 27, 2021 at 06:46:53PM +0300, Stanislav Lisovskiy wrote:
> TileF(Tile4 in bspec) format is 4K tile organized into
> 64B subtiles with same basic shape as for legacy TileY
> which will be supported by Display13.
Is it supported on all D13 or only on DG2? Could you point to the bspec
page describing this?
>
> v2: - Fixed wrong case condition(Jani Nikula)
> - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
>
> v3: - s/I915_TILING_F/TILING_4/g
> - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
> - Removed unneeded fencing code
>
> v4: - Rebased, fixed merge conflict with new table-oriented
> format modifier checking(Stan)
> - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 1 +
> drivers/gpu/drm/i915/display/intel_fb.c | 11 ++++++++++
> drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> .../drm/i915/display/intel_plane_initial.c | 1 +
> .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 1 +
> include/uapi/drm/drm_fourcc.h | 8 ++++++++
> 11 files changed, 39 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 79cd158503b3..9b3913d73213 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7755,6 +7755,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
> case I915_FORMAT_MOD_X_TILED:
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Yf_TILED:
> + case I915_FORMAT_MOD_4_TILED:
> break;
> default:
> drm_dbg_kms(&i915->drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> index 9ce1d273dc7e..d3dec51285f7 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -188,6 +188,10 @@ static const struct intel_modifier_desc intel_modifiers[] = {
> .modifier = I915_FORMAT_MOD_Yf_TILED,
> .display_ver = { 9, 11 },
> .tiling = I915_TILING_NONE,
> + }, {
> + .modifier = I915_FORMAT_MOD_4_TILED,
> + .display_ver = { 12, 13 },
From display_ver 13.
> + .tiling = I915_TILING_NONE,
> }, {
> .modifier = I915_FORMAT_MOD_Y_TILED,
> .display_ver = { 9, 13 },
> @@ -575,6 +579,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> return 128;
> else
> return 512;
> + case I915_FORMAT_MOD_4_TILED:
> + /*
> + * Each 4K tile consists of 64B(8*8) subtiles, with
> + * same shape as Y Tile(i.e 4*16B OWords)
> + */
> + return 128;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> return 128;
> @@ -743,6 +753,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Yf_TILED_CCS:
> case I915_FORMAT_MOD_Y_TILED:
> + case I915_FORMAT_MOD_4_TILED:
> case I915_FORMAT_MOD_Yf_TILED:
> return 1 * 1024 * 1024;
> default:
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 1f66de77a6b1..f079a771f802 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -747,6 +747,7 @@ static bool tiling_is_valid(struct drm_i915_private *dev_priv,
> case DRM_FORMAT_MOD_LINEAR:
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Yf_TILED:
> + case I915_FORMAT_MOD_4_TILED:
> return DISPLAY_VER(dev_priv) >= 9;
> case I915_FORMAT_MOD_X_TILED:
> return true;
> diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> index dcd698a02da2..d80855ee9b96 100644
> --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
> case DRM_FORMAT_MOD_LINEAR:
> case I915_FORMAT_MOD_X_TILED:
> case I915_FORMAT_MOD_Y_TILED:
> + case I915_FORMAT_MOD_4_TILED:
> break;
> default:
> drm_dbg(&dev_priv->drm,
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 69fd56de83a7..aeca96925feb 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> return PLANE_CTL_TILED_X;
> case I915_FORMAT_MOD_Y_TILED:
> return PLANE_CTL_TILED_Y;
> + case I915_FORMAT_MOD_4_TILED:
> + return PLANE_CTL_TILED_4;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> @@ -1930,9 +1932,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> case DRM_FORMAT_Y216:
> case DRM_FORMAT_XVYU12_16161616:
> case DRM_FORMAT_XVYU16161616:
> - if (modifier == DRM_FORMAT_MOD_LINEAR ||
> - modifier == I915_FORMAT_MOD_X_TILED ||
> - modifier == I915_FORMAT_MOD_Y_TILED)
> + if (!intel_fb_is_ccs_modifier(modifier))
> return true;
> fallthrough;
> default:
> @@ -2241,11 +2241,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> else
> fb->modifier = I915_FORMAT_MOD_Y_TILED;
> break;
> - case PLANE_CTL_TILED_YF:
> - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> - else
> - fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
> + if (DISPLAY_VER(dev_priv) >= 13) {
> + fb->modifier = I915_FORMAT_MOD_4_TILED;
> + } else {
> + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> + else
> + fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> + }
> break;
> default:
> MISSING_CASE(tiling);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 19e6700a4315..0a32ce800677 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
>
> #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
> +#define HAS_FTILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
> #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
> #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
> #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 169837de395d..8831b1885934 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -972,6 +972,7 @@ static const struct intel_device_info adl_p_info = {
> .display.has_cdclk_crawl = 1,
> .display.has_modular_fia = 1,
> .display.has_psr_hw_tracking = 0,
> + .has_4tile = 1, \
If it's only on DG2 then it should be added there.
> .platform_engine_mask =
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> .ppgtt_size = 48,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7c97bc352497..b70b72b032ef 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7195,6 +7195,7 @@ enum {
> #define PLANE_CTL_TILED_X (1 << 10)
> #define PLANE_CTL_TILED_Y (4 << 10)
> #define PLANE_CTL_TILED_YF (5 << 10)
> +#define PLANE_CTL_TILED_4 (5 << 10)
> #define PLANE_CTL_ASYNC_FLIP (1 << 9)
> #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 8e6f48d1eb7b..6c543a152250 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -125,6 +125,7 @@ enum intel_ppgtt_type {
> func(has_64bit_reloc); \
> func(gpu_reset_clobbers_display); \
> func(has_reset_engine); \
> + func(has_4tile); \
> func(has_global_mocs); \
> func(has_gt_uc); \
> func(has_l3_dpf); \
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index cffb3df35a63..1ac1af0a7f2d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5378,6 +5378,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> }
>
> wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
> + modifier == I915_FORMAT_MOD_4_TILED ||
> modifier == I915_FORMAT_MOD_Yf_TILED ||
> modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 45a914850be0..982b0a9fa78b 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -558,6 +558,14 @@ extern "C" {
> * pitch is required to be a multiple of 4 tile widths.
> */
> #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> +/*
> + * Intel F-tiling(aka Tile4) layout
> + *
> + * This is a tiled layout using 4Kb tiles in row-major layout.
> + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
> + * (16 bytes) chunks column-major..
> + */
> +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 12)
>
> /*
> * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> --
> 2.24.1.485.gad05a3d8e5
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
@ 2021-10-27 15:46 Stanislav Lisovskiy
2021-10-27 16:56 ` Imre Deak
2021-10-27 20:33 ` Ramalingam C
0 siblings, 2 replies; 28+ messages in thread
From: Stanislav Lisovskiy @ 2021-10-27 15:46 UTC (permalink / raw)
To: intel-gfx
Cc: Stanislav.Lisovskiy, jani.saarinen, matthew.d.roper,
ramalingam.c, ville.syrjala
TileF(Tile4 in bspec) format is 4K tile organized into
64B subtiles with same basic shape as for legacy TileY
which will be supported by Display13.
v2: - Fixed wrong case condition(Jani Nikula)
- Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
v3: - s/I915_TILING_F/TILING_4/g
- s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
- Removed unneeded fencing code
v4: - Rebased, fixed merge conflict with new table-oriented
format modifier checking(Stan)
- Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_fb.c | 11 ++++++++++
drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
.../drm/i915/display/intel_plane_initial.c | 1 +
.../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 1 +
include/uapi/drm/drm_fourcc.h | 8 ++++++++
11 files changed, 39 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 79cd158503b3..9b3913d73213 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7755,6 +7755,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
+ case I915_FORMAT_MOD_4_TILED:
break;
default:
drm_dbg_kms(&i915->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index 9ce1d273dc7e..d3dec51285f7 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -188,6 +188,10 @@ static const struct intel_modifier_desc intel_modifiers[] = {
.modifier = I915_FORMAT_MOD_Yf_TILED,
.display_ver = { 9, 11 },
.tiling = I915_TILING_NONE,
+ }, {
+ .modifier = I915_FORMAT_MOD_4_TILED,
+ .display_ver = { 12, 13 },
+ .tiling = I915_TILING_NONE,
}, {
.modifier = I915_FORMAT_MOD_Y_TILED,
.display_ver = { 9, 13 },
@@ -575,6 +579,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
return 128;
else
return 512;
+ case I915_FORMAT_MOD_4_TILED:
+ /*
+ * Each 4K tile consists of 64B(8*8) subtiles, with
+ * same shape as Y Tile(i.e 4*16B OWords)
+ */
+ return 128;
case I915_FORMAT_MOD_Y_TILED_CCS:
if (intel_fb_is_ccs_aux_plane(fb, color_plane))
return 128;
@@ -743,6 +753,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED:
+ case I915_FORMAT_MOD_4_TILED:
case I915_FORMAT_MOD_Yf_TILED:
return 1 * 1024 * 1024;
default:
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 1f66de77a6b1..f079a771f802 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -747,6 +747,7 @@ static bool tiling_is_valid(struct drm_i915_private *dev_priv,
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
+ case I915_FORMAT_MOD_4_TILED:
return DISPLAY_VER(dev_priv) >= 9;
case I915_FORMAT_MOD_X_TILED:
return true;
diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index dcd698a02da2..d80855ee9b96 100644
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
+ case I915_FORMAT_MOD_4_TILED:
break;
default:
drm_dbg(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 69fd56de83a7..aeca96925feb 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
return PLANE_CTL_TILED_X;
case I915_FORMAT_MOD_Y_TILED:
return PLANE_CTL_TILED_Y;
+ case I915_FORMAT_MOD_4_TILED:
+ return PLANE_CTL_TILED_4;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
@@ -1930,9 +1932,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_Y216:
case DRM_FORMAT_XVYU12_16161616:
case DRM_FORMAT_XVYU16161616:
- if (modifier == DRM_FORMAT_MOD_LINEAR ||
- modifier == I915_FORMAT_MOD_X_TILED ||
- modifier == I915_FORMAT_MOD_Y_TILED)
+ if (!intel_fb_is_ccs_modifier(modifier))
return true;
fallthrough;
default:
@@ -2241,11 +2241,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
else
fb->modifier = I915_FORMAT_MOD_Y_TILED;
break;
- case PLANE_CTL_TILED_YF:
- if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
- fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
- else
- fb->modifier = I915_FORMAT_MOD_Yf_TILED;
+ case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
+ if (DISPLAY_VER(dev_priv) >= 13) {
+ fb->modifier = I915_FORMAT_MOD_4_TILED;
+ } else {
+ if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
+ fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
+ else
+ fb->modifier = I915_FORMAT_MOD_Yf_TILED;
+ }
break;
default:
MISSING_CASE(tiling);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 19e6700a4315..0a32ce800677 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
#define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
+#define HAS_FTILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
#define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
#define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
#define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 169837de395d..8831b1885934 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -972,6 +972,7 @@ static const struct intel_device_info adl_p_info = {
.display.has_cdclk_crawl = 1,
.display.has_modular_fia = 1,
.display.has_psr_hw_tracking = 0,
+ .has_4tile = 1, \
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
.ppgtt_size = 48,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7c97bc352497..b70b72b032ef 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7195,6 +7195,7 @@ enum {
#define PLANE_CTL_TILED_X (1 << 10)
#define PLANE_CTL_TILED_Y (4 << 10)
#define PLANE_CTL_TILED_YF (5 << 10)
+#define PLANE_CTL_TILED_4 (5 << 10)
#define PLANE_CTL_ASYNC_FLIP (1 << 9)
#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 8e6f48d1eb7b..6c543a152250 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -125,6 +125,7 @@ enum intel_ppgtt_type {
func(has_64bit_reloc); \
func(gpu_reset_clobbers_display); \
func(has_reset_engine); \
+ func(has_4tile); \
func(has_global_mocs); \
func(has_gt_uc); \
func(has_l3_dpf); \
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cffb3df35a63..1ac1af0a7f2d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5378,6 +5378,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
}
wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
+ modifier == I915_FORMAT_MOD_4_TILED ||
modifier == I915_FORMAT_MOD_Yf_TILED ||
modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 45a914850be0..982b0a9fa78b 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -558,6 +558,14 @@ extern "C" {
* pitch is required to be a multiple of 4 tile widths.
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
+/*
+ * Intel F-tiling(aka Tile4) layout
+ *
+ * This is a tiled layout using 4Kb tiles in row-major layout.
+ * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
+ * (16 bytes) chunks column-major..
+ */
+#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 12)
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
--
2.24.1.485.gad05a3d8e5
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
2021-10-12 8:28 Stanislav Lisovskiy
@ 2021-10-13 16:18 ` Ramalingam C
0 siblings, 0 replies; 28+ messages in thread
From: Ramalingam C @ 2021-10-13 16:18 UTC (permalink / raw)
To: Stanislav Lisovskiy
Cc: intel-gfx, jani.saarinen, matthew.d.roper, ville.syrjala
On 2021-10-12 at 11:28:45 +0300, Stanislav Lisovskiy wrote:
> TileF(Tile4 in bspec) format is 4K tile organized into
> 64B subtiles with same basic shape as for legacy TileY
> which will be supported by Display13.
>
> v2: - Fixed wrong case condition(Jani Nikula)
> - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
>
> v3: - s/I915_TILING_F/TILING_4/g
> - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
> - Removed unneeded fencing code
>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 ++
> drivers/gpu/drm/i915/display/intel_fb.c | 7 ++++
> drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> .../drm/i915/display/skl_universal_plane.c | 36 ++++++++++++++-----
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 1 +
> include/uapi/drm/drm_fourcc.h | 8 +++++
> 10 files changed, 50 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 4f0badb11bbb..524a20fa67ce 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1325,6 +1325,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
> case DRM_FORMAT_MOD_LINEAR:
> case I915_FORMAT_MOD_X_TILED:
> case I915_FORMAT_MOD_Y_TILED:
> + case I915_FORMAT_MOD_4_TILED:
> break;
> default:
> drm_dbg(&dev_priv->drm,
> @@ -9330,6 +9331,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
> case I915_FORMAT_MOD_X_TILED:
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Yf_TILED:
> + case I915_FORMAT_MOD_4_TILED:
> break;
> default:
> drm_dbg_kms(&i915->drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> index fa1f375e696b..e19739fef825 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -127,6 +127,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> return 128;
> else
> return 512;
> + case I915_FORMAT_MOD_4_TILED:
> + /*
> + * Each 4K tile consists of 64B(8*8) subtiles, with
> + * same shape as Y Tile(i.e 4*16B OWords)
> + */
> + return 128;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> if (is_ccs_plane(fb, color_plane))
> return 128;
> @@ -305,6 +311,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Yf_TILED_CCS:
> case I915_FORMAT_MOD_Y_TILED:
> + case I915_FORMAT_MOD_4_TILED:
> case I915_FORMAT_MOD_Yf_TILED:
> return 1 * 1024 * 1024;
> default:
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 1f66de77a6b1..f079a771f802 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -747,6 +747,7 @@ static bool tiling_is_valid(struct drm_i915_private *dev_priv,
> case DRM_FORMAT_MOD_LINEAR:
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Yf_TILED:
> + case I915_FORMAT_MOD_4_TILED:
> return DISPLAY_VER(dev_priv) >= 9;
> case I915_FORMAT_MOD_X_TILED:
> return true;
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index a0e53a3b267a..586aa660ba7a 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -207,6 +207,13 @@ static const u64 adlp_step_a_plane_format_modifiers[] = {
> DRM_FORMAT_MOD_INVALID
> };
>
> +static const u64 dg2_plane_format_modifiers[] = {
> + I915_FORMAT_MOD_X_TILED,
> + I915_FORMAT_MOD_4_TILED,
> + DRM_FORMAT_MOD_LINEAR,
> + DRM_FORMAT_MOD_INVALID
> +};
> +
> int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
> {
> switch (format) {
> @@ -795,6 +802,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> return PLANE_CTL_TILED_X;
> case I915_FORMAT_MOD_Y_TILED:
> return PLANE_CTL_TILED_Y;
> + case I915_FORMAT_MOD_4_TILED:
> + return PLANE_CTL_TILED_F;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> @@ -1288,6 +1297,7 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
> fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
> fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
> + fb->modifier == I915_FORMAT_MOD_4_TILED ||
> fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
> @@ -1989,6 +1999,10 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> return false;
> break;
> + case I915_FORMAT_MOD_4_TILED:
> + if (!HAS_FTILE(dev_priv))
> + return false;
> + break;
> default:
> return false;
> }
> @@ -2029,9 +2043,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> case DRM_FORMAT_Y216:
> case DRM_FORMAT_XVYU12_16161616:
> case DRM_FORMAT_XVYU16161616:
> - if (modifier == DRM_FORMAT_MOD_LINEAR ||
> - modifier == I915_FORMAT_MOD_X_TILED ||
> - modifier == I915_FORMAT_MOD_Y_TILED)
> + if (!is_ccs_modifier(modifier))
> return true;
> fallthrough;
> default:
> @@ -2042,8 +2054,10 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> static const u64 *gen12_get_plane_modifiers(struct drm_i915_private *dev_priv,
> enum plane_id plane_id)
> {
> + if (HAS_FTILE(dev_priv))
> + return dg2_plane_format_modifiers;
> /* Wa_22011186057 */
> - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> + else if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> return adlp_step_a_plane_format_modifiers;
> else if (gen12_plane_supports_mc_ccs(dev_priv, plane_id))
> return gen12_plane_format_modifiers_mc_ccs;
> @@ -2313,11 +2327,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> else
> fb->modifier = I915_FORMAT_MOD_Y_TILED;
> break;
> - case PLANE_CTL_TILED_YF:
> - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> - else
> - fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_F on XE_LPD+ */
> + if (DISPLAY_VER(dev_priv) >= 13) {
> + fb->modifier = I915_FORMAT_MOD_4_TILED;
> + } else {
> + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> + else
> + fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> + }
> break;
> default:
> MISSING_CASE(tiling);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 12256218634f..674fe16decf1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1628,6 +1628,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
>
> #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
> +#define HAS_FTILE(dev_priv) (INTEL_INFO(dev_priv)->has_ftile)
Is it ok to mention Ftile here?
> #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
> #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
> #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 169837de395d..4fa712bc99f9 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -972,6 +972,7 @@ static const struct intel_device_info adl_p_info = {
> .display.has_cdclk_crawl = 1,
> .display.has_modular_fia = 1,
> .display.has_psr_hw_tracking = 0,
> + .has_ftile = 1, \
Same here...
> .platform_engine_mask =
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> .ppgtt_size = 48,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a897f4abea0c..5b97e6afe1bb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7197,6 +7197,7 @@ enum {
> #define PLANE_CTL_TILED_X (1 << 10)
> #define PLANE_CTL_TILED_Y (4 << 10)
> #define PLANE_CTL_TILED_YF (5 << 10)
> +#define PLANE_CTL_TILED_F (5 << 10)
And here..
Ram.
> #define PLANE_CTL_ASYNC_FLIP (1 << 9)
> #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 8e6f48d1eb7b..c462d2668f83 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -125,6 +125,7 @@ enum intel_ppgtt_type {
> func(has_64bit_reloc); \
> func(gpu_reset_clobbers_display); \
> func(has_reset_engine); \
> + func(has_ftile); \
> func(has_global_mocs); \
> func(has_gt_uc); \
> func(has_l3_dpf); \
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 8dbf8ec0d890..e2fa4cbfe023 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5376,6 +5376,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> }
>
> wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
> + modifier == I915_FORMAT_MOD_4_TILED ||
> modifier == I915_FORMAT_MOD_Yf_TILED ||
> modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 45a914850be0..982b0a9fa78b 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -558,6 +558,14 @@ extern "C" {
> * pitch is required to be a multiple of 4 tile widths.
> */
> #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> +/*
> + * Intel F-tiling(aka Tile4) layout
> + *
> + * This is a tiled layout using 4Kb tiles in row-major layout.
> + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
> + * (16 bytes) chunks column-major..
> + */
> +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 12)
>
> /*
> * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> --
> 2.24.1.485.gad05a3d8e5
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
@ 2021-10-12 8:28 Stanislav Lisovskiy
2021-10-13 16:18 ` Ramalingam C
0 siblings, 1 reply; 28+ messages in thread
From: Stanislav Lisovskiy @ 2021-10-12 8:28 UTC (permalink / raw)
To: intel-gfx
Cc: Stanislav.Lisovskiy, jani.saarinen, matthew.d.roper, ville.syrjala
TileF(Tile4 in bspec) format is 4K tile organized into
64B subtiles with same basic shape as for legacy TileY
which will be supported by Display13.
v2: - Fixed wrong case condition(Jani Nikula)
- Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
v3: - s/I915_TILING_F/TILING_4/g
- s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
- Removed unneeded fencing code
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 2 ++
drivers/gpu/drm/i915/display/intel_fb.c | 7 ++++
drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
.../drm/i915/display/skl_universal_plane.c | 36 ++++++++++++++-----
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 1 +
include/uapi/drm/drm_fourcc.h | 8 +++++
10 files changed, 50 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4f0badb11bbb..524a20fa67ce 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1325,6 +1325,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
+ case I915_FORMAT_MOD_4_TILED:
break;
default:
drm_dbg(&dev_priv->drm,
@@ -9330,6 +9331,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
+ case I915_FORMAT_MOD_4_TILED:
break;
default:
drm_dbg_kms(&i915->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index fa1f375e696b..e19739fef825 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -127,6 +127,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
return 128;
else
return 512;
+ case I915_FORMAT_MOD_4_TILED:
+ /*
+ * Each 4K tile consists of 64B(8*8) subtiles, with
+ * same shape as Y Tile(i.e 4*16B OWords)
+ */
+ return 128;
case I915_FORMAT_MOD_Y_TILED_CCS:
if (is_ccs_plane(fb, color_plane))
return 128;
@@ -305,6 +311,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED:
+ case I915_FORMAT_MOD_4_TILED:
case I915_FORMAT_MOD_Yf_TILED:
return 1 * 1024 * 1024;
default:
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 1f66de77a6b1..f079a771f802 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -747,6 +747,7 @@ static bool tiling_is_valid(struct drm_i915_private *dev_priv,
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
+ case I915_FORMAT_MOD_4_TILED:
return DISPLAY_VER(dev_priv) >= 9;
case I915_FORMAT_MOD_X_TILED:
return true;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index a0e53a3b267a..586aa660ba7a 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -207,6 +207,13 @@ static const u64 adlp_step_a_plane_format_modifiers[] = {
DRM_FORMAT_MOD_INVALID
};
+static const u64 dg2_plane_format_modifiers[] = {
+ I915_FORMAT_MOD_X_TILED,
+ I915_FORMAT_MOD_4_TILED,
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_INVALID
+};
+
int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
{
switch (format) {
@@ -795,6 +802,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
return PLANE_CTL_TILED_X;
case I915_FORMAT_MOD_Y_TILED:
return PLANE_CTL_TILED_Y;
+ case I915_FORMAT_MOD_4_TILED:
+ return PLANE_CTL_TILED_F;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
@@ -1288,6 +1297,7 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
+ fb->modifier == I915_FORMAT_MOD_4_TILED ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
@@ -1989,6 +1999,10 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
return false;
break;
+ case I915_FORMAT_MOD_4_TILED:
+ if (!HAS_FTILE(dev_priv))
+ return false;
+ break;
default:
return false;
}
@@ -2029,9 +2043,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_Y216:
case DRM_FORMAT_XVYU12_16161616:
case DRM_FORMAT_XVYU16161616:
- if (modifier == DRM_FORMAT_MOD_LINEAR ||
- modifier == I915_FORMAT_MOD_X_TILED ||
- modifier == I915_FORMAT_MOD_Y_TILED)
+ if (!is_ccs_modifier(modifier))
return true;
fallthrough;
default:
@@ -2042,8 +2054,10 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
static const u64 *gen12_get_plane_modifiers(struct drm_i915_private *dev_priv,
enum plane_id plane_id)
{
+ if (HAS_FTILE(dev_priv))
+ return dg2_plane_format_modifiers;
/* Wa_22011186057 */
- if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+ else if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
return adlp_step_a_plane_format_modifiers;
else if (gen12_plane_supports_mc_ccs(dev_priv, plane_id))
return gen12_plane_format_modifiers_mc_ccs;
@@ -2313,11 +2327,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
else
fb->modifier = I915_FORMAT_MOD_Y_TILED;
break;
- case PLANE_CTL_TILED_YF:
- if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
- fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
- else
- fb->modifier = I915_FORMAT_MOD_Yf_TILED;
+ case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_F on XE_LPD+ */
+ if (DISPLAY_VER(dev_priv) >= 13) {
+ fb->modifier = I915_FORMAT_MOD_4_TILED;
+ } else {
+ if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
+ fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
+ else
+ fb->modifier = I915_FORMAT_MOD_Yf_TILED;
+ }
break;
default:
MISSING_CASE(tiling);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 12256218634f..674fe16decf1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1628,6 +1628,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
#define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
+#define HAS_FTILE(dev_priv) (INTEL_INFO(dev_priv)->has_ftile)
#define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
#define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
#define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 169837de395d..4fa712bc99f9 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -972,6 +972,7 @@ static const struct intel_device_info adl_p_info = {
.display.has_cdclk_crawl = 1,
.display.has_modular_fia = 1,
.display.has_psr_hw_tracking = 0,
+ .has_ftile = 1, \
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
.ppgtt_size = 48,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a897f4abea0c..5b97e6afe1bb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7197,6 +7197,7 @@ enum {
#define PLANE_CTL_TILED_X (1 << 10)
#define PLANE_CTL_TILED_Y (4 << 10)
#define PLANE_CTL_TILED_YF (5 << 10)
+#define PLANE_CTL_TILED_F (5 << 10)
#define PLANE_CTL_ASYNC_FLIP (1 << 9)
#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 8e6f48d1eb7b..c462d2668f83 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -125,6 +125,7 @@ enum intel_ppgtt_type {
func(has_64bit_reloc); \
func(gpu_reset_clobbers_display); \
func(has_reset_engine); \
+ func(has_ftile); \
func(has_global_mocs); \
func(has_gt_uc); \
func(has_l3_dpf); \
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8dbf8ec0d890..e2fa4cbfe023 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5376,6 +5376,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
}
wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
+ modifier == I915_FORMAT_MOD_4_TILED ||
modifier == I915_FORMAT_MOD_Yf_TILED ||
modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 45a914850be0..982b0a9fa78b 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -558,6 +558,14 @@ extern "C" {
* pitch is required to be a multiple of 4 tile widths.
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
+/*
+ * Intel F-tiling(aka Tile4) layout
+ *
+ * This is a tiled layout using 4Kb tiles in row-major layout.
+ * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
+ * (16 bytes) chunks column-major..
+ */
+#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 12)
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
--
2.24.1.485.gad05a3d8e5
^ permalink raw reply related [flat|nested] 28+ messages in thread
end of thread, other threads:[~2021-11-25 11:10 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-11-22 21:14 [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support Stanislav Lisovskiy
2021-11-22 21:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: Tile 4 plane format support (rev5) Patchwork
2021-11-22 21:40 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-11-22 22:08 ` [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support Nanley Chery
2021-11-23 8:13 ` Lisovskiy, Stanislav
2021-11-23 12:41 ` Chery, Nanley G
2021-11-23 13:36 ` Lisovskiy, Stanislav
2021-11-23 15:06 ` Chery, Nanley G
2021-11-23 15:22 ` Lisovskiy, Stanislav
2021-11-23 15:59 ` Chery, Nanley G
2021-11-23 16:20 ` Imre Deak
2021-11-22 22:14 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dg2: Tile 4 plane format support (rev5) Patchwork
2021-11-23 3:36 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2021-11-25 11:10 [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support Stanislav Lisovskiy
2021-11-18 12:24 Stanislav Lisovskiy
2021-11-17 11:01 Stanislav Lisovskiy
2021-11-17 14:33 ` Imre Deak
2021-10-27 15:46 Stanislav Lisovskiy
2021-10-27 16:56 ` Imre Deak
2021-10-28 6:58 ` Lisovskiy, Stanislav
2021-10-28 7:39 ` Imre Deak
2021-10-28 7:49 ` Lisovskiy, Stanislav
2021-10-28 7:53 ` Imre Deak
2021-10-28 7:57 ` Lisovskiy, Stanislav
2021-10-27 20:33 ` Ramalingam C
2021-10-28 7:02 ` Lisovskiy, Stanislav
2021-10-12 8:28 Stanislav Lisovskiy
2021-10-13 16:18 ` Ramalingam C
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