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Date:   Tue, 23 Nov 2021 11:48:53 -0600
From:   Bjorn Helgaas <helgaas@kernel.org>
To:     Ben Widawsky <ben.widawsky@intel.com>
Cc:     Jonathan Cameron <Jonathan.Cameron@huawei.com>,
        linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
        Alison Schofield <alison.schofield@intel.com>,
        Dan Williams <dan.j.williams@intel.com>,
        Ira Weiny <ira.weiny@intel.com>,
        Vishal Verma <vishal.l.verma@intel.com>
Subject: Re: [PATCH 18/23] cxl/pci: Implement wait for media active
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On Tue, Nov 23, 2021 at 08:04:13AM -0800, Ben Widawsky wrote:
> On 21-11-23 11:09:34, Jonathan Cameron wrote:
> > On Mon, 22 Nov 2021 14:57:51 -0800
> > Ben Widawsky <ben.widawsky@intel.com> wrote:
> > 
> > > On 21-11-22 17:03:35, Jonathan Cameron wrote:
> > > > On Fri, 19 Nov 2021 16:02:45 -0800
> > > > Ben Widawsky <ben.widawsky@intel.com> wrote:
> > > >   
> > > > > CXL 2.0 8.1.3.8.2 defines "Memory_Active: When set,
> > > > > indicates that the CXL Range 1 memory is fully initialized
> > > > > and available for software use.  Must be set within Range 1.
> > > > > Memory_Active_Timeout of deassertion of  
> > ...
> > Ah, got it. Maybe Range 1: Memory Active timeout ?
> 
> I can, but this is just quoted from the spec. Would this be better:
> 
> The CXL Type 3 Memory Device Software Guide (Revision 1.0) describes the
> need to check media active before using HDM. CXL 2.0 8.1.3.8.2 states:
> 
>   Memory_Active: When set, indicates that the CXL Range 1 memory is
>   fully initialized and available for software use. Must be set within
>   Range 1. Memory_Active_Timeout of deassertion of reset to CXL device
>   if CXL.mem HwInit Mode=1

That is some weird wording.  I stumbled over that, too.  I like the
quote format better, but I still don't know what it means.

That last piece ("Memory_Active_Timeout of deassertion ...") purports
to be a sentence, but is not.