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envelope-from=figlesia@xilinx.com; helo=NAM11-DM6-obe.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, frasse.iglesias@gmail.com, alistair@alistair23.me, alistair23@gmail.com, philmd@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi, This series attempts to add support for Xilinx Versal's PMC SLCR (system-level control registers) and OSPI flash memory controller to Xilinx Versal virt machine. The series start with adding a model of Versal's PMC SLCR and connecting the model to the Versal virt machine. The series then adds a couple of headers into the xlnx_csu_dma.h needed for building and reusing it later with the OSPI. The series thereafter introduces a DMA control interface and implements the interface in the xlnx_csu_dma for being able to reuse and control the DMA with the OSPI controller. Thereafter a model of Versal's OSPI controller is added and connected to the Versal virt machine. The series then ends with adding initial support for the Micron Xccelera mt35xu01g flash and flashes of this type are connected to the OSPI in the Versal virt machine. Best regards, Francisco Iglesias Changelog: v2 -> v3 * Correct and also include hw/sysbus.h and hw/register.h into xlnx_csu_dma.h (patch: "include/hw/dma/xlnx_csu_dma: Add in missing includes in the header") v1 -> v2 * Correct the reset in the PMC SLCR model * Create a sub structure for the OSPI in the Versal structure (in patch: "hw/arm/xlnx-versal: Connect the OSPI flash memory controller model") * Change to use 'drive_get' instead of 'drive_get_next' (in patch: "hw/arm/xlnx-versal-virt: Connect mt35xu01g flashes to the OSPI") * Add a maintainers patch and list myself as maintainer for the OSPI controller Francisco Iglesias (10): hw/misc: Add a model of Versal's PMC SLCR hw/arm/xlnx-versal: Connect Versal's PMC SLCR include/hw/dma/xlnx_csu_dma: Add in missing includes in the header hw/dma: Add the DMA control interface hw/dma/xlnx_csu_dma: Implement the DMA control interface hw/ssi: Add a model of Xilinx Versal's OSPI flash memory controller hw/arm/xlnx-versal: Connect the OSPI flash memory controller model hw/block/m25p80: Add support for Micron Xccela flash mt35xu01g hw/arm/xlnx-versal-virt: Connect mt35xu01g flashes to the OSPI MAINTAINERS: Add an entry for Xilinx Versal OSPI MAINTAINERS | 6 + hw/arm/xlnx-versal-virt.c | 23 + hw/arm/xlnx-versal.c | 105 ++ hw/block/m25p80.c | 2 + hw/dma/dma-ctrl.c | 31 + hw/dma/meson.build | 1 + hw/dma/xlnx_csu_dma.c | 32 + hw/misc/meson.build | 5 +- hw/misc/xlnx-versal-pmc-iou-slcr.c | 1445 +++++++++++++++++++++ hw/ssi/meson.build | 1 + hw/ssi/xlnx-versal-ospi.c | 1892 ++++++++++++++++++++++++++++ include/hw/arm/xlnx-versal.h | 26 + include/hw/dma/dma-ctrl.h | 74 ++ include/hw/dma/xlnx_csu_dma.h | 9 + include/hw/misc/xlnx-versal-pmc-iou-slcr.h | 51 + include/hw/ssi/xlnx-versal-ospi.h | 86 ++ 16 files changed, 3788 insertions(+), 1 deletion(-) create mode 100644 hw/dma/dma-ctrl.c create mode 100644 hw/misc/xlnx-versal-pmc-iou-slcr.c create mode 100644 hw/ssi/xlnx-versal-ospi.c create mode 100644 include/hw/dma/dma-ctrl.h create mode 100644 include/hw/misc/xlnx-versal-pmc-iou-slcr.h create mode 100644 include/hw/ssi/xlnx-versal-ospi.h -- 2.11.0