Re: [PATCH 18/23] cxl/pci: Implement wait for media active

[Jonathan Cameron <Jonathan.Cameron@huawei.com>]

On Mon, 22 Nov 2021 17:03:35 +0000
Jonathan Cameron <Jonathan.Cameron@Huawei.com> wrote:

> On Fri, 19 Nov 2021 16:02:45 -0800
> Ben Widawsky <ben.widawsky@intel.com> wrote:
> 
> > CXL 2.0 8.1.3.8.2 defines "Memory_Active: When set, indicates that the
> > CXL Range 1 memory is fully initialized and available for software use.
> > Must be set within Range 1. Memory_Active_Timeout of deassertion of  
> 
> Range 1?
> 
> > reset to CXL device if CXL.mem HwInit Mode=1" The CXL* Type 3 Memory
> > Device Software Guide (Revision 1.0) further describes the need to check
> > this bit before using HDM.
> > 
> > Unfortunately, Memory_Active can take quite a long time depending on
> > media size (up to 256s per 2.0 spec). Since the cxl_pci driver doesn't
> > care about this, a callback is exported as part of driver state for use
> > by drivers that do care.
> > 
> > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>  
> 
> Same thing about size not being used...
> 
> > ---
> > This patch did not exist in RFCv2
> > ---
> >  drivers/cxl/cxlmem.h |  1 +
> >  drivers/cxl/pci.c    | 56 ++++++++++++++++++++++++++++++++++++++++++++
> >  2 files changed, 57 insertions(+)
> > 
> > diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> > index eac5528ccaae..a9424dd4e5c3 100644
> > --- a/drivers/cxl/cxlmem.h
> > +++ b/drivers/cxl/cxlmem.h
> > @@ -167,6 +167,7 @@ struct cxl_dev_state {
> >  	struct cxl_endpoint_dvsec_info *info;
> >  
> >  	int (*mbox_send)(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd);
> > +	int (*wait_media_ready)(struct cxl_dev_state *cxlds);

Missing docs for this. 

Jonathan