[PATCH] mtd: rawnand: arasan: Fix clock rate in NV-DDR

[Olga Kitaina <okitain@gmail.com>]

According to the Arasan NAND controller spec,
the flash clock rate for SDR must be <= 100 MHz,
while for NV-DDR it must be the same as the rate
of the CLK line for the mode.
The driver previously always set 100 MHz for NV-DDR, which
would result in incorrect behavior for NV-DDR modes 0-4.

The appropriate clock rate can be calculated
from the NV-DDR timing parameters as 1/tCK, or for rates
measured in picoseconds, 10^12 / nand_nvddr_timings->tCK_min.

Signed-off-by: Olga Kitaina <okitain@gmail.com>
---
 drivers/mtd/nand/raw/arasan-nand-controller.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/raw/arasan-nand-controller.c b/drivers/mtd/nand/raw/arasan-nand-controller.c
index 53bd10738418..ed4ee9942441 100644
--- a/drivers/mtd/nand/raw/arasan-nand-controller.c
+++ b/drivers/mtd/nand/raw/arasan-nand-controller.c
@@ -18,6 +18,7 @@
 #include <linux/gpio/consumer.h>
 #include <linux/interrupt.h>
 #include <linux/iopoll.h>
+#include <linux/math64.h>
 #include <linux/module.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
@@ -1043,7 +1044,12 @@ static int anfc_setup_interface(struct nand_chip *chip, int target,
 				 DQS_BUFF_SEL_OUT(dqs_mode);
 	}
 
-	anand->clk = ANFC_XLNX_SDR_DFLT_CORE_CLK;
+	if (nand_interface_is_sdr)
+		anand->clk = ANFC_XLNX_SDR_DFLT_CORE_CLK;
+	else
+		/* ONFI timings are defined in picoseconds */
+		anand->clk = div_u64((u64)NSEC_PER_SEC * 1000,
+				     conf->timings.nvddr.tCK_min);
 
 	/*
 	 * Due to a hardware bug in the ZynqMP SoC, SDR timing modes 0-1 work

base-commit: f53d4c109a666bf1a4883b45d546fba079258717
-- 
2.20.1


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